CN111292671A - Data driving circuit, driving method thereof and display device - Google Patents
Data driving circuit, driving method thereof and display device Download PDFInfo
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- CN111292671A CN111292671A CN202010241115.5A CN202010241115A CN111292671A CN 111292671 A CN111292671 A CN 111292671A CN 202010241115 A CN202010241115 A CN 202010241115A CN 111292671 A CN111292671 A CN 111292671A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
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Abstract
The invention provides a data driving circuit, a driving method thereof and a display device, wherein the data driving circuit comprises: the latch comprises a first decoder electrically connected with the output end of the latch, a first level conversion unit connected with the output end of the first decoder, and N +1 first-stage data selectors connected with the output end of the first level conversion unit; the second decoder is electrically connected with the output end of the latch, the second level conversion unit is connected with the output end of the second decoder, and the second-stage data selector is connected with the output end of the second level conversion unit; the output end of the first-stage data selector is electrically connected with the input end of the second-stage data selector, and the output end of the second-stage data selector is electrically connected with the pixel circuit. The data driving circuit, the driving method thereof and the display device provided by the invention can not only facilitate the improvement of the refresh rate of the display device, but also reduce the production cost of the display device.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a data driving circuit, a driving method thereof, and a display device.
Background
Currently, the trend of demands for display devices such as smart phones, tablet computers, and the like is large size, high resolution, and high refresh rate. However, as the refresh rate of the display device increases, the speed of outputting the gray scale signal from the data driving circuit increases, and in the related art, the speed of outputting the gray scale signal from the data driving circuit is slow, which restricts the improvement of the refresh rate of the display device.
Disclosure of Invention
Embodiments of the present invention provide a data driving circuit, a driving method thereof, and a display device, so as to solve a problem in the related art that as resolution increases, the number of channels or the number of data driving circuits needs to be correspondingly increased by the data driving circuit, which increases the production cost of the display device.
In order to solve the above technical problems, the present invention provides the following technical solutions:
in a first aspect, an embodiment of the present invention provides a data driving circuit, including a latch and a plurality of digital-to-analog converters; wherein each digital-to-analog converter comprises:
the latch comprises a first decoder electrically connected with the output end of the latch, a first level conversion unit connected with the output end of the first decoder, and N +1 first-stage data selectors connected with the output end of the first level conversion unit; n is a positive even number;
the second decoder is electrically connected with the output end of the latch, the second level conversion unit is connected with the output end of the second decoder, and the second-stage data selector is connected with the output end of the second level conversion unit;
the output ends of the N +1 first-stage data selectors are electrically connected with the input end of the second-stage data selector, and the output end of the second-stage data selector is electrically connected with the pixel circuit.
Further, the second-level data selector comprises a first data selection unit and a second data selection unit;
the input end of the first data selection unit is electrically connected with the output ends of the 1 st to Nth first-stage data selectors respectively, and the output end of the first data selection unit is electrically connected with the pixel circuit;
the input end of the second data selection unit is electrically connected with the output ends of the 2 nd to the (N + 1) th first-stage data selectors respectively, and the output end of the second data selection unit is electrically connected with the pixel circuit.
The digital-to-analog converter further comprises a first output buffer connected with the output end of the digital-to-analog converter and a plurality of sampling controllers connected with the output end of the first output buffer;
each sampling controller comprises a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, a first signal line and a second signal line;
the first end of the first switch is electrically connected with the output end of the first output buffer, and the second end of the first switch is electrically connected with the first end of the second switch;
a first end of the third switch is electrically connected with the output end of the first output buffer, and a second end of the third switch is electrically connected with a first end of the fourth switch;
a second end of the fourth switch is electrically connected with a second end of the second switch, and is used for outputting a sampling voltage to the pixel circuit;
one end of the first capacitor is electrically connected with the second end of the first switch, and the other end of the first capacitor is electrically connected with a grounding end;
one end of the second capacitor is electrically connected with the second end of the third switch, and the other end of the second capacitor is electrically connected with a grounding end;
the control end of the first switch and the control end of the fourth switch are electrically connected with the first signal line, the control end of the second switch and the control end of the third switch are electrically connected with the second signal line, and the voltage on the first signal line is opposite to the voltage on the second signal line.
Furthermore, the pixel circuit further comprises a second output buffer, wherein an input end of the second output buffer is electrically connected with a second end of the fourth switch, and an output end of the second output buffer is electrically connected with the pixel circuit.
Furthermore, a control switch is also connected in series between each sampling controller and the output end of the first output buffer;
the control switches are respectively electrically connected with the control signal lines in a one-to-one correspondence manner and are used for controlling the connection or disconnection between the sampling controller and the output end of the first output buffer under the control of control signals provided by the control signal lines connected with each other.
Further, the first output buffer includes a byte controller and an output buffer unit;
the byte controller comprises 3 control units, a first input end of each control unit is electrically connected with an output end of the first data selection unit, a second input end of the byte controller is electrically connected with an output end of the second data selection unit, an output end of the byte controller is electrically connected with an input end of the output buffer unit, and an output end of the output buffer unit is electrically connected with the sampling controllers;
the control end of each control unit is electrically connected with the output end of the latch and is used for controlling the output end of the control unit to output the signal output by the first data selection unit or the signal output by the second data selection unit under the control of the digital signal provided by the latch.
Further, the latch comprises a first layer latch unit and a second layer latch unit;
the second-layer latch unit comprises Y second-stage latch unit groups, each second-stage latch unit group comprises N second-stage latch units, and Y is a positive integer;
the first-layer latch unit comprises Y multiplied by N first-stage latch units, and output ends of the Y multiplied by N first-stage latch units are respectively and electrically connected with input ends of the Y second-stage latch unit groups.
Furthermore, the number of the digital-to-analog converters is Y, and the input ends of the Y digital-to-analog converters are electrically connected with the output ends of the Y second-stage latch unit groups in a one-to-one correspondence manner.
In a second aspect, an embodiment of the present invention further provides a display device, including the data driving circuit as described in any one of the above.
In a second aspect, an embodiment of the present invention further provides a control method for a data driving circuit, which is applied to the data driving circuit described in any one of the above, the method including:
controlling N +1 first-stage data selectors to respectively receive input voltage and data signals and output N +1 pre-selection signals;
and controlling a second-stage data selector to receive the N +1 pre-selection signals and output gray scale signals.
In the technical scheme provided by the invention, the digital-to-analog converter is designed into the first-stage data selector and the second-stage data selector, compared with the digital-to-analog conversion in a form of a switch tree in the related art, the number of switches of signals in the data converter in the process of converting data signals into gray-scale signals is reduced, namely, the turning time of the switches in the data converter can be reduced, the speed of converting the data signals into the gray-scale signals in the data driving circuit is improved, and the refresh rate of the display device is further improved; meanwhile, compared with the related art, the number of switches of the data converter is reduced, so that the area of the data driving circuit can be further reduced, and the production cost of the display device can be reduced. Therefore, the technical scheme provided by the invention not only can facilitate the improvement of the refresh rate of the display device, but also can reduce the production cost of the display device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a data driving circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a digital-to-analog converter in a data driving circuit according to another embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a connection between a data driving circuit and a pixel circuit according to another embodiment of the invention;
FIG. 4 is a schematic diagram of a digital-to-analog converter of a 10-bit switch tree in the related art;
fig. 5 is a schematic structural diagram of a sampling controller in a data driving circuit according to another embodiment of the present invention;
fig. 6 is a timing diagram illustrating structures in the sampling and outputting process of the data driving circuit according to another embodiment of the present invention;
FIG. 7 is a timing diagram of control signal lines in a data driving circuit according to another embodiment of the present invention;
fig. 8 is a schematic structural diagram of a first output buffer in a data driving circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a data driving circuit 100, as shown in fig. 1 and fig. 2, including a latch 110 and a plurality of digital-to-analog converters 120; wherein each digital-to-analog converter 120 comprises:
a first decoder 121 electrically connected to an output terminal of the latch 110, a first level shift unit 122 connected to an output terminal of the first decoder 121, and N +1 first-stage data selectors 123 connected to an output terminal of the first level shift unit 122; n is a positive even number;
a second decoder 124 electrically connected to an output terminal of the latch 110, a second level shift unit 125 connected to an output terminal of the second decoder 124, and a second stage data selector 126 connected to an output terminal of the second level shift unit 125;
the output ends of the N +1 first-stage data selectors 123 are all electrically connected to the input end of the second-stage data selector 126, and the output end of the second-stage data selector 126 is electrically connected to the pixel circuit.
In the embodiment of the invention, the digital-to-analog converter is designed into the first-stage data selector and the second-stage data selector, compared with the digital-to-analog conversion in the form of a switch tree in the related art, the number of switches of signals in the data converter in the process of converting data signals into gray-scale signals is reduced, that is, the turning time of the switches in the data converter can be reduced, the speed of converting the data signals into the gray-scale signals in the data driving circuit is improved, and the refresh rate of the display device is further improved; meanwhile, compared with the related art, the number of switches of the data converter is reduced, so that the area of the data driving circuit can be further reduced, and the production cost of the display device can be reduced. Therefore, the technical scheme provided by the invention not only can facilitate the improvement of the refresh rate of the display device, but also can reduce the production cost of the display device.
As shown in fig. 3, the data driving circuit 100 is configured to receive image data acquired by a Timing Controller (TCON)310 and output a gray-scale signal to the pixel circuit 320 based on the image data, so as to drive the light emitting device in the pixel circuit to emit light, thereby implementing display of the display device.
Specifically, as shown in fig. 1, the data driving circuit 100 may further include an interface circuit 130, a shift register (shift register)140, a latch (latch)110, a digital-to-analog converter (DAC) 120, a first output buffer (buffer)150, and the like.
The interface circuit 130 is configured to receive image data sent by the TCON, the shift register 140 is configured to collect a data signal output by the interface circuit, the latch 110 is configured to store a data signal of one scan line, the digital-to-analog converter 120 is configured to convert the digital signal into a gray-scale signal for driving the pixel circuit, and the first output buffer 150 is configured to improve driving capability.
The interface circuit 130 may be a Low Voltage Differential Signaling (LVDS) interface, a Clock Embedded Differential Signaling (CEDS) interface, and the like, which is not limited herein. The interface circuit 130 is configured to receive image data of the TCON and convert the differential signal into a digital signal. The transmission speed of the interface circuit 130 may be above 1Gbps in order to cope with the real-time transmission demand of large-sized high-resolution data.
The first decoder 121 may decode a first predetermined data bit of the data signal provided by the latch 110, and the second decoder 124 may decode a second predetermined data bit of the data signal provided by the latch 110, where the first predetermined data bit and the second predetermined data bit do not overlap. For example: the latch 110 provides a 10-bit data signal, and the first decoder 121 decodes the 7 th to 10 th data bits in the 10-bit data signal and provides the decoded data to the first level shifter 122; the second decoder 124 decodes the 3 rd to 6 th data bits in the 10-bit data signal and supplies to the second level shifter 125.
The first level shifter 122 converts the voltage into a voltage suitable for the first stage data selector 123 based on the decoded signal supplied from the first decoder 121, and supplies the voltage to the first stage data selector 123. The second level shifter 125 converts the voltage into a voltage suitable for the second stage data selector 126 based on the decoded signal provided from the second decoder 124, and provides the voltage to the second stage data selector 126.
The N +1 first-stage data selectors 123 may be data selectors (MUX) each of which selects 1 by N, that is, each first-stage data selector 123 includes N switches, output ends of the N switches are connected, and input ends of the N switches are respectively electrically connected to the latch 110, for example: as shown in fig. 2, each first-level data selector 123 is a 1-out-of-16 data selector, i.e., N-16. In addition, the N +1 first-stage data selectors 123 may be arranged in a reverse order coding manner.
The second level data selector 126 may be a 2-out-of-M data selector, where M is a positive even number. The digital-to-analog converter 120 in the embodiment of the present invention may be a resistive digital-to-analog converter.
Taking N as an example of 16, the first decoder 121 simultaneously outputs the data to 17 data selectors selecting 1 from 16 through the first level shifter 122. The 17 1-out-of-16 first-stage data selectors 123 are arranged in a reverse order coding, each first-stage data selector 123 comprises 16 switches, the voltage provided to the 1 st first-stage data selector 123 may be V0<0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240>, the voltage provided to the 2 nd first-stage data selector 123 may be V1<1, 17, 33, 49, 65, 81, 97, 113, 129, 145, 161, 177, 193, 209, 225, 241> … …, and so on, the voltage provided to the 16 th first-stage data selector 123 may be V15<15, 31, 47, 63, 79, 95, 111, 127, 143, 159, 175, 191, 207, 223, 239, 255, and the voltage provided to the 17 th first-stage data selector 123 may be V16<16, 32, 48, 96, 112, 144, 160, 176, 192, 208, 224, 240, 256 >.
The voltages with different magnitudes can be obtained by providing the data driving circuit with a resistance voltage dividing circuit (R-string), and are realized by providing different voltages obtained by voltage division to the input ends of the switches.
In the embodiment of the present invention, the number of switches that the signal undergoes in the data converter during the process of converting the data signal into the gray scale signal is 2 (one switch that undergoes the first level data selector 123 and one switch that undergoes the second level data selector 126), i.e. n is 2, and the formula of the calculation of the switching flip time of the dac 120 is TDAC＝Ron×Cp×[n(n+1)/2]The switching turnover time of the data converter in fig. 2 can be calculated to be 3Ron*CpWherein R isonTo switch internal resistance, CpIs the parasitic capacitance of the switch.
In the related art, the switching inversion time period of the dac 120 accounts for 70% of the total time period from the data driving circuit receiving the data signal to outputting the gray-scale signal, which limits the speed of the data driving circuit outputting the gray-scale signal.
As shown in fig. 4, which is a schematic structural diagram of a digital-to-analog converter of a 10-bit switch tree in the related art, the number of switches experienced by a signal in the data converter during the process of converting a data signal into a gray-scale signal is 10, that is, n is 10, and the signal passes through TDAC＝Ron×Cp×[n(n+1)/2]The switching flip time of the data converter in fig. 4 can be found to be 55Ron Cp.
The comparison shows that the switching turn-over time of the data converter provided by the embodiment of the invention is shorter than that of the data converter in the related art, and the embodiment of the invention can greatly improve the speed of converting the data signal into the gray scale signal in the data driving circuit, thereby being convenient for improving the refresh rate of the display device.
It can be further found that the number of switches of the data converter in the related art is greater than that of the data converter in the embodiment of the present invention. In the related art, the DAC occupies a relatively large area in the data driving circuit, which causes a problem of a relatively large area of the data driving circuit, thereby increasing the cost of the driving circuit and increasing the packaging difficulty of the data driving circuit in the display device. The data driving circuit provided by the embodiment of the invention greatly reduces the number of the switches of the DAC, is beneficial to miniaturization of the data driving circuit, and can reduce the generation cost of the display device and reduce the packaging difficulty of the driving circuit.
Further, as shown in fig. 2, the second level data selector 126 includes a first data selecting unit 1261 and a second data selecting unit 1262;
the input end of the first data selection unit 1261 is electrically connected to the output ends of the 1 st first-stage data selector 123 to the nth first-stage data selector 123, respectively, and the output end of the first data selection unit 1261 is electrically connected to the pixel circuit 320;
the input terminals of the second data selection unit 1262 are electrically connected to the output terminals of the 2 nd to (N + 1) th first-stage data selectors 123, respectively, and the output terminal of the second data selection unit 1262 is electrically connected to the pixel circuit 320.
As shown in fig. 2, in the present embodiment, the second-stage data selector 126 is used for outputting two signals, i.e., a high-level gray-scale signal and a low-level gray-scale signal.
Specifically, the first data selecting unit 1261 and the second data selecting unit 1262 are both data selecting units of 1 in N. The second level shifter unit 125 supplies voltages to the first data selection unit 1261 and the second data selection unit 1262, respectively.
The input ends of N switches of the first data selection unit 1261 are electrically connected with the output end of the 1 st first-stage data selector to the output end of the Nth first-stage data selector in a one-to-one correspondence manner, and the output end of the first data selection unit outputs a low-level gray scale signal; the input ends of N switches of the second data selection unit are electrically connected with the output end of the 2 nd first-stage data selector to the output end of the (N + 1) th first-stage data selector in a one-to-one correspondence mode, and the output end of the second data selection unit outputs high-level gray scale signals.
Further, as shown in fig. 2 and 5, a first output buffer 150 connected to an output terminal of the digital-to-analog converter 120 and a plurality of sampling controllers 160 connected to output terminals of the first output buffer 150 are further included;
each sampling controller 160 includes a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, a first capacitor C1, a second capacitor C2, a first signal line X, and a second signal line Y;
a first terminal of the first switch Q1 is electrically connected with the output terminal of the first output buffer 150, and a second terminal of the first switch Q1 is electrically connected with the first terminal of the second switch;
a first terminal of the third switch Q3 is electrically connected with the output terminal of the first output buffer 150, and a second terminal of the third switch Q3 is electrically connected with a first terminal of the fourth switch Q4;
a second terminal of the fourth switch Q4 is electrically connected to a second terminal of the second switch for outputting a sampled voltage to the pixel circuit;
one end of the first capacitor C1 is electrically connected to the second end of the first switch Q1, and the other end of the first capacitor C1 is electrically connected to the ground;
one end of the second capacitor C2 is electrically connected to the second end of the third switch Q3, and the other end of the second capacitor is electrically connected to the ground;
a control terminal of the first switch Q1 and a control terminal of the fourth switch Q4 are electrically connected to the first signal line, a control terminal of the second switch and a control terminal of the third switch Q3 are electrically connected to the second signal line, and a voltage on the first signal line is opposite to a voltage on the second signal line.
In this embodiment, the first output buffer 150 connected to the output end of the dac 120 can improve the driving capability of the gray-scale signal output by the dac 120.
The on-off of the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 are controlled by controlling the voltage on the first signal line X and the second signal line Y, so that the sampling of the first capacitor C1 is controlled, the output of the second capacitor C2 or the output of the first capacitor C1 is controlled, and the sampling of the second capacitor C2 is controlled.
Specifically, when the first signal line X provides a high voltage signal and the second signal line Y provides a low voltage signal, the first capacitor C1 outputs and the second capacitor C2 samples; when the first signal line X provides a low voltage signal and the second signal line Y provides a high voltage signal, the first capacitor C1 samples and the second capacitor C2 outputs.
Each digital-to-analog converter 120 successively outputs N gray scale signals within a line time, and the sampling control circuit performs double sampling output under the control of the voltage provided by the first signal line X and the second signal line Y when receiving each gray scale signal.
For example, in row a, the first signal line X provides a high signal, the output of the DAC is sampled by the second capacitor C2, and the signal delivered at this time is that of the previous row (a-1) and the first capacitor C1 is present. When the first signal line X provides a low level signal when the row A +1 is in, the output of the DAC is sampled by the first capacitor C1, and the signal of the second capacitor C2 exists in the previous row (A) is transmitted at the moment, and the sampling is always alternated (as shown in figure 6), so that the operational amplifier establishing time can be shortened, or the output stability can be improved within the fixed DAC refreshing time.
Further, a second output buffer 170 is included, an input terminal of the second output buffer 170 is electrically connected to the second terminal of the fourth switch Q4, and an output terminal of the second output buffer 170 is electrically connected to the pixel circuit.
The driving capability of the gray-scale signal output from the sampling controller 160 to the pixel circuit can be improved by adding the second output buffer 170.
Further, as shown in fig. 1, a control switch K is also connected in series between each sampling controller 160 and the output end of the first output buffer 150;
the plurality of control switches K are electrically connected to the plurality of control signal lines Z in a one-to-one correspondence, and the control switches K are configured to control the connection or disconnection between the sampling controller 160 and the output terminal of the first output buffer 150 under the control of the control signal provided by the connected control signal line Z.
In this embodiment, the number of the control switches K is N, and the number of the control signal lines Z is equal to the number of the control switches K.
The N control signal lines Z are respectively electrically connected with the N control switches K in a one-to-one correspondence manner, and the N control switches K can be controlled to be sequentially switched on in a time-sharing manner within one line, so that the N sampling controllers 160 are controlled to be switched on in a time-sharing manner with the digital-to-analog converter 120.
N is 16, 16 control signal lines (Z1, Z2 … … Z15, Z16) are respectively and correspondingly electrically connected with 16 control switches K (K1, K2 … … K15, K16) one by one, and a book sequence diagram of the 16 control signal lines is shown in fig. 7, wherein the sum of high level time of the 16 control signal lines is less than the charging time of a row of sub-pixels.
Thus, under the condition that each dac 120 outputs N gray scale signals sequentially within the charging time of a row of sub-pixels, the N gray scale signals can enter the N sampling controllers 160 in a one-to-one correspondence manner, so that the sampling controllers 160 can complete sampling and output in a time-sharing manner.
Further, as shown in fig. 1 and 8, the first output buffer 150 includes a byte controller 151 and an output buffer unit 152;
the byte controller comprises 3 control units, a first input end of each control unit is electrically connected with an output end of the first data selection unit, a second input end of the byte controller is electrically connected with an output end of the second data selection unit, an output end of the byte controller is electrically connected with an input end of the output buffer unit, and an output end of the output buffer unit is electrically connected with the sampling controllers 160;
the control end of each control unit is electrically connected to the output end of the latch 110, and is configured to control the output end of the control unit to output a low-level gray scale signal or a high-level gray scale signal under the control of a third preset data bit of the data signal provided by the latch 110.
In this embodiment, taking a byte controller as a 2-bit controller as an example: as shown in fig. 8, the apparatus includes 6 transmission gates, each 2 transmission gates form a group of control units, and form 3 groups of control units, wherein the input terminals of the 2 transmission gates in the group of control units are respectively connected to the two outputs of the second-stage data selector 126, that is, the high-level gray scale signal and the low-level gray scale signal. The output ends of the 2 transmission gates are connected with one input end of the output buffer unit together.
The 3 sets of control units determine the output signal from the 1 st and 2 nd bit values of the 10bit data signal provided by the latch 110, respectively, and the output rule is as shown in table 1 below:
| |
00 | 01 | 10 | 11 |
| in1 | VL | VL | VL | VL |
| in2 | VL | VH | VL | VH |
| in3 | VL | VL | VH | VH |
| In4 | VL | VL | VH | VH |
TABLE 1
The output buffer unit includes 4 input terminals, and a first input terminal is directly connected to the output terminal of the first data selection unit of the second-stage data selector 126, so as to obtain a low-level gray-scale signal.
The other 3 input ends are respectively electrically connected with the output ends of the 3 groups of control units, and the output of the byte controller can be obtained based on the value that the 1 st bit of the 10-bit data signal surrounds the 2 nd bit according to the rule in the table 1.
The subsequent output buffer unit 152 determines the output signals according to the values of the 1 st bit and the 2 nd bit of the 10bit data signal provided by the latch 110, and the output rule is as shown in the following table 2:
| |
00 | 01 | 10 | 11 | |
| | VL | 3/4VL+1/ |
2/4VL+2/ |
1/4VL+3/4VH |
TABLE 2
Further, as shown in fig. 1, the latch 110110 includes a first layer latch unit 111 and a second layer latch unit;
the second-layer latch unit includes Y second-stage latch unit groups 112, each of which includes N second-stage latch units, and Y is a positive integer;
the first-layer latch unit comprises Y multiplied by N first-stage latch units, and output ends of the Y multiplied by N first-stage latch units are respectively and electrically connected with input ends of the Y second-stage latch unit groups.
In this embodiment, taking the resolution of the display device as 3840 × 2160, 20 data driving circuits are adopted, and each pixel includes 4 sub-pixels as an example: that is, each data driving circuit is responsible for 768(3840 ÷ 20 × 4) columns of subpixels, and the 768 columns can be divided into 48 groups of second-stage latch cells on average. Each of the second-stage latch unit groups includes 16 second-stage latch units therein. That is, Y is 48 and N is 16.
Further, the number of the digital-to-analog converters 120 is Y, and the input ends of the Y digital-to-analog converters 120 are electrically connected to the output ends of the Y second-stage latch unit groups in a one-to-one correspondence manner.
In this embodiment, the number of the digital-to-analog converters 120 is equal to the number of the second-stage latch unit groups, and taking the above-mentioned 48 second-stage latch unit groups as an example, the 48 second-stage latch unit groups provide data signals to the 48 digital-to-analog converters 120 in a one-to-one correspondence.
Each second-stage latch unit group 112 may send the data to the corresponding dac 120 after the data of the second-stage latch unit group 112 is in place, or the second-stage latch unit groups 112 may send the data of all the Y second-stage latch unit groups 112 to the corresponding dacs 120 in a unified manner after the data of all the Y second-stage latch unit groups 112 are in place.
The embodiment of the invention also provides a display device which comprises the pixel circuit.
The display device may be a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, etc.
An embodiment of the present invention further provides a control method for a data driving circuit, which is applied to the data driving circuit described above, and the method includes:
controlling N +1 first-stage data selectors to respectively receive input voltage and data signals and output N +1 pre-selection signals;
and controlling a second-stage data selector to receive the N +1 pre-selection signals and output gray scale signals.
In the embodiment of the invention, the digital-to-analog converter is designed into the first-stage data selector and the second-stage data selector, compared with the digital-to-analog conversion in the form of a switch tree in the related art, the number of switches of signals in the data converter in the process of converting data signals into gray-scale signals is reduced, that is, the turning time of the switches in the data converter can be reduced, the speed of converting the data signals into the gray-scale signals in the data driving circuit is improved, and the refresh rate of the display device is further improved; meanwhile, compared with the related art, the number of switches of the data converter is reduced, so that the area of the data driving circuit can be further reduced, and the production cost of the display device can be reduced. Therefore, the technical scheme provided by the invention not only can facilitate the improvement of the refresh rate of the display device, but also can reduce the production cost of the display device.
As shown in fig. 1 to 3, the data driving circuit 100 is configured to receive image data acquired by a Timing Controller (TCON)310 and output a gray-scale signal to the pixel circuit 320 based on the image data, so as to drive a light emitting device in the pixel circuit to emit light, thereby implementing display of the display device.
Specifically, as shown in fig. 1, the data driving circuit 100 may further include an interface circuit 130, a shift register (shift register)140, a latch (latch)110, a digital-to-analog converter (DAC) 120, a first output buffer (buffer)150, and the like.
The interface circuit 130 is configured to receive image data sent by the TCON, the shift register 140 is configured to collect a data signal output by the interface circuit, the latch 110 is configured to store a data signal of one scan line, the digital-to-analog converter 120 is configured to convert the digital signal into a gray-scale signal for driving the pixel circuit, and the first output buffer 150 is configured to improve driving capability.
The interface circuit 130 may be a Low Voltage Differential Signaling (LVDS) interface, a Clock Embedded Differential Signaling (CEDS) interface, and the like, which is not limited herein. The interface circuit 130 is configured to receive image data of the TCON and convert the differential signal into a digital signal. The transmission speed of the interface circuit 130 may be above 1Gbps in order to cope with the real-time transmission demand of large-sized high-resolution data.
The first decoder 121 may decode a first predetermined data bit of the data signal provided by the latch 110, and the second decoder 124 may decode a second predetermined data bit of the data signal provided by the latch 110, where the first predetermined data bit and the second predetermined data bit do not overlap. For example: the latch 110 provides a 10-bit data signal, and the first decoder 121 decodes the 7 th to 10 th data bits in the 10-bit data signal and provides the decoded data to the first level shifter 122; the second decoder 124 decodes the 3 rd to 6 th data bits in the 10-bit data signal and supplies to the second level shifter 125.
The first level shifter 122 converts the voltage into a voltage suitable for the first stage data selector 123 based on the decoded signal supplied from the first decoder 121, and supplies the voltage to the first stage data selector 123. The second level shifter 125 converts the voltage into a voltage suitable for the second stage data selector 126 based on the decoded signal provided from the second decoder 124, and provides the voltage to the second stage data selector 126.
The N +1 first-stage data selectors 123 may be data selectors (MUX) each of which selects 1 by N, that is, each first-stage data selector 123 includes N switches, output ends of the N switches are connected, and input ends of the N switches are respectively electrically connected to the latch 110, for example: as shown in fig. 2, each first-level data selector 123 is a 1-out-of-16 data selector, i.e., N-16. In addition, the N +1 first-stage data selectors 123 may be arranged in a reverse order coding manner.
The second level data selector 126 may be a 2-out-of-M data selector, where M is a positive even number. The digital-to-analog converter 120 in the embodiment of the present invention may be a resistive digital-to-analog converter.
Taking N as an example of 16, the first decoder 121 simultaneously outputs the data to 17 data selectors selecting 1 from 16 through the first level shifter 122. The 17 1-out-of-16 first-stage data selectors 123 are arranged in a reverse order coding, each first-stage data selector 123 comprises 16 switches, the voltage provided to the 1 st first-stage data selector 123 may be V0<0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240>, the voltage provided to the 2 nd first-stage data selector 123 may be V1<1, 17, 33, 49, 65, 81, 97, 113, 129, 145, 161, 177, 193, 209, 225, 241> … …, and so on, the voltage provided to the 16 th first-stage data selector 123 may be V15<15, 31, 47, 63, 79, 95, 111, 127, 143, 159, 175, 191, 207, 223, 239, 255, and the voltage provided to the 17 th first-stage data selector 123 may be V16<16, 32, 48, 96, 112, 144, 160, 176, 192, 208, 224, 240, 256 >.
The voltages with different magnitudes can be obtained by providing the data driving circuit with a resistance voltage dividing circuit (R-string), and are realized by providing different voltages obtained by voltage division to the input ends of the switches.
In the embodiment of the present invention, the number of switches that the signal undergoes in the data converter during the process of converting the data signal into the gray scale signal is 2 (one switch that undergoes the first level data selector 123 and one switch that undergoes the second level data selector 126), i.e. n is 2, and the formula of the calculation of the switching flip time of the dac 120 is TDAC＝Ron×Cp×[n(n+1)/2]The switching turnover time of the data converter in fig. 2 can be calculated to be 3Ron*CpWherein R isonTo switch internal resistance, CpIs the parasitic capacitance of the switch.
In the related art, the switching inversion time period of the dac 120 accounts for 70% of the total time period from the data driving circuit receiving the data signal to outputting the gray-scale signal, which limits the speed of the data driving circuit outputting the gray-scale signal.
As shown in fig. 4, which is a schematic structural diagram of a digital-to-analog converter of a 10-bit switch tree in the related art, the number of switches experienced by a signal in the data converter during the process of converting a data signal into a gray-scale signal is 10, that is, n is 10, and the signal passes through TDAC＝Ron×Cp×[n(n+1)/2]The switching flip time of the data converter in fig. 4 can be found to be 55Ron Cp.
The comparison shows that the switching turn-over time of the data converter provided by the embodiment of the invention is shorter than that of the data converter in the related art, and the embodiment of the invention can greatly improve the speed of converting the data signal into the gray scale signal in the data driving circuit, thereby being convenient for improving the refresh rate of the display device.
It can be further found that the number of switches of the data converter in the related art is greater than that of the data converter in the embodiment of the present invention. In the related art, the DAC occupies a relatively large area in the data driving circuit, which causes a problem of a relatively large area of the data driving circuit, thereby increasing the cost of the driving circuit and increasing the packaging difficulty of the data driving circuit in the display device. The data driving circuit provided by the embodiment of the invention greatly reduces the number of the switches of the DAC, is beneficial to miniaturization of the data driving circuit, and can reduce the generation cost of the display device and reduce the packaging difficulty of the driving circuit.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A data driving circuit includes a latch and a plurality of digital-to-analog converters; wherein each digital-to-analog converter comprises:
the latch comprises a first decoder electrically connected with the output end of the latch, a first level conversion unit connected with the output end of the first decoder, and N +1 first-stage data selectors connected with the output end of the first level conversion unit; n is a positive even number;
the second decoder is electrically connected with the output end of the latch, the second level conversion unit is connected with the output end of the second decoder, and the second-stage data selector is connected with the output end of the second level conversion unit;
the output ends of the N +1 first-stage data selectors are electrically connected with the input end of the second-stage data selector, and the output end of the second-stage data selector is electrically connected with the pixel circuit.
2. The data driving circuit according to claim 1, wherein the second-stage data selector includes a first data selection unit and a second data selection unit;
the input end of the first data selection unit is electrically connected with the output ends of the 1 st to Nth first-stage data selectors respectively, and the output end of the first data selection unit is electrically connected with the pixel circuit;
the input end of the second data selection unit is electrically connected with the output ends of the 2 nd to the (N + 1) th first-stage data selectors respectively, and the output end of the second data selection unit is electrically connected with the pixel circuit.
3. The data driving circuit according to claim 2, further comprising a first output buffer connected to an output terminal of the digital-to-analog converter and a plurality of sampling controllers connected to an output terminal of the first output buffer;
each sampling controller comprises a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, a first signal line and a second signal line;
the first end of the first switch is electrically connected with the output end of the first output buffer, and the second end of the first switch is electrically connected with the first end of the second switch;
a first end of the third switch is electrically connected with the output end of the first output buffer, and a second end of the third switch is electrically connected with a first end of the fourth switch;
a second end of the fourth switch is electrically connected with a second end of the second switch, and is used for outputting a sampling voltage to the pixel circuit;
one end of the first capacitor is electrically connected with the second end of the first switch, and the other end of the first capacitor is electrically connected with a grounding end;
one end of the second capacitor is electrically connected with the second end of the third switch, and the other end of the second capacitor is electrically connected with a grounding end;
the control end of the first switch and the control end of the fourth switch are electrically connected with the first signal line, the control end of the second switch and the control end of the third switch are electrically connected with the second signal line, and the voltage on the first signal line is opposite to the voltage on the second signal line.
4. The data driving circuit of claim 3, further comprising a second output buffer, wherein an input terminal of the second output buffer is electrically connected to the second terminal of the fourth switch, and an output terminal of the second output buffer is electrically connected to the pixel circuit.
5. The data driving circuit according to claim 3, wherein a control switch is further connected in series between each sampling controller and the output end of the first output buffer;
the control switches are respectively electrically connected with the control signal lines in a one-to-one correspondence manner and are used for controlling the connection or disconnection between the sampling controller and the output end of the first output buffer under the control of control signals provided by the control signal lines connected with each other.
6. The data driving circuit according to claim 3, wherein the first output buffer includes a byte controller and an output buffer unit;
the byte controller comprises 3 control units, a first input end of each control unit is electrically connected with an output end of the first data selection unit, a second input end of the byte controller is electrically connected with an output end of the second data selection unit, an output end of the byte controller is electrically connected with an input end of the output buffer unit, and an output end of the output buffer unit is electrically connected with the sampling controllers;
the control end of each control unit is electrically connected with the output end of the latch and is used for controlling the output end of the control unit to output the signal output by the first data selection unit or the signal output by the second data selection unit under the control of the digital signal provided by the latch.
7. The data driving circuit according to claim 1, wherein the latch includes a first-layer latch unit and a second-layer latch unit;
the second-layer latch unit comprises Y second-stage latch unit groups, each second-stage latch unit group comprises N second-stage latch units, and Y is a positive integer;
the first-layer latch unit comprises Y multiplied by N first-stage latch units, and output ends of the Y multiplied by N first-stage latch units are respectively and electrically connected with input ends of the Y second-stage latch unit groups.
8. The data driving circuit according to claim 7, wherein the number of the digital-to-analog converters is Y, and the input ends of the Y digital-to-analog converters are electrically connected to the output ends of the Y second-stage latch unit groups in a one-to-one correspondence.
9. A display device comprising the data driving circuit according to any one of claims 1 to 8.
10. A control method of a data driving circuit, applied to the data driving circuit according to any one of claims 1 to 8, the method comprising:
controlling N +1 first-stage data selectors to respectively receive input voltage and data signals and output N +1 pre-selection signals;
and controlling a second-stage data selector to receive the N +1 pre-selection signals and output gray scale signals.
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