CN111277248B - Synchronous pulse generating device with multiple working modes and working method thereof - Google Patents
Synchronous pulse generating device with multiple working modes and working method thereof Download PDFInfo
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- CN111277248B CN111277248B CN202010258253.4A CN202010258253A CN111277248B CN 111277248 B CN111277248 B CN 111277248B CN 202010258253 A CN202010258253 A CN 202010258253A CN 111277248 B CN111277248 B CN 111277248B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
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Abstract
The invention relates to a synchronous pulse generating device with multiple working modes and a working method thereof, wherein the synchronous pulse generating device comprises the following components: the device comprises an upper computer control module, an external trigger signal generation module, an external clock input module, a communication module, an FPGA module and an output driving module; the upper computer control module is connected with the FPGA module through the communication module and is used for sending required pulse parameters; the external trigger signal generation module is connected with the FPGA module and used for providing an external trigger signal; the external clock input module is connected with the FPGA module and used for generating an input clock signal conforming to the FPGA module; the FPGA module is used for generating synchronous pulses conforming to corresponding pulse parameters according to the pulse parameters sent by the upper computer control module or the pulse parameters carried by the external trigger signals; the output driving module is used for providing a multichannel pulse signal according to the synchronous pulse output by the FPGA module. The invention can be widely applied to the field of synchronous pulse generating devices.
Description
Technical Field
The invention relates to a multi-working-mode synchronous pulse generating device and a working method thereof, which can be applied to the fields of proton and heavy ion beam pulse mode linear accelerators, laser targeting, spectrum analysis instruments, ion mass spectrometers and the like.
Background
The heavy ion beam is widely applied to the research fields of heavy ion biological effect, heavy ion cancer treatment, material science, single particle effect of aerospace devices and the like. The linac for proton, heavy ion beam devices is operated in pulsed mode. The linear accelerator has high acceleration gradient, good beam quality, strong beam and high transmission efficiency, and has important effect on the research of multiple high-charge-state and high-energy heavy nuclear beams such as bismuth, uranium and the like. The synchronous pulse generating device with multiple working modes can provide accurate pulse signals (pulse signals with adjustable period, pulse width and time delay among all paths) according with the working time sequence of the physical beam adjustment requirement for a linear accelerator chopper system with the pulse mode, a low-level system of a high-frequency transmitter and a beam diagnosis and feedback system. The chopper system switches the direct current beam into a pulse beam current conforming to a certain time structure according to the requirements of physical beam adjusting personnel according to the pulse signals provided by the synchronous pulse generating device; the low-level system of the high-frequency transmitter responds to the pulse signal of the synchronous pulse generating device to generate a periodic radio-frequency excitation signal to act on the high-frequency transmitter, so that a high-frequency cavity of the linear accelerator establishes an accelerating electric field in advance to accelerate the beam passing through the chopper system; and the beam diagnosis and feedback system accurately acquires the beam emittance and the beam intensity according to the pulse signals provided by the synchronous pulse generating device. It follows that the synchronization pulse generating means is an indispensable system for a pulse-mode linac.
At present, most of pulse mode linear accelerators adopt a general synchronous pulse generating device, such as BNC745T of the United states Stanford Research Systems company, the delay precision can reach ps level, the precision is high, the functions are multiple, the triggering mode is adjustable, the functions of a multifunctional display interface and keys are achieved, but the number of output channels of a single pulse mode linear accelerator of the general synchronous pulse generating device cannot meet the requirement of the pulse mode linear accelerator on synchronous triggering signals, the pulse mode linear accelerator cannot respond to external optical fiber triggering signals, and the pulse mode linear accelerator has the advantages of complex structure, large volume, high cost and no utilization of system expansion and maintenance. The domestic research on the synchronous pulse generating device is still a certain gap compared with foreign ones, and the domestic synchronous pulse generating device is generally developed for specific purposes.
The linear accelerator system in the pulse mode requires that the synchronous pulse generating device can output multi-channel synchronous pulses, the pulse width and the time delay of each channel of output channels can be independently adjusted, the time delay precision is 1us, and the period of each channel of output channels can be adjusted. In addition, because the pulse mode linear accelerator system is huge and the electromagnetic environment is complex, the synchronous pulse generator is required to have a reliable long-distance external optical fiber case triggering function, the free triggering mode and the given optical case triggering mode can be freely switched, and the period, pulse width and delay parameters, the synchronous pulse polarity and the working mode can be controlled through a computer remote interface. The current synchronous pulse generating device cannot meet the requirements.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a multi-working-mode synchronous pulse generating device and a working method thereof, wherein the device has multiple output channels, each output channel can perform independent remote configuration of parameters, and the requirements of a pulse-mode linear accelerator are met.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
in a first aspect of the present invention, there is provided a multi-operation mode synchronization pulse generating apparatus comprising: the device comprises an upper computer control module, an external trigger signal generation module, an external clock input module, a communication module, an FPGA module and an output driving module; the upper computer control module is connected with the FPGA module through the communication module and is used for sending a control instruction to the FPGA module, wherein the control instruction comprises a synchronous pulse parameter and a working mode, and the synchronous pulse parameter comprises pulse width, delay and period; the external trigger signal generation module is connected with the FPGA module and is used for providing an external light instance or an electric signal trigger signal; the external clock input module is connected with the FPGA module and is used for generating an input clock signal conforming to the FPGA module; the FPGA module is used for generating synchronous pulses conforming to corresponding pulse parameters in a given working mode according to the control instruction sent by the upper computer control module; the output driving module is used for providing a multichannel synchronous pulse signal according to the synchronous pulse output by the FPGA module.
Further, the upper computer control module comprises a pulse parameter setting module, a working mode setting module and a computer display interface; the pulse parameter setting module is used for setting the pulse width, delay and period of each path of pulse output by the FPGA module and sending the pulse to the FPGA module through the communication module; the working mode setting module is used for setting the working modes of the FPGA module, and comprises a free triggering mode and a given signal triggering mode; the computer display interface is used for displaying the set pulse parameters and the working modes.
Further, the external trigger signal generation module comprises an external light instance trigger signal input unit and an external electric signal trigger input unit; the external light instance trigger signal input unit comprises an external light instance input interface and an optical receiver which are connected with each other, wherein the external light instance input interface is connected with the external trigger input port and is used for receiving an external trigger light instance; the optical receiver is used for carrying out photoelectric conversion on the external triggering light instance and then sending the external triggering light instance to the FPGA module; the external electric signal trigger input unit comprises an external electric signal input interface and a level conversion chip which are connected with each other, wherein the external electric signal input interface is connected with the external trigger input port and is used for receiving an external trigger electric signal; the level conversion chip is used for carrying out level conversion on an external trigger electric signal and then sending the external trigger electric signal to the FPGA module.
Further, the external clock input module comprises a radio frequency power attenuation circuit and a level conversion unit; the radio frequency power attenuation circuit is connected with an external clock input port and is used for processing an external clock signal to enable the external clock signal to reach the signal amplitude required by the FPGA module and match with the input and output impedance; the level conversion unit is connected with the radio frequency power attenuation circuit and the FPGA module and is used for converting a clock signal sent by the radio frequency power attenuation circuit into an input level signal conforming to the FPGA module and then sending the input level signal to the FPGA module.
Further, the communication module comprises a network interface and a network interface chip, wherein the network interface adopts an RJ45 interface with a network isolation transformer; the network interface chip adopts an Ethernet controller which is internally integrated with a TCP/IP protocol stack, an Ethernet medium transmission layer and a physical layer.
Further, the FPGA module comprises an external light instance trigger signal analysis unit, a PLL unit, a TCP communication server end, an SRAM controller and a synchronous pulse output unit; the external light instance trigger signal analysis unit is connected with the external trigger signal generation module and is used for analyzing the input 32-bit wide light instance under a given signal trigger mode, comparing the analyzed light instance number with a pre-stored light instance number in the external instance trigger signal analysis unit, and sending a signal to the synchronous pulse output unit to output synchronous pulse if the pre-stored light instance number is met, otherwise, the synchronous pulse is not operated; the PLL unit is connected with the external clock input module, processes the clock signal input by the external clock input module and then is used as the working clock of the FPGA module; the TCP communication server side is used for receiving the period, pulse width and delay parameters issued by the upper computer control module in a free triggering mode or a given signal triggering working mode and sending the period, pulse width and delay parameters to the synchronous pulse output unit; the SRAM controller unit is used for data caching as TCP Ethernet communication; the synchronous pulse output unit is used for completing synchronous pulse output of corresponding pulse parameters according to the received period, pulse width and delay parameters.
Further, the output driving module comprises 28 paths of synchronous pulse output driving units, namely a trigger source pulse output driving unit and other 27 paths of synchronous pulse output driving units, wherein the trigger source pulse output driving unit and each path of synchronous pulse output driving unit are respectively connected with corresponding synchronous pulse output ports.
Further, the multi-working-mode synchronous pulse generating device further comprises an optical fiber trigger signal output module, wherein the optical fiber trigger signal output module is used for being connected with a next-stage trigger device and used as a trigger signal of the next-stage trigger device.
Further, the optical fiber trigger signal output module comprises a high-speed high-current driving chip, an optical transmitter unit and an optical fiber trigger output interface, wherein the high-speed high-current driving chip is connected with the FPGA module and is used for increasing the driving capability of the output level of the FPGA module; the optical transmitter unit is used for converting the electric signal sent by the high-speed high-current driving chip into an optical signal, and then is connected with the next-stage triggering device through the external optical fiber triggering output interface to serve as a triggering signal of the next-stage triggering device.
In a second aspect of the present invention, there is provided a method of operating a synchronous pulse generating device in a multi-operation mode, comprising the steps of: 1) Starting a synchronous pulse generating device with multiple working modes and an upper computer control module, and establishing communication between the synchronous pulse generating device and the upper computer control module through a communication module; 2) Selecting a working mode of the synchronous pulse generating device in an upper computer control module according to actual requirements, and entering a step 3 if the working mode is a free triggering mode; if the signal trigger mode is given, entering step 4); 3) Setting the period of a trigger source pulse output channel, selecting a free trigger mode, namely a continuous pulse mode, and then respectively setting the delay, the pulse width and the polarity of output pulses of other synchronous pulse output channels except the trigger source pulse output channel according to requirements; 4) Setting delay, pulse width and polarity of output pulses of other synchronous pulse output channels except the trigger source pulse output channel, selecting a given signal trigger mode, namely a single pulse mode, and inputting given light instances through an external trigger input port; 5) The FPGA module analyzes the given light instance, and when the given light instance number is matched with the stored light instance number in the FPGA, synchronous pulse output signals with corresponding time structures are generated according to the received pulse parameters.
Due to the adoption of the technical scheme, the invention has the following advantages: 1. each output channel of the synchronous pulse generating device provided by the invention can be independently and remotely configured with parameters, and 28 paths of synchronous pulse output channels meet the requirements of a pulse mode linear accelerator. 2. The free triggering mode and the given signal triggering mode can be switched freely through the computer control interface, and the operation is simple. 3. The invention is provided with the external trigger signal generating module, can receive the external trigger mode triggered by the light instance under the given signal trigger mode, has long trigger signal transmission distance, strong anti-interference capability and short delay, improves the stability and reliability of the system, and is convenient for the system to be further expanded by the arrangement of the optical fiber trigger signal output module. 4. The circuit structure adopted by the invention is compact, the volume and the weight of the synchronous pulse generating device are greatly reduced, and the manufacturing cost of the synchronous pulse generating device is greatly reduced. Therefore, the invention can be widely applied to the fields of proton and heavy ion beam pulse mode linear accelerators, laser targeting, spectrum analysis instruments, ion mass spectrometers and the like.
Drawings
FIG. 1 is a block diagram of a synchronous pulse generator according to the present invention;
FIG. 2 is a block diagram of the external trigger signal generation module of FIG. 1;
FIG. 3 is a block diagram of the external clock input module of FIG. 1;
FIG. 4 is a block diagram of the communication module of FIG. 1;
FIG. 5 is a block diagram of the structure of the FPGA module of FIG. 1;
FIG. 6 is a block diagram of the output driver module of FIG. 1;
FIG. 7 is a block diagram of the fiber trigger signal output module of FIG. 1;
FIG. 8 is a timing diagram of the synchronous pulse output in the free trigger mode;
FIG. 9 is a flow chart of a programming process for receiving external light instance triggers in a given signal trigger mode.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings and examples.
As shown in fig. 1, the present invention provides a multi-operation mode synchronization pulse generating device, which includes: the device comprises an upper computer control module 1, an external trigger signal generation module 2, an external clock input module 3, a communication module 4, an FPGA module 5 and an output driving module 6. The upper computer control module 1 is connected with the FPGA module 5 through the communication module 4 and is used for sending a control instruction to the FPGA module 5, wherein the control instruction comprises synchronous pulse parameters (namely pulse width, delay and period) and a working mode command; the external trigger signal generation module 2 is connected with the FPGA module 5 and is used for providing external light cases or electric signal trigger signals; the external clock input module 3 is connected with the FPGA module 5 and is used for generating an input clock signal conforming to the FPGA module 5; the FPGA module 5 is used for generating synchronous pulses conforming to corresponding pulse parameters in a given working mode (namely a free trigger mode or a given signal trigger mode) according to the control instruction sent by the upper computer control module 1; the output driving module 6 is used for providing a multichannel synchronous pulse signal according to the synchronous pulse output by the FPGA module 5.
Furthermore, the upper computer control module 1 is realized by means of the design of a VC6.0 development platform. The upper computer control module 1 comprises a pulse parameter setting module, a working mode setting module and a computer display interface; the pulse parameter setting module is used for setting the pulse width, delay and period of each path of pulse output by the FPGA module 5 and sending the pulse to the FPGA module 5 through the communication module 4; the working mode setting module is used for setting the working modes of the FPGA module 5, and comprises a free triggering mode and a given signal triggering mode; the computer display interface is used for displaying the set pulse parameters and the set working modes.
Further, as shown in fig. 2, the external trigger signal generating module 2 includes an external light instance trigger signal input unit and an external electric signal trigger input unit; the external light instance trigger signal input unit comprises an external light instance input interface 21 and an optical receiver 22 which are connected with each other, wherein the external light instance input interface 21 is connected with an external trigger input port and is used for receiving an external trigger light instance; the optical receiver 22 is configured to perform photoelectric conversion on the external triggering light instance and send the external triggering light instance to the FPGA module 5; the external electric signal trigger input unit comprises an external electric signal input interface 23 and a level conversion chip 24 which are connected with each other, wherein the external electric signal input interface 23 is connected with the external trigger input port and is used for receiving an external trigger electric signal, and the level conversion chip 24 is used for carrying out level conversion on the external trigger electric signal and then sending the external trigger electric signal to the FPGA module 5.
Further, as shown in fig. 3, the external clock input module 3 includes a radio frequency power attenuation circuit 31 and a level conversion unit 32, where the radio frequency power attenuation circuit 31 is connected to an external clock input port, and is used to process an external clock signal to reach a signal amplitude required by the FPGA module 5, and match with an input/output impedance; the level conversion unit 32 is connected to the radio frequency power attenuation circuit 31 and the FPGA module 5, and is configured to convert a clock signal sent by the radio frequency power attenuation circuit 31 into an input level signal that conforms to the FPGA module 5, and then send the signal to the FPGA module 5 as a working clock of the FPGA module 5. Preferably, the external clock is typically an operating clock of the device triggered by the synchronization signal. By arranging the external clock input module 3, the clock signal input into the FPGA module 5 can be synchronized with the clock generated by the device triggered by the synchronizing signal, so that the purpose of reducing errors is achieved.
Further, as shown in fig. 4, the communication module 4 includes a network interface and a network interface chip. Preferably, the network interface in the invention adopts an RJ45 interface with a network isolation transformer. The network interface chip employs an ethernet controller with a TCP/IP protocol stack, an ethernet medium transport layer (MAC) and a physical layer (PHY) integrated therein.
Further, as shown in fig. 5, the FPGA module 5 includes an external light case trigger signal analyzing unit 51, a PLL unit 52, a TCP communication server 53, an SRAM controller 54, and a synchronization pulse output unit 55. The external light instance trigger signal analyzing unit 51 is connected to an external light instance trigger signal input unit in the external trigger signal generating module 2, and is configured to analyze a 32-bit wide light instance input to the FPGA module 5 in a given signal trigger mode (in the present invention, a given signal refers to a given light instance trigger signal), and compare the analyzed light instance number with a pre-stored light instance number in the external instance trigger signal analyzing unit 51, and if the pre-stored light instance number is met, send a signal to the synchronization pulse output unit 55 to output a synchronization pulse, otherwise, do not act; the PLL unit 52 is connected to the external clock input module 3, processes the clock signal input by the external clock input module 3, and then uses the processed clock signal as the working clock of the FPGA module 5; the TCP communication server 53 is configured to receive pulse parameters, i.e. period, pulse width, delay parameters, issued by the upper computer control module 1 through the communication module 4 in the free trigger mode or the given signal trigger mode, and send the pulse parameters to the synchronous pulse output unit 55; the SRAM controller unit 54 is configured to store a control command sent by the upper computer control module 1 as a data buffer for TCP ethernet communication; the synchronous pulse output unit 55 is used for completing synchronous pulse output of corresponding pulse parameters according to the received period, pulse width and delay parameters.
Furthermore, the FPGA module 5 may select a temperature compensation crystal oscillator signal of 50MHz of the pulse generating device of the present invention as the working clock of the FPGA module 5, or may select a clock processed by the external clock input module 3 as the working clock of the FPGA module 5.
Further, as shown in fig. 6, the output driving module 6 includes 28 paths of synchronous pulse output driving units, which are respectively a T0 channel output driving unit, a 1 channel output driving unit, a 2 channel output driving unit, and the like, where the 28 paths of output driving units are respectively connected to corresponding synchronous pulse output ports, and the T0 channel output port is used as a trigger source pulse output channel in the present invention. The output driving module 6 is used for completing the selection of the driving capability and polarity function of the synchronous pulse output signal. The 28 paths of synchronous pulse output can be independently set with the delay and pulse width parameters of each output channel through the upper computer control module 1 connected with the Ethernet. The delay resolution can reach 20ns, the period adjustable range can reach 10us-10s in the free triggering mode, and the output jitter is smaller than 20ns.
Furthermore, the multi-working-mode synchronous pulse generating device further comprises an optical fiber trigger signal output module 7, wherein the optical fiber trigger signal output module 7 can be connected with a next-stage trigger device to serve as a trigger signal of the next-stage trigger device, so that the system expansion is facilitated.
Further, as shown in fig. 7, the optical fiber trigger signal output module 7 includes a high-speed high-current driving chip 71, an optical transmitter unit 72, and an optical fiber trigger output interface 73, where the high-speed high-current driving chip 71 is connected to the FPGA module 5, and is used to increase the driving capability of the output level of the FPGA module 5; the optical transmitter unit 72 is used for converting the electrical signal sent by the high-speed high-current driving chip 71 into an optical signal, and then is connected with a next-stage triggering device through the external optical fiber triggering output interface 73 to serve as a triggering signal of the next-stage triggering device, so that the system is convenient to expand.
Based on the synchronous pulse generating device with multiple working modes, the invention also provides a working method of the synchronous pulse generating device with multiple working modes, which has two working modes of given signal triggering and free triggering, and specifically comprises the following steps:
1) The synchronous pulse generating device with multiple working modes is started, the upper computer control module 1 is started, and communication between the synchronous pulse generating device and the upper computer control module is established through the communication module 4;
2) Selecting a working mode of the synchronous pulse generating device in the upper computer control module 1 according to actual requirements, and entering a step 3 if the working mode is a free triggering mode; if the signal trigger mode is given, entering step 4);
3) Setting the period of a trigger source pulse output channel (in the invention, a T0 channel is used as the trigger source pulse output channel), selecting a free trigger working mode, namely a continuous pulse mode, and then respectively setting the delay, the pulse width and the polarity of output pulses of other synchronous pulse output channels except the trigger source pulse output channel according to requirements;
4) Setting delay, pulse width and polarity of output pulses of other synchronous pulse output channels except the trigger source pulse output channel, selecting a given signal trigger mode, namely a single pulse mode, and inputting given light instances through an external trigger input port;
5) As shown in fig. 8, the FPGA module 5 analyzes a given light instance, and when the given light instance number matches with the light instance number stored in the FPGA module, generates a synchronous pulse output signal with a corresponding time structure according to the received pulse parameter.
As shown in fig. 9, the processing procedure of the optical instance analysis unit in the FPGA module 5 is shown. By utilizing a 390KHz clock generated by frequency division of a temperature compensation crystal oscillator signal of 50MHz of the pulse generating device of the invention to sample an input signal, when the instance number of 32 bits of bit width accords with the trigger instance number of the pulse generating device of the invention, delay is started, the delay time is up, synchronous pulses with corresponding pulse width are output, and meanwhile, whether the pulse output in the trigger period is ended or not is judged, and the next trigger period is not responded under the condition of not ending. The light case triggering mode has the advantages of small attenuation, strong anti-interference capability, high safety performance, small volume and light weight, and particularly has incomparable advantages under the application of special electromagnetic environments such as long-distance transmission and accelerators. The external electric signal trigger input unit converts the external trigger level signal into a level signal conforming to LVCOMS (3.3V) through the high-speed level conversion chip and inputs the level signal into the FPGA module. The external light case trigger mode sync pulse output period is determined by the light case trigger period.
A specific embodiment is given above, but the invention is not limited to the described embodiment. The basic idea of the invention is that the above-mentioned scheme, it is not necessary for those skilled in the art to design various modified models, formulas, parameters according to the teaching of the present invention to take creative effort. Variations, modifications, substitutions and alterations are also possible in the embodiments without departing from the principles and spirit of the present invention.
Claims (6)
1. A synchronous pulse generating device with multiple working modes, which is characterized in that: it comprises the following steps:
the device comprises an upper computer control module, an external trigger signal generation module, an external clock input module, a communication module, an FPGA module and an output driving module;
the upper computer control module is connected with the FPGA module through the communication module and is used for sending a control instruction to the FPGA module, wherein the control instruction comprises a synchronous pulse parameter and a working mode, and the synchronous pulse parameter comprises pulse width, delay, period and polarity;
the external trigger signal generation module is connected with the FPGA module and is used for providing an external light instance or an electric signal trigger signal;
the external clock input module is connected with the FPGA module and is used for generating an input clock signal conforming to the FPGA module;
the FPGA module is used for generating synchronous pulses conforming to corresponding pulse parameters in a given working mode according to the control instruction sent by the upper computer control module;
the output driving module is used for providing a multichannel synchronous pulse signal according to the synchronous pulse output by the FPGA module;
the external trigger signal generation module comprises an external light instance trigger signal input unit and an external electric signal trigger input unit; the external light instance trigger signal input unit comprises an external light instance input interface and an optical receiver which are connected with each other, wherein the external light instance input interface is connected with the external trigger input port and is used for receiving an external trigger light instance; the optical receiver is used for performing photoelectric conversion on the external triggering light instance and then sending the external triggering light instance to the FPGA module; the external electric signal trigger input unit comprises an external electric signal input interface and a level conversion chip which are connected with each other, wherein the external electric signal input interface is connected with the external trigger input port and is used for receiving an external trigger electric signal; the level conversion chip is used for carrying out level conversion on the external trigger electric signal and then sending the external trigger electric signal to the FPGA module;
the external clock input module comprises a radio frequency power attenuation circuit and a level conversion unit; the radio frequency power attenuation circuit is connected with an external clock input port and is used for processing an external clock signal to enable the external clock signal to reach the signal amplitude required by the FPGA module and match with the input and output impedance; the level conversion unit is connected with the radio frequency power attenuation circuit and the FPGA module and is used for converting a clock signal sent by the radio frequency power attenuation circuit into an input level signal conforming to the FPGA module and then sending the input level signal to the FPGA module;
the communication module comprises a network interface and a network interface chip, wherein the network interface adopts an RJ45 interface with a network isolation transformer; the network interface chip adopts an Ethernet controller which is internally integrated with a TCP/IP protocol stack, an Ethernet medium transmission layer and a physical layer;
the FPGA module comprises an external light instance trigger signal analysis unit, a PLL unit, a TCP communication server end, an SRAM controller and a synchronous pulse output unit;
the external light instance trigger signal analysis unit is connected with the external trigger signal generation module and is used for analyzing the input 32-bit wide light instance under a given signal trigger mode, comparing the analyzed light instance number with a pre-stored light instance number in the external instance trigger signal analysis unit, and sending a signal to the synchronous pulse output unit to output synchronous pulse if the pre-stored light instance number is met, otherwise, the synchronous pulse is not operated;
the PLL unit is connected with the external clock input module, processes the clock signal input by the external clock input module and then is used as the working clock of the FPGA module;
the TCP communication server side is used for receiving the period, pulse width, delay and polarity parameters issued by the upper computer control module in a free triggering mode or a given signal triggering working mode and sending the period, pulse width, delay and polarity parameters to the synchronous pulse output unit;
the SRAM controller unit is used for data caching as TCP Ethernet communication;
the synchronous pulse output unit is used for completing synchronous pulse output of corresponding pulse parameters according to the received period, pulse width and delay parameters.
2. A multi-mode synchronous pulse generating device as defined in claim 1, wherein: the upper computer control module comprises a pulse parameter setting module, a working mode setting module and a computer display interface;
the pulse parameter setting module is used for setting the pulse width, delay, period and polarity of each path of pulse output by the FPGA module and sending the pulse to the FPGA module through the communication module;
the working mode setting module is used for setting the working modes of the FPGA module, and comprises a free triggering mode and a given signal triggering mode;
the computer display interface is used for displaying the set pulse parameters and the working modes.
3. A multi-mode synchronous pulse generating device as defined in claim 1, wherein: the output driving module comprises 28 paths of synchronous pulse output driving units, namely a trigger source pulse output driving unit and other 27 paths of synchronous pulse output driving units, wherein the trigger source pulse output driving unit and the paths of synchronous pulse output driving units are respectively connected with corresponding synchronous pulse output ports.
4. A multi-mode synchronous pulse generating device as defined in claim 1, wherein: the synchronous pulse generating device with multiple working modes further comprises an optical fiber trigger signal output module, wherein the optical fiber trigger signal output module is used for being connected with a next-stage trigger device and used as a trigger signal of the next-stage trigger device.
5. The multiple operation mode synchronization pulse generating device according to claim 4, wherein: the optical fiber trigger signal output module comprises a high-speed high-current driving chip, an optical transmitter unit and an optical fiber trigger output interface, wherein the high-speed high-current driving chip is connected with the FPGA module and is used for increasing the driving capability of the output level of the FPGA module; the optical transmitter unit is used for converting the electric signal sent by the high-speed high-current driving chip into an optical signal, and then is connected with the next-stage triggering device through the optical fiber triggering output interface to serve as a triggering signal of the next-stage triggering device.
6. A method of operating a synchronous pulse generating device employing a multiple operation mode as defined in any one of claims 1-5, comprising the steps of:
1) Starting a synchronous pulse generating device with multiple working modes and an upper computer control module, and establishing communication between the synchronous pulse generating device and the upper computer control module through a communication module;
2) Selecting a working mode of the synchronous pulse generating device in an upper computer control module according to actual requirements, and entering a step 3 if the working mode is a free triggering mode; if the signal trigger mode is given, entering step 4);
3) Setting the period of a trigger source pulse output channel, selecting a free trigger mode, namely a continuous pulse mode, and then respectively setting the delay, the pulse width and the polarity of output pulses of other synchronous pulse output channels except the trigger source pulse output channel according to requirements;
4) Setting delay, pulse width and polarity of output pulses of other synchronous pulse output channels except the trigger source pulse output channel, selecting a given signal trigger mode, namely a single pulse mode, and inputting given light instances through an external trigger input port;
5) The FPGA module analyzes the given light instance, and when the given light instance number is matched with the stored light instance number in the FPGA, synchronous pulse output signals with corresponding time structures are generated according to the received pulse parameters.
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| CN111751630A (en) * | 2020-07-07 | 2020-10-09 | 马玉丰 | Synchronous pulse generation method of mechanical arm antenna test system |
| CN112332810A (en) * | 2020-11-24 | 2021-02-05 | 无锡捷捷兴电子科技有限公司 | Multi-path high-power synchronous pulse output device |
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