CN111277234B - Power amplifier - Google Patents
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- CN111277234B CN111277234B CN202010278876.8A CN202010278876A CN111277234B CN 111277234 B CN111277234 B CN 111277234B CN 202010278876 A CN202010278876 A CN 202010278876A CN 111277234 B CN111277234 B CN 111277234B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a power amplifier, and belongs to the technical field of electronics and communication. The power amplifier is composed of a bias circuit formed by a CMOS circuit and a signal amplifying circuit formed by a silicon germanium heterojunction triode circuit. Wherein the bias circuit comprises a positive temperature coefficient current source circuit; a negative temperature coefficient current source circuit; a current mirror circuit which combines the received positive temperature coefficient current and negative temperature coefficient current into a current source with adjustable temperature coefficient, and then outputs the current source through an output end; a bias voltage circuit outputting a varying current according to a temperature coefficient adjustable current source; and the signal amplifying circuit adopts a silicon germanium heterojunction triode circuit to amplify and output the input radio frequency signal. When the invention is applied, the output power can be adjusted between-10 dBm and 30dBm, so that the invention can not only meet the low-power consumption application in low power, but also meet the application of high output power in special long-distance condition.
Description
Technical Field
The invention relates to the technical field of electronics and communication, in particular to a power amplifier.
Background
The output power of the conventional CMOS power amplifier for BLE (Bluetooth Low Energy) is about 0-10dBm, and the transmission distance is within 100 meters. Fig. 1 shows a conventional CMOS power amplifier circuit. Typically the breakdown voltage of a CMOS transistor is 3.3V (the breakdown voltage of a deep sub-micron CMOS device is around 1.2V-3.3V), the maximum swing of the output signal cannot exceed 3.3V, whereas for a class a power amplifier the output signal swing is equal to twice the supply voltage, when the supply voltage is around 1.2V, the output signal swing is around 2.4V. The class a power amplifier output power in this case is around 10 dBm. In addition, the CMOS cascode structure or the differential structure can improve the output power at a certain layering degree, but the output power is not more than 20dBm.
At low supply voltages, the conventional power amplifier requires very large current to output high power, resulting in increased transistor size, increased parasitic capacitance, and reduced operating efficiency. In addition, as the operating temperature of the power amplifier increases, the output power of the power amplifier decreases.
Disclosure of Invention
The invention mainly solves the technical problem of providing a power amplifier, which regulates and controls the current of the power amplifier so as to control the working temperature of the power amplifier, and can regulate and control the output power of the power amplifier between-10 dBm and 30 dBm.
In order to achieve the above purpose, the invention adopts a technical scheme that: there is provided a power amplifier characterized by comprising: a positive temperature coefficient current source circuit which outputs a positive temperature coefficient current; a negative temperature coefficient current source circuit which outputs a negative temperature coefficient current; a current mirror circuit that receives the positive temperature coefficient current and the negative temperature coefficient current and combines the two temperature coefficient currents into one temperature coefficient adjustable current source, the current mirror circuit outputting the temperature coefficient adjustable current source; a bias voltage circuit outputting a varying current according to a temperature coefficient adjustable current source; and the signal amplifying circuit adopts a silicon germanium heterojunction triode circuit to amplify the accessed radio frequency signal and outputs the amplified radio frequency signal, and the signal amplifying circuit is electrically connected with the bias voltage circuit.
The beneficial effects of the invention are as follows: the invention combines the CMOS process and the silicon germanium (SiGe) Heterojunction (HBT) triode process to design the power amplifier, and the power amplifier can adjust the output power between-10 dBm and 30dBm, thereby not only meeting the low-power consumption application in low power, but also meeting the application of high output power in special long-distance conditions.
Drawings
FIG. 1 is a schematic diagram of a conventional CMOS power amplifier circuit;
FIG. 2 is a schematic diagram of a power amplifier circuit of the present invention;
the components in the drawings are marked as follows: 1-first resistor, 2-first NMOS tube, 3-first PMOS tube, 4-second NMOS tube, 5-second PMOS tube, 6-second resistor, 7-third NMOS tube, 8-third PMOS tube, 9-fourth NMOS tube, 10-fourth PMOS tube, 11-fifth NMOS tube, 12-sixth NMOS tube, 13-fifth PMOS tube, 14-sixth PMOS tube, 15-seventh PMOS tube, 16-first capacitor, 17-first inductor, 18-second capacitor, 19-third resistor, 20-second inductor, 21-first triode, 22-third capacitor, 23-fourth resistor, 24-third inductor, 25-third triode, 26-second triode, 27-fourth capacitor and 28-fourth inductor.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making clear and defining the scope of the present invention.
It should be noted that the terms "first," "second," "third," and the like in the claims and description herein are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The design of the invention adopts the SiGe BiCMOS process, combines the BiCMOS process in the CMOS process and the silicon germanium (SiGe) Heterojunction (HBT) triode process, and not only utilizes the characteristic of high gain of the SiGe process, but also combines the characteristic of flexible control of the CMOS process. The invention adopts the SiGe HBT as the core part of the power amplifier, can greatly improve the output power of the power amplifier, and adopts the CMOS circuit to flexibly adjust the output current so as to adjust the paranoid voltage of the SiGe HBT amplifying circuit and further adjust the output power of the power amplifier.
Fig. 2 shows a specific embodiment of a power amplifier structure according to the present invention, in which the power amplifier mainly includes: the first resistor 1, the first NMOS tube 2, the first PMOS tube 3, the second NMOS tube 4, the second PMOS tube 5, the second resistor 6, the third NMOS tube 7, the third PMOS tube 8, the fourth NMOS tube 9, the fourth PMOS tube 10, the fifth NMOS tube 11, the sixth NMOS tube 12, the fifth PMOS tube 13, the sixth PMOS tube 14, the seventh PMOS tube 15, the first capacitor 16, the first inductor 17, the second capacitor 18, the third resistor 19, the second inductor 20, the first triode 21, the third capacitor 22, the fourth resistor 23, the third inductor 24, the third triode 25, the second triode 26, the fourth capacitor 27 and the fourth inductor 28. The amplifier is composed of a bias circuit module adopting a CMOS circuit and a signal amplifying module adopting a silicon germanium heterojunction triode circuit.
In one embodiment of the present invention, the CMOS bias circuit module provides a varying bias voltage to the signal amplification module, primarily by adjusting the magnitude of the output current. The CMOS bias circuit module comprises a positive temperature coefficient current source circuit, a negative temperature coefficient current source circuit, a current mirror circuit and a bias voltage circuit. Wherein, the positive temperature coefficient current source circuit outputs positive temperature coefficient current; the negative temperature coefficient current source circuit outputs a negative temperature coefficient current; the current mirror circuit receives the positive temperature coefficient current and the negative temperature coefficient current, combines the two temperature coefficient currents into a current source with adjustable temperature coefficient, and then outputs the current source; the bias voltage circuit receives the current source input by the current mirror circuit, and then outputs current with corresponding change according to the current source with adjustable temperature coefficient.
In one embodiment of the present invention, the positive temperature coefficient current source circuit mainly comprises a first resistor 1, a first NMOS transistor 2, a first PMOS transistor 3, a second NMOS transistor 4, and a second PMOS transistor 5.
One end of the first resistor 1 is connected with a working power supply and inputs positive temperature coefficient current, and the other end of the first resistor is connected with the drain electrode of the first NMOS tube 2. The drain electrode and the grid electrode of the first NMOS tube 2 are mutually communicated, and the source electrode of the first NMOS tube 2 is grounded. The source electrode of the first PMOS tube 3 is connected with a working power supply, and the grid electrode and the drain electrode of the first PMOS tube 3 are mutually communicated. The drain electrode of the second NMOS tube 4 is connected with the drain electrode of the first PMOS tube 3, the grid electrode of the second NMOS tube 4 is connected with the grid electrode of the first NMOS tube 2, and the source electrode of the second NMOS tube 4 is grounded. The source electrode of the second PMOS tube 5 is connected with a working power supply, the grid electrode of the second PMOS tube 5 is connected with the grid electrode of the first PMOS tube 3, and the drain electrode of the second PMOS tube 5 is connected with the drain electrode of the fifth NMOS tube 11 serving as the input end of the current mirror circuit. Preferably, when the aspect ratio of the second PMOS transistor 5 is adjusted to change, the magnitude of the drain output current of the second PMOS transistor changes accordingly.
In one embodiment of the present invention, the negative temperature coefficient current source circuit mainly comprises a second resistor 6, a third NMOS transistor 7, a third PMOS transistor 8, a fourth NMOS transistor 9, and a fourth PMOS transistor 10.
One end of the second resistor 6 is connected with the working power supply and inputs negative temperature coefficient current, and the other end of the second resistor is connected with the drain electrode of the third NMOS tube 7. The drain electrode and the grid electrode of the third NMOS tube 7 are mutually communicated, and the source electrode of the third NMOS tube 7 is grounded. The source electrode of the third PMOS tube 8 is connected with a working power supply, and the grid electrode and the drain electrode of the third PMOS tube 8 are mutually communicated. The drain electrode of the fourth NMOS tube 9 is connected with the drain electrode of the third PMOS tube 8, the grid electrode of the fourth NMOS tube 9 is connected with the grid electrode of the third NMOS tube 7, and the source electrode of the fourth NMOS tube 9 is grounded. The source electrode of the fourth PMOS tube 10 is connected with a working power supply, the grid electrode of the fourth PMOS tube 10 is connected with the grid electrode of the third PMOS tube 8, and the drain electrode of the fourth PMOS tube 10 is connected with the drain electrode of the fifth NMOS tube 11 serving as the input end of the current mirror circuit. Preferably, when the aspect ratio of the fourth PMOS transistor 10 is adjusted to change, the magnitude of the drain output current thereof changes accordingly.
In one embodiment of the present invention, the current mirror circuit is mainly composed of a fifth NMOS transistor 11 and a sixth NMOS transistor 12. The drain electrode of the fifth NMOS tube 11 is communicated with the grid electrode, the source electrode of the fifth NMOS tube 11 is grounded, and the drain electrode of the fifth NMOS tube 11 is connected with the drain electrode of the second PMOS tube 5 and the drain electrode of the fourth PMOS tube 10. The grid electrode of the sixth NMOS tube 12 is connected with the grid electrode of the fifth NMOS tube 11, the source electrode of the sixth NMOS tube 12 is grounded, and the drain electrode of the sixth NMOS tube 12 is connected with the grid electrode of the sixth PMOS tube 14 and the grid electrode of the seventh PMOS tube 15 in the bias voltage circuit.
The drain electrode of the fifth NMOS 11 is used as the input terminal of the current mirror circuit, which introduces a positive temperature coefficient current and a negative temperature coefficient current into the fifth NMOS 11, and the two currents are combined through the fifth NMOS 11 to form a current source with adjustable temperature coefficient. The current source is mirrored by the sixth NMOS transistor 12 and then transferred to the bias voltage circuit from the drain of the sixth NMOS transistor 12, which is the output of the current mirror circuit. Preferably, when the aspect ratio of the sixth NMOS transistor 12 is adjusted to change, the magnitude of the drain output current thereof changes accordingly.
In one embodiment of the present invention, the bias voltage circuit is mainly composed of a fifth PMOS transistor 13, a sixth PMOS transistor 14 and a seventh PMOS transistor 15. The drain electrode of the fifth PMOS tube 13 is connected with the output end (drain electrode of the sixth NMOS tube 12) of the current mirror circuit, the drain electrode and the grid electrode of the fifth PMOS tube 13 are mutually communicated, and the source electrode of the fifth PMOS tube 13 is connected with a working power supply. The source electrode of the sixth PMOS tube 14 is connected with a working power supply, the grid electrode of the sixth PMOS tube 14 is connected with the drain electrode of the fifth PMOS tube 13, and the drain electrode of the sixth PMOS tube 14 is connected with a third resistor 19 in the signal amplifying circuit. The source electrode of the seventh PMOS tube 15 is connected with a working power supply, the grid electrode of the seventh PMOS tube 15 is connected with the drain electrode of the fifth PMOS tube 13, and the drain electrode of the seventh PMOS tube 15 is connected with a fourth resistor 23 in the signal amplifying circuit. Preferably, when the aspect ratio of the sixth PMOS transistor 14 and/or the seventh PMOS transistor 15 is adjusted to change, the drain output current of the sixth PMOS transistor 14 and/or the seventh PMOS transistor 15 changes accordingly.
Because the grid electrode of the sixth PMOS transistor 14 and the grid electrode of the seventh PMOS transistor 15 are both connected to the drain electrode of the fifth PMOS transistor 13, and the drain electrode of the fifth PMOS transistor 13 is connected to the output end (the drain electrode of the sixth NMOS transistor 12) of the current mirror circuit, the grid electrode of the sixth PMOS transistor 14 and the grid electrode of the seventh PMOS transistor 15 can both receive the current source with adjustable temperature coefficient. Meanwhile, the aspect ratios of the sixth PMOS transistor 14 and the seventh PMOS transistor 15 can be adjusted, so that the current output by the drains of the sixth PMOS transistor 14 and the seventh PMOS transistor 15 can be adjusted according to actual needs, that is, the two paths of currents respectively provided by the sixth PMOS transistor 14 and the seventh PMOS transistor 15 for the signal amplifying circuit can be adjusted. The magnitude of the bias voltage in the signal amplifying circuit can be adjusted according to actual requirements.
In a specific embodiment of the invention, the signal amplifying circuit amplifies the accessed radio frequency signal by adopting a silicon germanium heterojunction triode circuit and outputs the amplified radio frequency signal, and the signal amplifying circuit is electrically connected with the bias voltage circuit. The signal amplifying circuit mainly comprises a first capacitor 16, a first inductor 17, a second capacitor 18, a third resistor 19, a second inductor 20, a first triode 21, a third capacitor 22, a fourth resistor 23, a third inductor 24, a third triode 25, a second triode 26, a fourth capacitor 27 and a fourth inductor 28. The first capacitor 16 is a radio frequency signal input interface, and one pole of the first capacitor 16 is connected to the radio frequency signal input terminal. One end of the first inductor 17 is connected to the other pole of the first capacitor 16, and the other end of the first inductor 17 is grounded. One pole of the second capacitor 18 is connected to the other pole of the first capacitor 16. One end of the third resistor 19 is connected to the other pole of the second capacitor 18, and the other end of the third resistor 19 is connected to the drain of the sixth PMOS transistor 14 in the bias voltage circuit. The base of the first triode 21 is connected to the other pole of the second capacitor 18, and the emitter of the first triode 21 is grounded. One end of the second inductor 20 is connected with an operating power supply, and the other end of the second inductor 20 is connected with a collector electrode of the first triode 21. One pole of the third capacitor 22 is connected to the collector of the first transistor 21. One end of the fourth resistor 23 is connected with the other pole of the third capacitor 22, and the other end of the fourth resistor 23 is connected with the drain electrode of the seventh PMOS tube 15 in the bias voltage circuit. The base of the second triode 26 is connected to the other pole of the third capacitor 22 and the emitter of the second triode 26 is grounded. An emitter of the third triode 25 is connected with a collector of the second triode 26, and a base of the third triode 25 is connected with a working power supply. One end of the third inductor 24 is connected with the base electrode of the third triode 25, and the other end of the third inductor 24 is connected with the collector electrode of the third triode 25. One pole of the fourth capacitor 27 is connected to the collector of the third triode 25, and the other pole of the fourth capacitor 27 is connected to the radio frequency signal output terminal. One end of the fourth inductor 28 is connected to the other pole of the fourth capacitor 27, and the other end of the fourth inductor 28 is grounded.
The aspect ratios of the tubes in the second PMOS tube 5, the fourth PMOS tube 10, the sixth NMOS tube 12, the sixth PMOS tube 14 and the seventh PMOS tube 15 of the CMOS bias circuit can be adjusted, so that the output current is adjusted. The first triode 21 in the signal amplification circuit is a first stage amplification, and can provide a power gain of 20db when the first triode 21 operates at 2.5V. The common emitter common base combination formed by the second transistor 26 and the third transistor 25 is used as a second-stage amplification, and the combined amplification stage can bear voltage swing of up to 10V, so that the output power can be 30dBm, thereby meeting the long-distance application of some special occasions. The variable current output by the sixth PMOS transistor 14 can adjust the first-stage amplified paranoid voltage, and the variable current output by the seventh PMOS transistor 15 can adjust the second-stage amplified paranoid voltage. The radio frequency signal is input into the signal amplifying circuit and is output after two-stage amplification.
When a conventional power amplifier in the prior art works, the output power is reduced along with the temperature rise. When the power amplifier works, after the temperature is increased, the output voltage temperature coefficient of the bias circuit can be adjusted to improve the two-stage amplified paranoid voltage in the signal amplifying circuit, so that the output power is improved, and the output power reduction caused by the transconductance reduction after the temperature is increased is counteracted.
The invention combines the CMOS process and the silicon germanium (SiGe) Heterojunction (HBT) triode process to design the power amplifier, and the power amplifier can adjust the output power between-10 dBm and 30dBm, thereby not only meeting the low-power consumption application in low power, but also meeting the application of high output power in special long-distance conditions.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structural changes made by the present invention and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A power amplifier, comprising:
a positive temperature coefficient current source circuit which outputs a positive temperature coefficient current;
a negative temperature coefficient current source circuit which outputs a negative temperature coefficient current;
a current mirror circuit that receives the positive temperature coefficient current and the negative temperature coefficient current and combines the two temperature coefficient currents into one temperature coefficient adjustable current source, the current mirror circuit outputting the temperature coefficient adjustable current source;
a bias voltage circuit outputting a varying current according to the temperature coefficient adjustable current source; and
the signal amplifying circuit adopts a silicon germanium heterojunction triode circuit to amplify the accessed radio frequency signal and outputs the amplified radio frequency signal, and the signal amplifying circuit is electrically connected with the bias voltage circuit;
wherein the bias voltage circuit includes: the drain electrode of the fifth PMOS tube is connected with the output end of the current mirror circuit, the drain electrode of the fifth PMOS tube is communicated with the grid electrode, and the source electrode of the fifth PMOS tube is connected with a working power supply;
a sixth PMOS tube, which provides a path of changing current for the signal amplifying circuit, wherein the source electrode of the sixth PMOS tube is connected with a working power supply, the grid electrode of the sixth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the signal amplifying circuit; and
the seventh PMOS tube provides another path of changing current for the signal amplifying circuit, a source electrode of the seventh PMOS tube is connected with a working power supply, a grid electrode of the seventh PMOS tube is connected with a drain electrode of the fifth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the signal amplifying circuit.
2. The power amplifier of claim 1, wherein the positive temperature coefficient current source circuit comprises:
one end of the first resistor is connected with a working power supply and inputs positive temperature coefficient current;
the drain electrode of the first NMOS tube is communicated with the grid electrode and is connected with the other end of the first resistor, and the source electrode of the first NMOS tube is grounded;
the source electrode of the first PMOS tube is connected with a working power supply, and the grid electrode and the drain electrode of the first PMOS tube are communicated;
the drain electrode of the second NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded; and
and the source electrode of the second PMOS tube is connected with a working power supply, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is connected with the input end of the current mirror circuit.
3. The power amplifier of claim 2, wherein when the aspect ratio of the second PMOS transistor is adjusted to change, the magnitude of the drain output current of the second PMOS transistor changes accordingly.
4. The power amplifier of claim 1, wherein the negative temperature coefficient current source circuit comprises:
one end of the second resistor is connected with the working power supply and inputs negative temperature coefficient current;
the drain electrode of the third NMOS tube is communicated with the grid electrode and is connected with the other end of the second resistor, and the source electrode of the third NMOS tube is grounded;
the source electrode of the third PMOS tube is connected with a working power supply, and the grid electrode and the drain electrode of the third PMOS tube are communicated;
the drain electrode of the fourth NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, and the source electrode of the fourth NMOS tube is grounded; and
and the source electrode of the fourth PMOS tube is connected with a working power supply, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the input end of the current mirror circuit.
5. The power amplifier of claim 4, wherein when the aspect ratio of the fourth PMOS transistor is adjusted to change, the magnitude of the drain output current of the fourth PMOS transistor changes accordingly.
6. The power amplifier of claim 1, wherein the current mirror circuit comprises:
the drain electrode of the fifth NMOS tube is the input end of the current mirror circuit, the drain electrode of the fifth NMOS tube is communicated with the grid electrode, and the source electrode of the fifth NMOS tube is grounded; and
and the grid electrode of the sixth NMOS tube is connected with the grid electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube is grounded, the drain electrode of the sixth NMOS tube is connected with the bias voltage circuit, and the drain electrode of the sixth NMOS tube is the output end of the current mirror circuit.
7. The power amplifier of claim 6, wherein when the aspect ratio of the sixth NMOS transistor is adjusted to change, the magnitude of the drain output current of the sixth NMOS transistor changes accordingly.
8. The power amplifier of claim 1, wherein when the aspect ratio of the sixth PMOS transistor and/or the seventh PMOS transistor is adjusted to change, the magnitude of the drain output current of the sixth PMOS transistor and/or the seventh PMOS transistor changes accordingly.
9. The power amplifier of claim 1, wherein the signal amplification circuit comprises:
the first capacitor is a radio frequency signal input interface, and one pole of the first capacitor is connected with the radio frequency signal input end;
one end of the first inductor is connected with the other pole of the first capacitor, and the other end of the first inductor is grounded;
a second capacitor having one pole connected to the other pole of the first capacitor;
one end of the third resistor is connected with the other pole of the second capacitor, and the other end of the third resistor is connected with the bias voltage circuit;
the base electrode of the first triode is connected with the other electrode of the second capacitor, and the emitting electrode of the first triode is grounded;
one end of the second inductor is connected with a working power supply, and the other end of the second inductor is connected with the collector electrode of the first triode;
a third capacitor having a pole connected to the collector of the first transistor;
one end of the fourth resistor is connected with the other pole of the third capacitor, and the other end of the fourth resistor is connected with the bias voltage circuit;
the base electrode of the second triode is connected with the other electrode of the third capacitor, and the emitter electrode of the second triode is grounded;
the emitter of the third triode is connected with the collector of the second triode, and the base of the third triode is connected with a working power supply;
one end of the third inductor is connected with the base electrode of the third triode, and the other end of the third inductor is connected with the collector electrode of the third triode;
one pole of the fourth capacitor is connected with the collector electrode of the third triode, and the other pole of the fourth capacitor is connected with the radio frequency signal output end; and
and one end of the fourth inductor is connected with the other pole of the fourth capacitor, and the other end of the fourth inductor is grounded.
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|---|---|---|---|---|
| CN104135238A (en) * | 2013-05-03 | 2014-11-05 | 日月光半导体制造股份有限公司 | RF power amplifier and electronic system |
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