CN111258941B

CN111258941B - System for outputting digital signal and method for outputting digital signal

Info

Publication number: CN111258941B
Application number: CN201811464289.7A
Authority: CN
Inventors: 王天宇
Original assignee: China Telecom Corp Ltd
Current assignee: China Telecom Corp Ltd
Priority date: 2018-12-03
Filing date: 2018-12-03
Publication date: 2021-11-26
Anticipated expiration: 2038-12-03
Also published as: CN111258941A

Abstract

The disclosure provides a method and a device for outputting a digital signal, and relates to the technical field of digital circuits. The method for outputting the digital signal comprises the following steps: stacking a plurality of top plates on the main plate in sequence; and inputting the clock signal and the data signal of the main board into the data selector of each top board for processing, so that the data selector of each top board outputs each data information in the data signal in a round-robin manner, and each data information corresponds to each different clock information in the clock signal. This is disclosed through carrying out time division multiplex to the mainboard interface, has realized the multilayer extension to the mainboard interface for can pile up the multilayer roof on the mainboard.

Description

System for outputting digital signal and method for outputting digital signal

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to a system for outputting a digital signal and a method for outputting a digital signal.

Background

Arduino is a convenient, flexible and convenient open-source electronic prototype platform. Including hardware (various models of Arduino boards) and software (Arduino IDE), was developed by the european development team in winter 2005.

The Arduino interface is a standard interface for Arduino. Figure 1 shows the standard interface of Arduino. The interface comprises 8 power interfaces, 6 paths of analog signal interfaces and 18 paths of digital signal interfaces.

Due to the influence of Arduino, especially in the field of internet of things, there are more and more development boards supporting Arduino interfaces. The standard Arduino Uno development board uses Atmega328 as a micro control unit, operating at 16MHZ, and all ceiling frequencies are based on 16MHZ or lower. Therefore, the mainboard has the capability of driving a plurality of top plates by adopting the micro control unit with 16MHZ frequency multiplication. Taking the STM32L476 development board as an example, the working frequency of the STM32L476 development board is 80MHZ, and the STM32L476 development board has the capability of driving 5 top plates.

Disclosure of Invention

The technical problem that this disclosure solved is how to prevent the damage of lightning stroke to the side equipment of output digital signal and receive the electric side equipment while guaranteeing communication service.

According to an aspect of an embodiment of the present disclosure, there is provided a method of outputting a digital signal, including: stacking a plurality of top plates on the main plate in sequence; and inputting the clock signal and the data signal of the main board into the data selector of each top board for processing, so that the data selector of each top board outputs each data information in the data signal in a round-robin manner, and each data information corresponds to each different clock information in the clock signal.

In some embodiments, the data selector comprises a programmable counter and an and gate circuit; the data selector for inputting the clock signal and the data signal of the main board into each top board for processing comprises: inputting a clock signal of the mainboard into the programmable counters of the top plates, and simultaneously inputting an output result and a data signal of the mainboard into an AND gate circuit; the programmable counters of the respective top plates are configured to intercept respective different clock information in the clock signal in turn.

In some embodiments, sequentially stacking a plurality of top plates on the main plate includes: inserting a male contact pin in a lower panel of the first top plate into a female socket in an upper panel of the mainboard; and inserting the male pin in the lower panel of the second top plate into the female socket in the upper panel of the first top plate, and so on.

In some embodiments, further comprising: and inputting each data information in the data signals output by the data selector round streams of each top plate into the latch of each top plate respectively.

In some embodiments, the clock frequency of the motherboard is an integer multiple of the clock frequency of the respective top plate.

According to another aspect of an embodiment of the present disclosure, there is provided an apparatus for outputting a digital signal, including a main board and a plurality of top plates sequentially stacked on the main board; wherein each top plate is provided with a data selector, each data selector being configured to: and processing the input clock signal and the data signal of the mainboard, and outputting each data information in the data signal in turn, wherein each data information corresponds to each different clock information in the clock signal.

In some embodiments, the data selector comprises a programmable counter and an and gate circuit; the input end of the programmable counter of each top plate is electrically connected with the clock line of the mainboard, and the output end of the programmable counter and the data signal of the mainboard are simultaneously accessed into the AND gate circuit; the programmable counters of the top plates are configured to intercept different clock information in the clock signal in turn.

In some embodiments, the upper panel of the main board is provided with a female socket, the upper panel of each top board is provided with a female socket, and the lower panel of each top board is provided with a male pin; the male contact pin of the first top plate is inserted into the female socket of the main plate, the male contact pin of the second top plate is inserted into the female socket of the second top plate, and so on.

In some embodiments, a latch is further disposed on each top plate, and an input terminal of the latch of each top plate is electrically connected to an output terminal of the data selector of the top plate.

This is disclosed through carrying out time division multiplex to the mainboard interface, has realized the multilayer extension to the mainboard interface for can pile up the multilayer roof on the mainboard.

Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive exercise.

Figure 1 shows the standard interface of Arduino.

Fig. 2 illustrates a flow diagram of a method of outputting a digital signal according to some embodiments of the present disclosure.

Fig. 3 schematically shows a main plate on which a plurality of top plates are stacked in sequence.

FIG. 4 illustrates a data timing diagram of various data information in the data selector round-robin output data signal for the top plate.

FIG. 5 illustrates another data timing diagram that illustrates various data information in the data selector round-robin output data signal for the top plate.

Fig. 6 shows a schematic flow diagram of an apparatus for outputting a digital signal according to some embodiments of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

The inventor researches and discovers that the current multi-layer board multiplexing mainly comprises two types. One of these is chip select enable: and chip selection is carried out by using one pin of the main board, so that the function of the current top board is enabled. Another type is that multiple top boards can be cascaded using an industrial computer bus protocol such as PC/104, followed by address access enabling. However, chip select enable needs to occupy one pin of the motherboard, so that one more pin of the motherboard is occupied by adding one top plate, and the resources of the motherboard are consumed. The switching speed of the address protocol is not fast enough, and the method is often suitable for the type of performing a large number of continuous operations on each sub-address and is more applied to computer systems with strong performance.

In view of the above, the present invention provides a method for outputting a digital signal to solve the above problems. The description will be given by taking a multilayer board with an Arduino interface as an example.

Some embodiments of the method of outputting a digital signal of the present disclosure are first described in conjunction with fig. 2.

Fig. 2 illustrates a flow diagram of a method of outputting a digital signal according to some embodiments of the present disclosure. As shown in fig. 2, the method of outputting a digital signal in the present embodiment includes steps S202 to S204.

In step S202, a plurality of top plates are sequentially stacked on the main plate.

Fig. 3 schematically shows a main plate on which a plurality of top plates are stacked in sequence. As shown in fig. 3, by means of the Arduino interface, the upper panels of the main board and the top board are female-head plastic seats, and the lower panels of the top board are male-head pins. A male pin in the lower panel of the first top plate can be inserted into a female socket in the upper panel of the mainboard; and inserting the male pin in the lower panel of the second top plate into the female socket in the upper panel of the first top plate, and so on.

After the stacking is complete, a column of pins may be defined for the motherboard and each top plate as a clock signal and a column of pins as a data signal. The pin defined as the clock signal or the data signal may be an 18-channel digital signal interface located in the Arduino interface, or may be a 6-channel analog signal interface located in the Arduino interface. It will be appreciated by those skilled in the art that if a 6-way analog signal interface is used, analog-to-digital conversion is required.

It should be noted that the clock frequency of the main board is required to be an integral multiple of the clock frequency of each top board. For example, STM32L476 may be clocked at 80Mhz, and the processor on the top board may be selected from Atmega328 by Arduino Uno, with a clock frequency of 16 Mhz. Thus, the motherboard theoretically has the capability of driving 5 top boards.

In step S204, the clock signal and the data signal of the motherboard are input to the data selector of each top board for processing, so that the data selector of each top board outputs each data information in the data signal in a round-robin manner, and each data information corresponds to each different clock information in the clock signal.

FIG. 4 illustrates a data timing diagram of various data information in the data selector round-robin output data signal for the top plate. As shown in fig. 4, if there are 4 top boards, the first top Board1 is active when the first clock signal CLK comes, and cycles with 4 clock signals as a cycle. The second ceiling Board2 is asserted when the second clock signal arrives, cycling through 4 clock signals. Third top panel Board3, fourth top panel Board4 and so on. Each DATA information in the DATA signal DATA may be specifically adjusted according to an interface protocol.

In some embodiments, the data selector includes a programmable counter and an AND gate circuit. In step S204, the clock signal of the main board is input to the programmable counters of the respective top boards, and the output result is input to the and circuit together with the data signal of the main board. Wherein the programmable counters of the respective top plates are configured to alternately intercept respective different clock information in the clock signal.

For example, the clock line of each top plate is first connected to a programmable counter, which may be specifically an adder counter, whose count is determined by the total number of top plates and the top plate number. The data selector is then told by a clock signal through a programmable counter when which way to select for output or input. The 4 programmable counters can respectively intercept different clock information in the clock signals under the conditions of 1, 2, 3 and 4 of data information, and output low level under other conditions, thereby determining whether the data signal is input or not. Those skilled in the art will appreciate that the processing logic of the data selector may also be implemented in software.

FIG. 5 illustrates another data timing diagram that illustrates various data information in the data selector round-robin output data signal for the top plate. As shown in fig. 5, a half-rate transmission scheme is adopted to transmit one bit empty and one bit empty to reduce interference in the output signal, and for example, 4-bit 2-ary code is output to each top board in the following order:

board 1: 1001; board 2; 1010; board 3: 1011; board 4: 1100, 1100; the main board output is DATA 1111A, 0001A, 0110A, 1010A.

The embodiment realizes the multilayer expansion of the mainboard interface by performing time division multiplexing on the mainboard interface, so that a plurality of layers of top plates can be stacked on the mainboard. Therefore, the embodiment solves the problems that a single main board interface is not enough to use and the resource provided for the top board is limited, and also avoids the condition that a plurality of communication systems need to be expanded for the top board.

In some embodiments, the method further comprises step S206.

In step S206, the data information in the data signal output from the data selector round stream of each top plate is input to the latch of each top plate.

After time division multiplexing is realized through the data selector, signals output by the data selector can keep data through the data latch, and data distortion is avoided.

Some embodiments of the apparatus for outputting a digital signal of the present disclosure are described below with reference to fig. 6.

Fig. 6 shows a schematic flow diagram of an apparatus 60 for outputting a digital signal according to some embodiments of the present disclosure. As shown in fig. 6, the apparatus 60 for outputting a digital signal in the present embodiment includes a main board 602 and a plurality of top plates 604 stacked in sequence on the main board. Wherein each top plate 604 is provided with a data selector 6042, each data selector 6042 being configured to: and processing the input clock signal and the data signal of the mainboard, and outputting each data information in the data signal in turn, wherein each data information corresponds to each different clock information in the clock signal.

In some embodiments, the data selector 6042 includes a programmable counter 60422 and an and gate circuit 60424; the input end of the programmable counter 60422 of each top plate is electrically connected with the clock line of the main board, and the output end and the data signal of the main board are simultaneously connected into the AND circuit 60424; the programmable counters 60422 of the respective top plates are configured to take turns intercepting respective different clock information in the clock signal.

In some embodiments, the upper panel of the main board 602 is provided with a female socket, the upper panel of each top board 604 is provided with a female socket, and the lower panel of each top board is provided with a male pin; the male contact pin of the first top plate is inserted into the female socket of the main plate, the male contact pin of the second top plate is inserted into the female socket of the second top plate, and so on.

In some embodiments, a latch 6044 is also provided on each top plate 604, and an input of the latch 6044 of each top plate is electrically connected to an output of the data selector 6042 of the top plate 604.

In some embodiments, the clock frequency of the motherboard 602 is an integer multiple of the clock frequency of the respective top plate 604.

As will be appreciated by one skilled in the art, embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable non-transitory storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only exemplary of the present disclosure and is not intended to limit the present disclosure, so that any modification, equivalent replacement, or improvement made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims

1. A method of outputting a digital signal, comprising:

stacking a plurality of top plates on the main plate in sequence;

inputting the clock signal and the data signal of the main board into the data selector of each top board for processing, so that the data selector of each top board outputs each data information in the data signal in a round-robin manner, wherein each data information corresponds to each different clock information in the clock signal, respectively, and the clock signal and the data signal are respectively corresponding to each different clock information in the clock signal,

the data selector comprises a programmable counter and an AND gate circuit;

the data selector which inputs the clock signal and the data signal of the main board into each top board for processing comprises the following steps: inputting a clock signal of the mainboard into the programmable counters of the top plates, and simultaneously inputting an output result and a data signal of the mainboard into an AND gate circuit; the programmable counters of the respective top plates are configured to intercept respective different clock information in the clock signal in turn.

2. The method of claim 1, wherein the sequentially stacking a plurality of top plates on a main plate comprises:

inserting a male contact pin in a lower panel of the first top plate into a female socket in an upper panel of the mainboard;

and inserting the male pin in the lower panel of the second top plate into the female socket in the upper panel of the first top plate, and so on.

3. The method of claim 1, further comprising:

and inputting each data information in the data signals output by the data selector round streams of each top plate into the latch of each top plate respectively.

4. The method of claim 1, wherein the clock frequency of the motherboard is an integer multiple of the clock frequency of the respective top plate.

5. An apparatus for outputting a digital signal includes a main board and a plurality of top plates sequentially stacked on the main board; wherein each top plate is provided with a data selector, each data selector being configured to: processing the input clock signal and data signal of the mainboard, and outputting each data information in the data signal in turn, wherein each data information corresponds to each different clock information in the clock signal, respectively,

the data selector comprises a programmable counter and an AND gate circuit; the input end of the programmable counter of each top plate is electrically connected with the clock line of the mainboard, and the output end of the programmable counter and the data signal of the mainboard are simultaneously accessed into the AND gate circuit; a programmable counter of each top plate configured to intercept each different clock information in the clock signal in turn.

6. The apparatus of claim 5, wherein the upper panel of the main board is provided with female sockets, the upper panel of each top board is provided with female sockets, and the lower panel of each top board is provided with male pins; the male contact pin of the first top plate is inserted into the female socket of the main plate, the male contact pin of the second top plate is inserted into the female socket of the second top plate, and so on.

7. The apparatus of claim 5, wherein a latch is further provided on each top plate, and an input terminal of the latch of each top plate is electrically connected to an output terminal of the data selector of the top plate.

8. The apparatus of claim 5, wherein the clock frequency of the main board is an integer multiple of the clock frequency of each top board.