CN111258132A - Array substrate and liquid crystal display panel - Google Patents
Array substrate and liquid crystal display panel Download PDFInfo
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- CN111258132A CN111258132A CN202010242474.2A CN202010242474A CN111258132A CN 111258132 A CN111258132 A CN 111258132A CN 202010242474 A CN202010242474 A CN 202010242474A CN 111258132 A CN111258132 A CN 111258132A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- Crystallography & Structural Chemistry (AREA)
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
Abstract
The embodiment of the application provides an array substrate and a liquid crystal display panel. The array substrate includes: a substrate having a display region and a non-display region; a plurality of pixel units; each chip is connected with the pixel units through a plurality of fan-out lines, and the lengths of the fan-out lines are different; and the auxiliary connecting lines are arranged in the non-display area, each auxiliary connecting line is set to be a first preset length, and each auxiliary connecting line in the auxiliary connecting lines is respectively connected with one fan-out line in parallel, so that the equivalent resistance of each fan-out line is adjusted, and the charging time of the fan-out lines to the pixel units is balanced. According to the display device, each auxiliary connecting line in the plurality of auxiliary connecting lines is connected with one fan-out line in parallel, so that the equivalent resistance of each fan-out line is adjusted, the charging time of the plurality of fan-out lines to the plurality of pixel units is balanced, the display balance can be improved, and the display quality is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a liquid crystal display panel.
Background
The Gate Driver On Array, abbreviated as GOA, is a driving method for Gate line-by-line scanning, which is implemented by fabricating a Gate line scanning driving signal circuit On an Array substrate by using Array process in the existing thin film transistor liquid crystal display.
For the GOA product, usually a dual-drive product, i.e. the left GOA and the right GOA drive the display panel simultaneously, which causes the same gate routing, the gate waveform in the middle area will not be consistent with the edge gate waveform, which means that after the time of the timing signal and the data voltage signal is set at the chip on chip, the charging time in different areas in the panel will not be consistent due to the reason of the GOA drive setting, i.e. the middle charging time is short and the edge charging time is long. The charging time difference causes different charging rates in different areas in the surface, which results in uneven display of the image.
Disclosure of Invention
An object of the embodiments of the present application is to provide an array substrate and a liquid crystal display panel, which have the beneficial effect of improving the charging uniformity of each pixel unit.
In a first aspect, an embodiment of the present application provides an array substrate, including:
a substrate having a display region and a non-display region;
a plurality of pixel units disposed in the display region;
the chip on film is arranged in the non-display area, each chip on film is connected with the pixel units through a plurality of fan-out lines, and the lengths of the fan-out lines are different;
the plurality of auxiliary connecting lines are arranged in the non-display area, each auxiliary connecting line is set to be different in first preset length, each auxiliary connecting line in the plurality of auxiliary connecting lines is connected with one of the plurality of fan-out lines in parallel, and therefore the equivalent resistance of each fan-out line is adjusted, and the charging time of the plurality of fan-out lines to the plurality of pixel units is balanced.
According to the embodiment of the application, the plurality of auxiliary connecting lines are arranged, each auxiliary connecting line in the plurality of auxiliary connecting lines is connected with one fan-out line in parallel, so that the equivalent resistance of each fan-out line is adjusted, the plurality of fan-out lines are balanced in charging time of the pixel units, the display balance can be improved, and the display quality is improved
Optionally, in the array substrate described in the present application, a first metal layer, a second metal layer, and a first insulating layer located between the first metal layer and the second metal layer are disposed on the substrate; the first metal layer forms a plurality of fanout lines, and the second metal layer forms a plurality of connection auxiliary lines.
Optionally, in the array substrate of the present application, the plurality of auxiliary connection lines correspond to a part of the fanout lines;
the first insulating layer is provided with a plurality of metalized holes, and each auxiliary connecting line is connected with the corresponding fanout line in parallel through the metalized holes.
Optionally, in the array substrate of the present application, the plurality of fan-out lines include at least one first fan-out line with a first length and a plurality of second fan-out lines, the lengths of the plurality of second fan-out lines are different, and the lengths of the plurality of second fan-out lines are all greater than the first fan-out line;
the plurality of connecting auxiliary lines and the plurality of second fan-out lines are connected in parallel in a one-to-one correspondence mode, so that the parallel equivalent resistance of each second fan-out line and the corresponding connecting auxiliary line is equal to the equivalent resistance of the first fan-out line.
Optionally, in the array substrate of the present application, the plurality of auxiliary connection lines correspond to one of the plurality of fanout lines one to one;
the first insulating layer is provided with a plurality of metalized holes, and each auxiliary connecting line is connected with the corresponding fanout line in parallel through the metalized holes.
Optionally, in the array substrate described in the present application, the lengths of the fan-out lines are not uniform;
the fan-out lines and the auxiliary connecting lines are connected in parallel in a one-to-one correspondence mode to form a plurality of groups of parallel lines, and the equivalent resistances of the groups of parallel lines are the same.
Optionally, in the array substrate described in the present application, a length of each connection auxiliary line is the same as a length of a corresponding fanout line; the fan-out lines have the same thickness and different widths; the longer the fan-out lines among the plurality of fan-out lines, the larger the width of the connection auxiliary line corresponding to the fan-out line.
According to the embodiment of the application, the auxiliary connecting lines with different widths are connected with the fanout lines with different lengths in parallel, so that the balance of the fanout lines is adjusted, the charging time balance of each pixel unit is ensured, and the display uniformity can be improved.
Optionally, in the array substrate described in the present application, a width of each connection auxiliary line is the same as a width of a corresponding fanout line; the fan-out lines have the same thickness and different lengths; the longer the length of the fan-out line among the plurality of fan-out lines is, the longer the length of the connection auxiliary line corresponding to the fan-out line is.
Optionally, in the array substrate described in the present application, a length of each connection auxiliary line is the same as a length of a corresponding fanout line; the fan-out lines have the same width and different thicknesses; the longer the length of the fan-out lines is, the larger the thickness of the connection auxiliary line corresponding to the fan-out line is.
According to the embodiment of the application, the auxiliary connecting lines with different thicknesses are connected in parallel with the fan-out lines with different lengths, so that the balance of the fan-out lines is adjusted, the charging time balance of each pixel unit is ensured, and the display uniformity can be improved.
In a second aspect, an embodiment of the present application provides a liquid crystal display panel, including the array substrate described in any one of the above.
As can be seen from the above, in the embodiment of the application, by providing a plurality of connection auxiliary lines, which are disposed in the non-display area, each of the connection auxiliary lines is set to have a first preset length, and each of the connection auxiliary lines is connected in parallel with one of the fan-out lines, so as to adjust an equivalent resistance of each of the fan-out lines, so that the plurality of fan-out lines are charge-time-balanced to a plurality of pixel units, thereby improving display balance and display quality.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic partial structure diagram of an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic partial cross-sectional view of an array substrate according to an embodiment of the present disclosure; and
fig. 4 is another partial structural schematic diagram of an array substrate according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "plurality" means two or more unless specifically limited otherwise.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure, and fig. 2 is a schematic partial structural diagram of the array substrate. The array substrate includes: the liquid crystal display device comprises a substrate 10, a plurality of pixel units 20, a plurality of chip-on-film chips 30, a plurality of fanout lines 40a, a plurality of auxiliary connecting lines 40b, a GOA driving circuit 60, a plurality of scanning lines 70 and a plurality of data lines 80.
Wherein, the substrate 10 has a display region 11 and a non-display region 12; the plurality of pixel units 20 are arranged in the display area 11 in a uniform array; the GOA driver circuit 60 and the plurality of flip-chip on film chips 30 are disposed in the non-display area 12. The data lines 80 and the scan lines 70 are criss-cross to define a plurality of pixel regions, and the pixel units 20 are respectively disposed in the pixel regions. The GOA driving circuit 60 is connected to the plurality of scan lines 70, and the plurality of chip on film chips 30 are correspondingly connected to the plurality of data lines 80 through the plurality of fanout lines 40a, so as to charge the corresponding pixel units 20.
Wherein, the lengths of the fan-out lines 40a are different; each of the auxiliary connecting lines 40b is set to a first preset length, and each of the auxiliary connecting lines 40b of the plurality of auxiliary connecting lines 40b is connected in parallel with one of the fanout lines 40a, so as to adjust an equivalent resistance of each of the fanout lines 40a, and equalize charging times of the plurality of fanout lines 40a to the plurality of pixel units 20.
Referring to fig. 3, a first metal layer 401a, a second metal layer 401b and a first insulating layer 402 between the first metal layer 401a and the second metal layer 401b are disposed on the substrate 10; the first metal layer 401a forms a plurality of fanout lines 40a, and the second metal layer 401b forms a plurality of connection auxiliary lines 40 b.
In some embodiments, the plurality of auxiliary connection lines 40b correspond to a portion of the fanout lines 40a of the plurality of fanout lines 40 a; that is, the number of the auxiliary connection lines 40b is less than the number of the fanout lines 40 a. A plurality of metalized holes 4021 are formed in the first insulating layer 402, and each of the auxiliary connection lines 40b is connected in parallel to the corresponding fanout line 40a through the metalized holes 4021.
Specifically, the fan-out lines 40a include at least one first fan-out line with a first length and a plurality of second fan-out lines, the second fan-out lines have different lengths, and the second fan-out lines have lengths larger than the first fan-out lines. The plurality of auxiliary connecting lines 40b are connected in parallel with the plurality of second fanout lines in a one-to-one correspondence manner, so that the parallel equivalent resistance of each second fanout line and the corresponding auxiliary connecting line is equal to the equivalent resistance of the first fanout line. The auxiliary connecting lines with different lengths are connected in parallel with the fanout lines with different lengths, so that the balance of the fanout lines is adjusted, the charging time balance of each pixel unit is ensured, and the display uniformity can be improved.
In some embodiments, the auxiliary connection lines 40b correspond to one of the fanout lines 40a, that is, the number of the auxiliary connection lines is the same. And, each auxiliary connection line 40b is opposite to a part or the whole of the corresponding fanout line 40 a. A plurality of metalized holes 4021 are formed in the first insulating layer 402, and each of the auxiliary connecting wires is connected in parallel to the corresponding fanout line 40a through the metalized holes 4021. The lengths of the fan-out lines 40a are not uniform; the fan-out lines 40a and the auxiliary connecting lines 40b are connected in parallel in a one-to-one correspondence manner to form a plurality of groups of parallel lines, and the groups of parallel lines have the same equivalent resistance. The auxiliary connecting lines with different lengths are connected in parallel with the fanout lines with different lengths, so that the balance of the fanout lines is adjusted, the charging time balance of each pixel unit is ensured, and the display uniformity can be improved.
In some embodiments, the length of each of the connection auxiliary lines 40b is the same as the length of the corresponding fanout line 40 a; the plurality of fanout lines 40a have the same thickness and different widths; the longer the length of the fanout lines 40a, the larger the width of the connection auxiliary line corresponding to the fanout line 40 a. The equivalent resistances of the auxiliary connecting lines 40b are different by setting different widths, and the auxiliary connecting lines with different widths are connected in parallel with the fanout lines with different lengths, so that the balance of the fanout lines is adjusted, the charging time balance of each pixel unit is ensured, and the display uniformity can be improved.
In some embodiments, the length of each of the connection auxiliary lines 40b is the same as the length of the corresponding fanout line 40 a; the plurality of fanout lines 40a have the same width and different thicknesses, so that the equivalent resistances thereof are different; the longer the length of the fanout lines 40a, the greater the thickness of the connection auxiliary line 40b corresponding to the fanout line 40 a. The fan-out lines 40a with different lengths are connected in parallel through the connecting auxiliary lines 40b with different thicknesses, so that the balance of the fan-out lines is adjusted, the charging time balance of each pixel unit is ensured, and the uniformity of display can be improved.
It can be understood that, in some embodiments, the length, the width, and the thickness of each connection auxiliary line 40b are all different or partially different, so as to achieve the purpose of better setting the resistance of each connection auxiliary line, further achieve accurate control of the equivalent resistance of each fan-out line, achieve the balance adjustment of the charging time of each pixel unit, and improve the display quality.
In addition, referring to fig. 4, fig. 4 is another partial structural schematic diagram of the array substrate according to the embodiment of the present disclosure. The array substrate shown in fig. 4 is different from the array substrate shown in fig. 2 in that, in the array substrate shown in fig. 4, the longer the length of the fan-out line 40a among the plurality of fan-out lines 40a, the longer the length of the connection auxiliary line 40b corresponding to the longer fan-out line 40 a.
Specifically, the width of each connection auxiliary line 40b is the same as the width of the corresponding fanout line 40 a; the plurality of fanout lines 40a have the same thickness and different lengths; the longer the length of the fan-out line 40a among the plurality of fan-out lines 40a, the longer the length of the connection auxiliary line 40b corresponding to the fan-out line 40 a. The auxiliary connecting lines 40b with different lengths are connected in parallel with the fanout lines 40a with different lengths, so that the balance of the fanout lines is adjusted, the charging time balance of each pixel unit is ensured, and the uniformity of display can be improved.
As can be seen from the above, in the embodiment of the application, by providing a plurality of connection auxiliary lines, which are disposed in the non-display area, each of the connection auxiliary lines is set to have a first preset length, and each of the connection auxiliary lines is connected in parallel with one of the fan-out lines, so as to adjust an equivalent resistance of each of the fan-out lines, so that the plurality of fan-out lines are charge-time-balanced to a plurality of pixel units, thereby improving display balance and display quality.
The application also provides a liquid crystal display panel, which comprises the array substrate in any embodiment, and of course, the liquid crystal display panel also comprises a color film substrate and a liquid crystal molecular layer. The array substrate and the color film substrate are opposite and arranged at intervals, and the liquid crystal molecular layer is clamped between the array substrate and the color film substrate.
The above embodiments are merely examples, and not intended to limit the scope of the present application, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present application, or those directly or indirectly applied to other related arts, are included in the scope of the present application.
Claims (10)
1. An array substrate, comprising:
a substrate having a display region and a non-display region;
a plurality of pixel units disposed in the display region;
the chip on film is arranged in the non-display area, each chip on film is connected with the pixel units through a plurality of fan-out lines, and the lengths of the fan-out lines are different;
the plurality of auxiliary connecting lines are arranged in the non-display area, each auxiliary connecting line is set to be different in first preset length, each auxiliary connecting line in the plurality of auxiliary connecting lines is connected with one of the plurality of fan-out lines in parallel, and therefore the equivalent resistance of each fan-out line is adjusted, and the charging time of the plurality of fan-out lines to the plurality of pixel units is balanced.
2. The array substrate of claim 1, wherein the substrate is provided with a first metal layer, a second metal layer and a first insulating layer between the first metal layer and the second metal layer; the first metal layer forms a plurality of fanout lines, and the second metal layer forms a plurality of connection auxiliary lines.
3. The array substrate of claim 2, wherein the plurality of auxiliary connecting lines correspond to some of the fanout lines;
the first insulating layer is provided with a plurality of metalized holes, and each auxiliary connecting line is connected with the corresponding fanout line in parallel through the metalized holes.
4. The array substrate of claim 3, wherein the plurality of fanout lines comprise at least one first fanout line with a first length and a plurality of second fanout lines, the plurality of second fanout lines have different lengths, and the plurality of second fanout lines have lengths greater than the first fanout line;
the plurality of connecting auxiliary lines and the plurality of second fan-out lines are connected in parallel in a one-to-one correspondence mode, so that the parallel equivalent resistance of each second fan-out line and the corresponding connecting auxiliary line is equal to the equivalent resistance of the first fan-out line.
5. The array substrate of claim 2, wherein the plurality of auxiliary connecting lines correspond to one of the plurality of fanout lines;
the first insulating layer is provided with a plurality of metalized holes, and each auxiliary connecting line is connected with the corresponding fanout line in parallel through the metalized holes.
6. The array substrate of claim 5, wherein the fan-out lines have different lengths;
the fan-out lines and the auxiliary connecting lines are connected in parallel in a one-to-one correspondence mode to form a plurality of groups of parallel lines, and the equivalent resistances of the groups of parallel lines are the same.
7. The array substrate of any one of claims 1-6, wherein each of the connection auxiliary lines has a length equal to a length of the corresponding fanout line; the fan-out lines have the same thickness and different widths; the longer the fan-out lines among the plurality of fan-out lines, the larger the width of the connection auxiliary line corresponding to the fan-out line.
8. The array substrate of any one of claims 1-6, wherein each of the connection auxiliary lines has a width equal to a width of the corresponding fanout line; the fan-out lines have the same thickness and different lengths; the longer the length of the fan-out line among the plurality of fan-out lines is, the longer the length of the connection auxiliary line corresponding to the fan-out line is.
9. The array substrate of any one of claims 1-6, wherein each of the connection auxiliary lines has a length equal to a length of the corresponding fanout line; the fan-out lines have the same width and different thicknesses; the longer the length of the fan-out lines is, the larger the thickness of the connection auxiliary line corresponding to the fan-out line is.
10. A liquid crystal display panel comprising the array substrate according to any one of claims 1 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010242474.2A CN111258132A (en) | 2020-03-31 | 2020-03-31 | Array substrate and liquid crystal display panel |
| PCT/CN2020/087670 WO2021196328A1 (en) | 2020-03-31 | 2020-04-29 | Array substrate and liquid crystal display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010242474.2A CN111258132A (en) | 2020-03-31 | 2020-03-31 | Array substrate and liquid crystal display panel |
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| CN111258132A true CN111258132A (en) | 2020-06-09 |
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| CN202010242474.2A Pending CN111258132A (en) | 2020-03-31 | 2020-03-31 | Array substrate and liquid crystal display panel |
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| CN (1) | CN111258132A (en) |
| WO (1) | WO2021196328A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2021227108A1 (en) * | 2020-05-13 | 2021-11-18 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| WO2024120121A1 (en) * | 2022-12-08 | 2024-06-13 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
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- 2020-04-29 WO PCT/CN2020/087670 patent/WO2021196328A1/en active Application Filing
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| CN1512251A (en) * | 2002-12-30 | 2004-07-14 | ���ǵ�����ʽ���� | Display panel with signal line and liquid crystal display device |
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| WO2024120121A1 (en) * | 2022-12-08 | 2024-06-13 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
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| Publication number | Publication date |
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| WO2021196328A1 (en) | 2021-10-07 |
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