CN111257874A - PFA FPGA parallel implementation method - Google Patents
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Abstract
The invention discloses a method for realizing FPGA (field programmable gate array) parallel of a polar coordinate format algorithm in an airborne SAR (synthetic aperture radar) real-time processing system, which overcomes the defects of insufficient processing capacity and low imaging precision of the existing signal processing platform under the requirements of extremely low power consumption, light weight limitation and miniaturization, adopts a PFA (polar Format related data) high-precision imaging algorithm, carries out engineering improvement on the algorithm based on a Chirp Scaling Principle (PCS), can equivalently realize distance interpolation by two times of FFT (fast Fourier transform algorithm) operation, greatly reduces the calculated amount, realizes acceleration processing of the polar coordinate format algorithm in an FPGA (field programmable gate array) chip in parallel and efficiently, improves the execution efficiency and the processing speed of the algorithm of the real-time imaging system, is applied to the airborne SAR real-time processing system, has the capability of carrying out continuous and stable high-resolution imaging on the ground, has high application value and is worth popula.
Description
Technical Field
The invention belongs to the technical field of radar real-time imaging, and particularly relates to a PFA FPGA parallel implementation method.
Background
The synthetic aperture radar can acquire high-resolution ground images all day long and all day long, is widely applied to the military and civil fields, and becomes an important development direction in the technical field of modern radars. The bunching SAR is used as an important working mode of the imaging radar, a higher-resolution image can be obtained by adjusting the beam pointing to irradiate a fixed area for a long time, and the limitation that the highest resolution is half of the azimuth aperture length of the antenna in a stripe SAR mode is broken through. At present, the most applied in real-time bunching SAR imaging is a Polar coordinate Format Algorithm (PFA for short), the PFA adopts the Polar coordinate Format to store data, so that the problem of the moving of a cross-resolution unit far away from a central scattering point of an imaging area is effectively solved, and the effective focusing imaging range of the bunching SAR is improved; meanwhile, the orientation resampling process of the algorithm essentially comprises a keystone transformation, linear distance walk of all targets including moving targets can be automatically corrected, and particularly when the moving targets are imaged, the residual distance walk of the targets can still not exceed a distance resolution unit. However, the algorithm needs to realize coordinate conversion through two-dimensional interpolation and two-dimensional Inverse Fast Fourier Transform (IFFT), and this processing process causes huge computation to the algorithm, which provides huge challenges for a signal processing hardware platform and an implementation method.
The hardware realization platform for real-time digital signal processing mainly comprises a DSP and an FPGA. In the early development stage of the SAR system, the DSP has been widely used. However, as the requirements of the SAR imaging system in terms of performance, power consumption, reliability, and the like are continuously increased, it is increasingly difficult for the DSP to meet the requirements of real-time performance. The FPGA can rapidly complete the basic operations of digital signal processing such as FFT, complex multiplication and addition, CORDIC algorithm and the like by utilizing special hardware structures such as large-scale logic units, on-chip memories, high-speed buses, pipeline processing and the like. Due to the limitation of various resources in the FPGA chip, the occupancy rate of the FPGA resources directly determines the real-time processing capacity and the equipment amount of the signal processor, in order to reduce the equipment amount of a system, the implementation of the PFA algorithm needs to be closely combined with the hardware system architecture characteristics of the FPGA, and the algorithm is mapped on the FPGA chip with the minimum occupation requirement of the processing resources on the premise that the algorithm meets the imaging performance requirement. Under the background, a method for realizing the PFA algorithm in parallel in the FPGA is needed, and the PFA imaging algorithm has the characteristics of complex operation and high parallelism, is utilized, and efficiently finishes the engineering realization of the algorithm.
Disclosure of Invention
The invention provides a PFA FPGA parallel implementation method for solving the problems in the prior art, and adopts the following technical scheme for achieving the purpose.
Echo data caching, accomplish the data acquisition function by high-speed AD chip, change radar intermediate frequency echo signal into digital signal, send for FPGA through high-speed serial bus, FPGA receives baseband quadrature sampling data, on the one hand, accomplish data record by a plurality of FLASH chips of FPGA control in parallel, on the other hand, accomplish data caching by FPGA, according to the sampling point number of radar distance to the processing, parallelly store in DDR1 and two sets of DDR2 respectively.
PFA parameter calculation, extracting radar known parameters in echo data, including radar range RrefAn azimuth sampling frequency PRF, a flying height H, a flying speed v, an azimuth sampling pulse number N _ pulse, a distance pulse sampling point number Nr, an azimuth imaging processing point number Na and a pulse width TaA transmission pulse spectrum width B, a transmission signal wavelength lambda and a pulse sampling frequency fsAngle of declination thetasAccording to the parameters, PFA parameters required by scale transformation are calculated, in order to improve the operation efficiency, double pulses are adopted for simultaneous parallel processing, the subsequent double operation modules read the parameters simultaneously, and two groups of RAMs store the calculated parametersThe RAM storing the data reads one parameter at a time according to one address.
And (3) distance direction processing, resampling is realized by adopting a Chirp Scaling principle, pulse data are read from DDR1 and DDR2 respectively, parameters are read from two groups of RAMs respectively, phase factors are obtained through calculation, and complex multiplication operation is carried out.
When complex multiplication starts to be output, triggering an IP core of Fast Fourier Transform (FFT), setting the processing length of the FFT, simultaneously performing FFT and filtering function calculation, when the dv signal of the FFT core is pulled high, representing that the FFT generates result output, performing complex multiplication operation on the output result of the FFT and the filtering function, performing Inverse Fast Fourier Transform (IFFT) in parallel, multiplying the result by a phase compensation factor, performing Fourier transform in parallel and multiplying the result by the filtering function, repeating the steps until all pulse processing is completed, and writing back data DDR.
And azimuth processing, namely resampling is realized by adopting a Chirp Scaling principle, and PFA azimuth interpolation is essentially azimuth time domain scale transformation with distance-by-distance frequency change, and comprises three FFT operations and four complex multiplication operations.
And completing azimuth resampling and azimuth compression, wherein the signals are still in a frequency domain in a distance dimension, performing distance IFFT (inverse fast Fourier transform) on the output signals, realizing two-dimensional focusing imaging on a target, performing modulus on two-dimensional data, and realizing data conversion from a complex number domain to an amplitude domain.
And (3) image quantization, namely calculating the two-dimensional matrix mean value corresponding to the image data, namely the mean value of the distance matrix and the orientation matrix, multiplying the two-dimensional matrix mean value by a quantization coefficient to finish image quantization, and converting the image data in the floating point format into gray level image data.
According to the invention, a high-speed large-capacity Virtex-7 series FPGA is used as a processing core, and a PFA imaging algorithm is mapped into a single FPGA chip to be realized, so that the traditional DSP + FPGA processing architecture is replaced, a large amount of data interaction among multiple chips is avoided, the processing efficiency and speed are greatly improved, and the overall real-time performance of the system is improved; the whole imaging algorithm is completely processed in a single chip, data flow is clear, realization is flexible, realization cost is greatly reduced, and system capacity is easy to expand; the method is realized by combining motion compensation with a PFA imaging algorithm, solves the problems of motion compensation precision and high resolution imaging precision requirements under a complex motion environment, can stably and continuously output high-quality SAR images, is flexible and efficient to realize, can be applied to newly-developed aperture radars, can also be popularized on the existing synthetic aperture radars, and improves the real-time imaging performance of the existing airborne SAR system.
Drawings
Fig. 1 is a process flow, fig. 2 is a parameter calculation module, fig. 3 is a parameter calculation sequence, fig. 4 is a distance direction process flow, fig. 5 is an azimuth direction process flow, fig. 6 is a time division multiplexing flow, and fig. 7 is a real-time image processing.
Detailed Description
The technical scheme of the invention is specifically explained in the following by combining the attached drawings.
A PFA FPGA parallel implementation is disclosed, as shown in figure 1, an AD chip writes intermediate frequency sampling data of radar baseband echoes into double channels DDR1 and DDR2 in an odd-even mode through a high-speed serial bus for temporary storage, radar parameters required by distance direction processing and azimuth direction processing mesoscale conversion are calculated and stored into two groups of RAMs, PFA processing based on PCS is performed in parallel, and the PFA processing comprises a series of FFT and complex multiplication operations, so that data modulus value calculation and image quantization are completed.
The parameter calculation is completed by a plurality of calculation modules, as shown in FIG. 2, including a fixed point to floating point conversion module, an angle parameter calculation module, a distance parameter calculation module, a parameter storage module, and fxCalculation module and fyAnd a calculation module.
The parameter calculation module extracts constant parameters from the input radar echo data, calculates radar parameters required by a subsequent algorithm processing module, firstly inputs the constant parameters including radar action distance, azimuth sampling frequency, flight height, flight speed, distance sampling point number, azimuth sampling point number and azimuth sampling pulse number, and calculates related PFA parameters including distance scale conversion factors, flight corners, distance time axes, distance interpolation frequency axes, frequency modulation slopes and the like according to the constant parameters.
The parameter calculation is performed in time series, and as shown in fig. 3, the state _ X indicates the state _ Nr, state _ Na, and state _ Nrr parameters input by the external module, the O _ para _ X indicates the O _ para _ K, O _ para _ fc and O _ delta _ fy CONSTANT parameters output by the parameter calculation module, the I _ para _ addr _ X indicates the value of the RAM in the parameter calculation module read by the external module input parameter calculation module, and the O _ para _ y indicates the time axis and frequency axis parameters output by the parameter calculation module.
The module outputs an O _ finish signal, which indicates that the constant parameters mounted on the bus are stable and available, the related time axis and frequency axis parameters are respectively stored in the two related groups of RAMs and can be called by an external module at any time, the external input finishes the address addressing of the RAMs, and the addressing result is output after two clock cycles.
The distance direction processing adopts a Chirp Scaling principle to realize resampling, as shown in figure 4, four expressions are in an exponential form, and exponential operation is realized by a cordic IP core in an FPGA.
Respectively calculating phase compensation factors phi of the first pulse and the second pulse according to the parameters output by the parameter calculation module1(tau), completing the calculation of the phase compensation factor, triggering DDR1 and DDR2 to simultaneously read two pulse data in parallel, and respectively performing complex multiplication operation with the corresponding phase compensation factor
Where c is the speed of light, τ is the fast time, k is the chirp rate, δrAs distance to scale conversion factor, RaFor the instantaneous distance from the antenna phase center to the scene center, the complex multiplication operation starts to output, an FFT IP core is triggered, the FFT operation length is set, the FFT operation is carried out, the FFT core starts to output, namely the DV signal of the FFT core is pulled high, and the data subjected to the FFT operation and a filter function H are subjected to1(fτ) Multiplication by a filter function of
The complex multiplication operation starts to output data, the FFT IP core is triggered again, the length of the FFT IP core is set, the FFT core is set to work in an inverse mode, and the output result of the IFFT is multiplied by a secondary phase function phi2(τ) a quadratic phase function of
In the formula fcPerforming FFT operation on the complex multiplication output result of the quadratic phase function for the carrier frequency, and multiplying the result by the motion compensation filter factor
And outputs the result SR(t,fτ)。
In the distance direction processing, an input signal is a signal after reference distance compensation, and a PFA distance direction resampled signal is output, wherein distance direction pulse compression and motion compensation of a scene central point are embedded into distance scale conversion, and the distance direction pulse compression and the motion compensation of the scene central point are not respectively carried out by a traditional PFA algorithm.
The azimuth processing also adopts Chirp Scaling principle to realize resampling, and as shown in FIG. 5, PFA azimuth interpolation is essentially azimuth time domain scale transformation with distance-by-distance frequency change, and the result S is output to the processing module for distanceR(t,fτ) Multiplication by a filter function
To obtain SR,A1(t,fτ)＝SR(t,fτ)·h1(t) selecting because the azimuthal Doppler slope of the input signal has been removed
Wherein
The direction can be recovered to the original Doppler modulation, and the result S of filtering output is obtainedR,A1(t,fτ) Performing fast Fourier transform and multiplying by frequency domain quadratic phase function
To obtain SR,A2(ft,fτ)＝FFT[SR,A1(t,fτ)]·Φ1(ft) To SR,A2(ft,fτ) Performing an inverse fast Fourier transform and multiplying by a filter function h2(t)＝exp(-jπδakat2) To obtain SR,A3(t,fτ)＝IFFT[SR,A2(ft,fτ)]·h2(t) for SR,A3(t,fτ) Performing fast Fourier transform and multiplying by frequency domain quadratic phase function
To obtain SKT(ft,fτ)＝FFT[SR,A3(t,fτ)]·Φ2(ft) Wherein δa＝fc/(fc+fτ) And completing azimuth resampling and azimuth compression for the azimuth scale transformation factor.
In the distance direction and the azimuth direction processing process, when the scale transformation principle is used for processing the slope-removed signal, 6 times of FFT or IFFT operation are needed in total, in the FPGA engineering design, a method of instantiating a plurality of FFT IP cores simultaneously can be adopted, although the design logic is simplified, the resource occupation of a DSP and an RAM is increased, the equipment scale of signal processing is enlarged, aiming at the FFT operation cost, the engineering realization of the FPGA is improved by adopting a time division multiplexing mode, one FFT IP core is instantiated and is set to be in a pipeline mode, as shown in figure 6, the input state conversion control is completed by combining a control state machine, data are loaded continuously, a large amount of hardware resources are saved, and the processing efficiency of the algorithm is ensured.
And completing azimuth processing, completing azimuth resampling and azimuth compression, enabling the signal to be still in a frequency domain in a distance dimension, performing distance IFFT (inverse fast Fourier transform) on the output signal, realizing two-dimensional focusing imaging on a target, performing modulus on two-dimensional data, and realizing data conversion from a complex number domain to an amplitude domain.
The image data in the floating point format is output as gray-scale image data, two dimensions corresponding to the image data, that is, the mean value of the distance and orientation matrices, are calculated, and the image quantization is completed by multiplying the mean value by a quantization coefficient, as shown in fig. 7.
The above-described embodiments are not intended to limit the present invention, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present invention are included in the scope of the present invention.
Claims (8)
1. A PFA FPGA parallel implementation method sends radar data to FPGA for processing, and is characterized by comprising the following steps: the data are sent through a high-speed serial bus, the data are respectively stored in a double-channel DDR1 and a double-channel DDR2 according to odd and even addresses, PFA parameters are calculated by adopting a double-pulse and double-storage RAM, fixed point to floating point conversion, angle parameter calculation, distance parameter calculation, parameter storage, distance direction interpolation axis calculation and interpolation frequency axis calculation are realized by an FPGA, data are respectively read from two groups of DDR and the RAM, distance direction and azimuth direction resampling is realized by adopting Chirp Scaling, complex data are converted into amplitude data, and floating point images are converted into gray level images.
2. The FPGA parallel implementation method of PFA according to claim 1, wherein the fixed-point to floating-point conversion comprises: and converting the distance direction point number, the azimuth direction point number and the azimuth direction sampling pulse number in the fixed point format into double-precision data.
3. The FPGA parallel implementation method of PFA according to claim 2, wherein the angle parameter calculation comprises: and calculating the flight rotation angle according to the radar data.
4. The FPGA parallel implementation method of PFA according to claim 3, wherein the distance parameter calculation comprises: calculating the distance R between the initial position, the phase center and the scene center according to the radar data and the flight rotation angleaDistance direction time axis tτDistance to frequency axis fτ。
5. The FPGA parallel implementation of PFA of claim 4, wherein the distance resampling comprises: setting light speed c, fast time tau, frequency modulation slope k and distance-to-scale conversion factor deltarSubstitution formula
Separately calculating the phase compensation factors phi of the two pulses1(tau), taking out the data sum phi of the double-channel DDR1 and DDR21(tau) complex multiplying, FFT converting the complex multiplying result, setting filter function
FFT result and H1(fτ) Complex multiplication, IFFT conversion of the complex multiplication result, and setting of carrier frequency fcSubstitution formula
Calculating a quadratic phase function phi2(τ), IFFT transform result and φ2(tau) complex multiplying, FFT converting the complex multiplying result, setting the filter factor of motion compensation
FFT result and H2(fτ) Multiple multiplication, setting the result SR(t,fτ)。
6. The FPGA parallel implementation of PFA of claim 5, wherein the azimuth resampling comprises: setting a filter function
Setting up
And
h1(t) and SR(t,fτ) Multiple multiplication SR,A1(t,fτ)＝SR(t,fτ)·h1(t) obtaining SR,A1(t,fτ)，SR,A1(t,fτ) Performing FFT to set frequency domain quadratic phase function
Multiplying the result of FFT by SR,A2(ft,fτ)＝FFT[SR,A1(t,fτ)]·Φ1(ft) Complex multiplication result SR,A2(ft,fτ) IFFT conversion is carried out, and a filter function h is set2(t)＝exp(-jπδakat2) And complex multiplication S of IFFT transform resultR,A3(t,fτ)＝IFFT[SR,A2(ft,fτ)]·h2(t), complex multiplication result SR,A3(t,fτ) Performing FFT to set an azimuth scale factor deltaa＝fc/(fc+fτ) Setting a frequency domain quadratic phase function
Multiplying the result of FFT by SKT(ft,fτ)＝FFT[SR,A3(t,fτ)]·Φ2(ft)。
7. The FPGA parallel implementation method of PFA according to claim 1, wherein the converting the complex data into amplitude data comprises: and performing distance IFFT on the frequency domain signal to realize two-dimensional focusing imaging and performing modulo on two-dimensional data.
8. The FPGA parallel implementation method of PFA according to claim 1, wherein the converting the floating point image into a grayscale image comprises: and calculating the mean value of the two-dimensional matrix corresponding to the image data, and multiplying the mean value by the quantization coefficient.
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