CN111244128A - Display panel and display device - Google Patents
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- CN111244128A CN111244128A CN201811446725.8A CN201811446725A CN111244128A CN 111244128 A CN111244128 A CN 111244128A CN 201811446725 A CN201811446725 A CN 201811446725A CN 111244128 A CN111244128 A CN 111244128A
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- 239000010409 thin film Substances 0.000 claims abstract description 142
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000010408 film Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 30
- 230000000694 effects Effects 0.000 abstract description 13
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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Abstract
The embodiment of the invention discloses a display panel and a display device. The display panel comprises a substrate and a plurality of pixel circuits formed on the substrate, wherein each pixel circuit comprises a plurality of thin film transistors, each thin film transistor comprises an active layer, and the active layers of at least two thin film transistors are positioned in different film layers. The technical scheme provided by the embodiment of the invention can improve the pixel density of the display panel, thereby improving the display effect of the display panel.
Description
Technical Field
The present invention relates to display technologies, and in particular, to a display panel and a display device.
Background
An Organic Light Emitting Diode (OLED) is an Organic thin film electroluminescent device, and has advantages of self-luminescence, low power consumption, low cost, and the like, and is receiving more and more attention.
Among the pixel circuits of the OLED display panel, the simplest 2T1C (two thin film transistors and one capacitor) pixel circuit can satisfy the basic function of display. However, in order to make the display performance of the OLED display panel more excellent, a plurality of Thin Film Transistors (TFTs) are usually additionally provided in the pixel circuit. In order to make each thin film transistor have a better driving effect, it is necessary to ensure that the size of the active layer of each thin film transistor is sufficiently large. It is obvious that for a display panel with a certain size, the larger the number of thin film transistors in a single pixel circuit, the larger the area that the single pixel circuit needs to occupy, the smaller the number of light emitting cells that can be accommodated in the display panel, and the lower the pixel density (Pixels perench, PPI) of the display panel, the poorer the display effect of the display panel.
Disclosure of Invention
The invention provides a display panel and a display device, which are used for improving the pixel density of the display panel and further improving the display effect of the display panel.
In a first aspect, an embodiment of the present invention provides a display panel, including a substrate base plate;
a plurality of pixel circuits formed on the substrate, the pixel circuits including a plurality of thin film transistors;
each thin film transistor includes an active layer;
the active layers of at least two thin film transistors are located in different film layers.
Further, the display panel includes a first semiconductor layer and a second semiconductor layer which are stacked;
the active layer comprises a first type active layer and a second type active layer; the first type of active layer is positioned in the first semiconductor layer, and the second type of active layer is positioned in the second semiconductor layer;
the thin film transistor corresponding to the first type of active layer is a first type of thin film transistor, and the thin film transistor corresponding to the second type of active layer is a second type of thin film transistor;
and each thin film transistor in the same pixel circuit is a first type thin film transistor or a second type thin film transistor.
Further, the display panel further includes a plurality of light emitting units formed on the pixel circuit; the light-emitting units are connected with the pixel circuits in a one-to-one correspondence manner;
the light-emitting units are arranged to form an array structure with M rows and N columns, and M and N are positive integers;
in the odd-numbered rows along the row direction of the array structure, all the thin film transistors in the pixel units corresponding to the odd-numbered light emitting units are first-class thin film transistors, and all the thin film transistors in the pixel units corresponding to the even-numbered light emitting units are second-class thin film transistors;
in the even-numbered rows along the row direction of the array structure, each thin film transistor in the pixel unit corresponding to the odd-numbered light emitting unit is a second-type thin film transistor, and each thin film transistor in the pixel unit corresponding to the even-numbered light emitting unit is a first-type thin film transistor.
Further, the display panel further includes a plurality of light emitting units formed on the pixel circuit; the light-emitting units are connected with the pixel circuits in a one-to-one correspondence manner;
the light-emitting units are arranged to form an array structure with M rows and N columns, and M and N are positive integers;
in any row along the row direction of the array structure, each thin film transistor in the pixel units corresponding to the odd-numbered light emitting units is a first-type thin film transistor, and each thin film transistor in the pixel units corresponding to the even-numbered light emitting units is a second-type thin film transistor.
Further, the vertical projection of all the first type active layers on the substrate base plate is a first projection;
the vertical projection of all the second type active layers on the substrate base plate is a second projection;
the first projection is not coincident with the second projection;
the display panel includes a first metal layer between the first semiconductor layer and the second semiconductor layer;
the first type thin film transistor further comprises a first gate electrode, and the second type thin film transistor further comprises a second gate electrode;
each first gate electrode and each second gate electrode are located in the first metal layer, and the first gate electrode and the second gate electrode are electrically insulated from each other.
Further, the vertical projection of all the first type active layers on the substrate base plate is a first projection; the vertical projection of all the second type active layers on the substrate base plate is a second projection;
the first projection and the second projection at least partially coincide.
Further, the display panel further comprises a plurality of scanning lines;
in the same row, the pixel units corresponding to all the light-emitting units are electrically connected with the same scanning line;
the display panel includes a first metal layer between the first semiconductor layer and the second semiconductor layer;
the first type thin film transistor further comprises a first gate electrode, and the second type thin film transistor further comprises a second gate electrode;
the first gate electrode is located in the first metal layer, and in the same row, the first gate electrode of the first type thin film transistor is simultaneously used as the second gate electrode of the second type thin film transistor adjacent to the first gate electrode.
Further, the display panel includes a first metal layer and a second metal layer between the first semiconductor layer and the second semiconductor layer;
the first metal layer is positioned between the first semiconductor layer and the second metal layer;
the first type thin film transistor further comprises a first gate electrode, and the second type thin film transistor further comprises a second gate electrode; the first gate electrode is located in the first metal layer and the second gate electrode is located in the second metal layer.
Any two of the first type active layer, the second type active layer, the first gate electrode and the second gate electrode are at least partially overlapped.
Further, the first type of thin film transistor further includes a first drain electrode and a first source electrode, and the second type of thin film transistor further includes a second drain electrode and a second source electrode, wherein a vertical projection of the first drain electrode on the substrate base plate and a vertical projection of the second drain electrode on the substrate base plate do not coincide, and a vertical projection of the first source electrode on the substrate base plate and a vertical projection of the second source electrode on the substrate base plate do not coincide.
In a second aspect, an embodiment of the present invention further provides a display device, where the display device includes any one of the display panels provided in the embodiments of the present invention.
According to the display panel provided by the embodiment of the invention, the active layers of at least two thin film transistors are positioned in different film layers, so that the problems that the number of light emitting units which can be accommodated in the display panel is smaller, the pixel density (Pixels Per Inch, PPI) of the display panel is lower and the display effect of the display panel is poorer as the number of thin film transistors in a single pixel circuit is larger and the area occupied by the single pixel circuit is larger in the existing OLED display panel are solved, and the pixel density of the display panel is improved, so that the display effect of the display panel is improved.
Drawings
Fig. 1 is a schematic cross-sectional view illustrating a display panel according to an embodiment of the present invention;
fig. 2 is a schematic top view of a display panel according to an embodiment of the present invention;
FIG. 3 is a schematic top view of another display panel according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of another display panel according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view illustrating another display panel according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, the larger the number of thin film transistors in a single pixel circuit in the conventional OLED display panel, the larger the area that the single pixel circuit needs to occupy, the smaller the number of light emitting units that can be accommodated in the display panel, and the lower the pixel density of the display panel, the poorer the display effect of the display panel.
As a result of analyzing the above problems, those skilled in the art have found that the root cause of the above problems is that, in the conventional OLED display panel, only one semiconductor layer is provided, and the active layer of each thin film transistor of each pixel unit is located in the semiconductor layer. Obviously, the area of the semiconductor layer is constant for a display panel of a certain size. In order to make each thin film transistor have a better driving effect, the size of an active layer in the thin film transistor may not be reduced. This makes the number of active layers that the semiconductor layer can accommodate limited. As the number of thin film transistors in the pixel circuit increases, the number of pixel circuits that can be provided is naturally reduced, and the pixel density of the display panel is also reduced.
In view of this, an embodiment of the present invention provides a display panel. The display panel comprises a substrate and a plurality of pixel circuits formed on the substrate, wherein each pixel circuit comprises a plurality of thin film transistors, each thin film transistor comprises an active layer, and the active layers of at least two thin film transistors are positioned in different film layers.
In the display panel provided by the embodiment of the invention, the active layers of at least two thin film transistors are positioned in different film layers, and at least two semiconductor layers are substantially manufactured in the display panel and used for manufacturing the active layers. This may allow the display panel to accommodate more active layers. Observing from display panel light-emitting side, different thin film transistors appear "interlude or overlap", and then make the area that average single pixel circuit needs to occupy reduce, single pixel circuit area that brings when having solved increase thin film transistor number among the current display panel increases, and then the problem that restriction display panel pixel density improves has reached the pixel density that improves display panel, and then improves display panel's display effect's effect.
In the above technical solution, the number of the semiconductor layers in the display panel is two or more, which is not limited in the present application.
Fig. 1 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention. When the display panel includes only two semiconductor layers, alternatively, referring to fig. 1, the display panel includes a first semiconductor layer and a second semiconductor layer which are stacked; the active layer includes a first type active layer 212 and a second type active layer 222, the first type active layer 212 is located in the first semiconductor layer, the second type active layer 222 is located in the second semiconductor layer, the thin film transistor corresponding to the first type active layer 212 is a first type thin film transistor 210, the thin film transistor corresponding to the second type active layer 222 is a second type thin film transistor 220, and the same pixel circuit may include both the first type thin film transistor 210 and the second type thin film transistor 220.
Optionally, the thin film transistors in the same pixel circuit may be the first type thin film transistor 210 or the second type thin film transistor 220. The arrangement difficulty of each pixel circuit is low, the manufacturing process is simple, and the implementation is easy.
It should be noted that fig. 1 only exemplarily shows that the display panel includes a first semiconductor layer and a second semiconductor layer, the first type active layer 212 of the first type thin film transistor 210 and the active layer 222 of the second type thin film transistor 220 are located in two different film layers, in other embodiments, the number of layers N1(N1 is a positive integer greater than 2) of the semiconductor layers of the display panel and the N1 type thin film transistor corresponding to the N1 type semiconductor layers may be set according to practical requirements, and the embodiment of the present invention is not limited thereto. In addition, the same pixel circuit may include transistors of M1 type (1 ≦ M1 ≦ N1, and M1 is smaller than the number of thin film transistors in a single pixel circuit), where the specific value of M1 and the number of thin film transistors in the same pixel circuit may be set according to actual requirements, which is not limited in this application.
If the tfts in the same pixel circuit are the first type tft 210 or the second type tft 220, there are a plurality of specific arrangement schemes, and the following description will describe in detail with reference to typical examples, but not limiting the present application.
Fig. 2 is a schematic top view of a display panel according to an embodiment of the present invention. The display panel further includes a plurality of light emitting units 410 formed on the pixel circuits, and the light emitting units 410 are connected to the pixel circuits (not shown in fig. 2) in a one-to-one correspondence. The light emitting units 410 are arranged to form an array structure with M rows and N columns, wherein M and N are positive integers, and along the row direction of the array structure, in the odd-numbered rows, all the thin film transistors in the pixel units corresponding to the odd-numbered light emitting units 410 are first-type thin film transistors, and all the thin film transistors in the pixel units corresponding to the even-numbered light emitting units 410 are second-type thin film transistors; in the row direction of the array structure, in the even-numbered row, each thin film transistor in the pixel unit corresponding to the odd-numbered light emitting unit 410 is the second-type thin film transistor, and each thin film transistor in the pixel unit corresponding to the even-numbered light emitting unit 410 is the first-type thin film transistor. In fig. 2, a pixel circuit in which each thin film transistor is a first type thin film transistor and a pixel circuit in which each thin film transistor is a second type thin film transistor are distinguished by different filling patterns.
Fig. 3 is a schematic top view of another display panel according to an embodiment of the present invention. The display panel further includes a plurality of light emitting units 410 formed on the pixel circuits, and the light emitting units 410 are connected to the pixel circuits (not shown in fig. 3) in a one-to-one correspondence. With reference to fig. 3, the light emitting units 410 are arranged to form an array structure with M rows and N columns, where M and N are positive integers, and along the row direction of the array structure, in any row, each thin film transistor in the pixel unit corresponding to the odd-numbered light emitting unit 410 is a first-type thin film transistor, and each thin film transistor in the pixel unit corresponding to the even-numbered light emitting unit 410 is a second-type thin film transistor. Similarly, in fig. 3, a pixel circuit in which each thin film transistor is a first type thin film transistor and a pixel circuit in which each thin film transistor is a second type thin film transistor are distinguished by different filling patterns.
It should be noted that the display panel provided in fig. 2 or fig. 3 may have a cross-sectional structure similar to that of fig. 1. In particular, with continued reference to fig. 1, the perpendicular projection of all the first-type active layers 212 on the substrate base plate 10 is a first projection, and the perpendicular projection of all the second-type active layers 222 on the substrate base plate 10 is a second projection, and the first projection and the second projection are not coincident. The display panel includes a first metal layer between the first semiconductor layer and the second semiconductor layer, the first thin film transistor 210 further includes a first gate electrode 211, the second thin film transistor 220 further includes a second gate electrode 221, each of the first gate electrode 211 and each of the second gate electrode 221 are located in the first metal layer, and the first gate electrode 211 and the second gate electrode 221 are electrically insulated from each other. By the arrangement, the first gate electrodes 211 and the second gate electrodes 221 can be manufactured in the same manufacturing process, the number of manufacturing processes is simplified, and the production efficiency of the display panel is improved.
Optionally, the vertical projection of all the first type active layers on the substrate base plate can be set as a first projection; the vertical projection of all the second type active layers on the substrate base plate is a second projection; the first projection and the second projection at least partially coincide. Set up like this, can be so that observe from display panel light-emitting side, different thin film transistor "alternates or the overlap" gets inseparabler for the area that average single pixel circuit needs to occupy further reduces, reaches the pixel density that further improves display panel, improves display panel's display effect's purpose.
Fig. 4 is a schematic cross-sectional view of another display panel according to an embodiment of the invention. Fig. 2 provides a schematic cross-sectional structure of the display panel similar to that of fig. 4. Specifically, referring to fig. 2 and 4, the display panel further includes a plurality of scan lines (not shown in fig. 2); in the same row, the pixel units corresponding to the light emitting units 410 are electrically connected to the same scanning line. The display panel includes a first metal layer between the first semiconductor layer and the second semiconductor layer; the first-type thin film transistor 210 further includes a first gate electrode 212, and the second-type thin film transistor 220 further includes a second gate electrode 221. The first gate electrode 212 is located in the first metal layer, and in the same row, the first gate electrode 212 of the first-type thin film transistor 210 simultaneously serves as the second gate electrode 221 of the second-type thin film transistor 220 adjacent thereto. What is essentially so arranged is that the first gate electrode 212 of the first-type thin film transistor 210 is multiplexed into the second gate electrode 221 of the second-type thin film transistor 220. And pixel circuits corresponding to the two thin film transistors in a multiplexing relationship are electrically connected with the same scanning line. The arrangement can reduce the number of gate electrode manufacturing processes, reduce the cost and improve the production efficiency of the display panel. Meanwhile, different thin film transistors can be inserted or overlapped more tightly, so that the area occupied by an average single pixel circuit is further reduced, the pixel density of the display panel is further improved, and the display effect of the display panel is improved.
Further, when the technical scheme in fig. 4 is adopted, in order to prevent two pixel circuits adjacently arranged in the same row from interfering with each other, optionally, both of the two thin film transistors in the multiplexing relationship are non-driving transistors. The driving transistor is a thin film transistor that determines the magnitude of the current flowing through the light emitting unit 410.
Fig. 5 is a schematic cross-sectional view of another display panel according to an embodiment of the invention. Fig. 2 and 3 provide display panels that may have cross-sectional structural schematics similar to fig. 5. Specifically, referring to fig. 2, 3 and 5, the display panel includes a first metal layer and a second metal layer between a first semiconductor layer and a second semiconductor layer. The first metal layer is positioned between the first semiconductor layer and the second metal layer; the first-type thin film transistor 210 further includes a first gate electrode 211, and the second-type thin film transistor 220 further includes a second gate electrode 221; the first gate electrode 211 is located in the first metal layer, and the second gate electrode 221 is located in the second metal layer; any two of the first-type active layer 212, the second-type active layer 222, the first gate electrode 211, and the second gate electrode 221 are at least partially coincident. The arrangement can further enable different thin film transistors to be more compact in insertion or overlapping, so that the area occupied by the average single pixel circuit is further reduced, the pixel density of the display panel is further improved, and the display effect of the display panel is improved.
It should be noted that fig. 4 and fig. 5 only exemplarily show that the vertical projection of the first type active layer 212 of the first type thin film transistor 210 on the substrate 10 is located within the vertical projection of the second type active layer 222 of the second type thin film transistor 220 on the substrate 10, which is only a specific example of the present application and is not a limitation of the present application. It can be understood that the higher the degree to which the vertical projection of the first type active layer 212 of the first type thin film transistor 210 on the substrate base plate 10 and the vertical projection of the second type active layer 222 of the second type thin film transistor 220 on the substrate base plate 10 coincide, the greater the pixel density of the display device.
Optionally, the first-type thin film transistor 210 of the display panel may further include a first drain electrode 213 and a first source electrode 214, and the second-type thin film transistor 220 may further include a second drain electrode 223 and a second source electrode 224, where a vertical projection of the first drain electrode 213 on the substrate 10 and a vertical projection of the second drain electrode 223 on the substrate 10 are not overlapped, and a vertical projection of the first source electrode 214 on the substrate 10 and a vertical projection of the second source electrode 224 on the substrate 10 are not overlapped.
Note that, in order to make the vertical projection of the first drain electrode 213 on the base substrate 10 and the vertical projection of the second drain electrode 223 on the base substrate 10 not coincide with each other, the vertical projection of the first source electrode 214 on the base substrate 10 and the vertical projection of the second source electrode 224 on the base substrate 10 do not coincide with each other, and the above embodiment is referred to, but the present application is not limited thereto.
Based on the same inventive concept, the embodiment of the invention also provides a display device. Fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present invention. The display device 1 includes any of the display panels 20 described above.
Since the display device 1 includes any of the display panels 20 described above, the display device 1 has the same or corresponding functions and advantages as or to the display panel included therein.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A display panel, comprising:
a substrate base plate;
a plurality of pixel circuits formed on the substrate, the pixel circuits including a plurality of thin film transistors;
each of the thin film transistors includes an active layer;
the active layers of at least two of the thin film transistors are located in different film layers.
2. The display panel according to claim 1, wherein the display panel comprises a first semiconductor layer and a second semiconductor layer which are stacked;
the active layers comprise a first type active layer and a second type active layer; the first type active layer is positioned in the first semiconductor layer, and the second type active layer is positioned in the second semiconductor layer;
the thin film transistor corresponding to the first type active layer is a first type thin film transistor, and the thin film transistor corresponding to the second type active layer is a second type thin film transistor;
and each thin film transistor in the same pixel circuit is the first type thin film transistor or the second type thin film transistor.
3. The display panel according to claim 2, further comprising a plurality of light emitting units formed over the pixel circuit; the light emitting units are connected with the pixel circuits in a one-to-one correspondence manner;
the light-emitting units are arranged to form an array structure with M rows and N columns, and M and N are positive integers;
along the row direction of the array structure, in an odd-numbered row, each thin film transistor in the pixel unit corresponding to the odd-numbered light-emitting unit is a first-class thin film transistor, and each thin film transistor in the pixel unit corresponding to the even-numbered light-emitting unit is a second-class thin film transistor;
in the even-numbered rows along the row direction of the array structure, each thin film transistor in the pixel unit corresponding to the odd-numbered light emitting units is a second-type thin film transistor, and each thin film transistor in the pixel unit corresponding to the even-numbered light emitting units is a first-type thin film transistor.
4. The display panel according to claim 2, further comprising a plurality of light emitting units formed over the pixel circuit; the light emitting units are connected with the pixel circuits in a one-to-one correspondence manner;
the light-emitting units are arranged to form an array structure with M rows and N columns, and M and N are positive integers;
in any row along the row direction of the array structure, each thin film transistor in the pixel units corresponding to the odd-numbered light emitting units is a first-type thin film transistor, and each thin film transistor in the pixel units corresponding to the even-numbered light emitting units is a second-type thin film transistor.
5. The display panel according to claim 3 or 4, wherein a vertical projection of all the first type active layers on the substrate base plate is a first projection;
the vertical projection of all the second active layers on the substrate base plate is a second projection;
the first projection is not coincident with the second projection;
the display panel includes a first metal layer between the first semiconductor layer and a second semiconductor layer;
the first type thin film transistor further comprises a first gate electrode, and the second type thin film transistor further comprises a second gate electrode;
each of the first gate electrodes and each of the second gate electrodes are located in the first metal layer, and the first gate electrodes and the second gate electrodes are electrically insulated from each other.
6. The display panel according to claim 4,
the vertical projection of all the first type active layers on the substrate base plate is a first projection;
the vertical projection of all the second active layers on the substrate base plate is a second projection;
the first projection and the second projection at least partially coincide.
7. The display panel according to claim 6, wherein the display panel further comprises a plurality of scan lines;
in the same row, the pixel units corresponding to the light-emitting units are electrically connected with the same scanning line;
the display panel includes a first metal layer between the first semiconductor layer and a second semiconductor layer;
the first type thin film transistor further comprises a first gate electrode, and the second type thin film transistor further comprises a second gate electrode;
the first gate electrode is located in the first metal layer, and in the same row, the first gate electrode of the first type thin film transistor simultaneously serves as the second gate electrode of the second type thin film transistor adjacent thereto.
8. The display panel according to claim 6, wherein the display panel comprises a first metal layer and a second metal layer between the first semiconductor layer and the second semiconductor layer;
the first metal layer is positioned between the first semiconductor layer and the second metal layer;
the first type thin film transistor further comprises a first gate electrode, and the second type thin film transistor further comprises a second gate electrode; the first gate electrode is located in the first metal layer, and the second gate electrode is located in the second metal layer;
any two of the first type active layer, the second type active layer, the first gate electrode and the second gate electrode are at least partially overlapped.
9. The display panel according to claim 2, wherein the first-type thin film transistor further comprises a first drain electrode and a first source electrode, and wherein the second-type thin film transistor further comprises a second drain electrode and a second source electrode, wherein a perpendicular projection of the first drain electrode on the base substrate and a perpendicular projection of the second drain electrode on the base substrate do not coincide, and wherein a perpendicular projection of the first source electrode on the base substrate and a perpendicular projection of the second source electrode on the base substrate do not coincide.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
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| CN201811446725.8A CN111244128A (en) | 2018-11-29 | 2018-11-29 | Display panel and display device |
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| CN201811446725.8A CN111244128A (en) | 2018-11-29 | 2018-11-29 | Display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115440162A (en) * | 2022-11-09 | 2022-12-06 | 惠科股份有限公司 | Display panel and display device |
| WO2024036766A1 (en) * | 2022-08-16 | 2024-02-22 | 武汉华星光电技术有限公司 | Array substrate and display panel |
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| CN106257677A (en) * | 2015-06-19 | 2016-12-28 | 乐金显示有限公司 | Thin film transistor base plate and the display device of this thin film transistor base plate of use |
| CN106158882A (en) * | 2016-09-27 | 2016-11-23 | 厦门天马微电子有限公司 | A kind of display device, display floater, array base palte and preparation method thereof |
| CN107154407A (en) * | 2017-05-17 | 2017-09-12 | 厦门天马微电子有限公司 | Laminated film transistor device and its manufacture method, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024036766A1 (en) * | 2022-08-16 | 2024-02-22 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN115440162A (en) * | 2022-11-09 | 2022-12-06 | 惠科股份有限公司 | Display panel and display device |
| US11967282B2 (en) | 2022-11-09 | 2024-04-23 | HKC Corporation Limited | Display panel and display device |
| WO2024098772A1 (en) * | 2022-11-09 | 2024-05-16 | 惠科股份有限公司 | Display panel and display apparatus |
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