CN111240115B - Thin film transistor array substrate, manufacturing method thereof and liquid crystal display panel - Google Patents
Thin film transistor array substrate, manufacturing method thereof and liquid crystal display panel Download PDFInfo
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- CN111240115B CN111240115B CN202010184870.4A CN202010184870A CN111240115B CN 111240115 B CN111240115 B CN 111240115B CN 202010184870 A CN202010184870 A CN 202010184870A CN 111240115 B CN111240115 B CN 111240115B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
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- Optics & Photonics (AREA)
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Abstract
A thin film transistor array substrate, a manufacturing method thereof and a liquid crystal display panel are provided, wherein the thin film transistor array substrate comprises: the liquid crystal display device comprises a substrate, a grid electrode, a scanning line connected with the grid electrode, a grid electrode insulating layer, an active layer, a source electrode, a drain electrode, a first insulating layer, a common electrode layer, a second insulating layer, a pixel electrode layer and a data line; the common electrode layer is provided with through holes corresponding to the source electrode and the drain electrode, the pixel electrode layer is electrically connected with the source electrode through a first contact hole, and the first contact hole penetrates through the second insulating layer and the first insulating layer; the data line is electrically connected with the drain electrode through a second contact hole, and the second contact hole penetrates through the third insulating layer, the second insulating layer and the first insulating layer; according to the invention, the source electrode, the drain electrode and the data line are stacked, and further the first contact hole for connecting the source electrode and the pixel electrode, and the second contact hole for connecting the data line and the drain electrode are also stacked with the data line, so that the width of the opening region along the extension direction of the scanning line is increased, and the opening ratio is increased.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor array substrate, a manufacturing method thereof and a liquid crystal display panel.
Background
At present, High Definition Display devices (HD) and Full High Definition Display devices (FHD) are becoming popular, and Liquid Crystal Display (LCD) with High resolution and High transmittance is a trend.
Fig. 1 is a schematic view of a partial plan structure of a thin film transistor array substrate in the prior art, which includes a plurality of scan lines 101, a plurality of data lines 102, and a plurality of pixel units defined by the plurality of scan lines 101 and the plurality of data lines 102 crossing each other. The pixel unit is provided with a gate connected to the scan line 101, an active layer 103 over the gate, a source electrode 104 and a drain electrode 105 respectively contacting the active layer 103, and a pixel electrode 106. Since one or more insulating layers are sandwiched between the source electrode 104 and the pixel electrode 106, a contact hole 107 needs to be formed on the insulating layer by etching so that the pixel electrode 106 fills the contact hole 107 and is electrically connected to the source electrode 104, and in order to ensure a sufficiently reliable connection between the pixel electrode 106 and the source electrode 104, the contact hole 107 needs to occupy a certain area, and further, the source electrode 104 needs to be designed to be larger in size to be stably and electrically connected to the pixel electrode 106 filled in the contact hole 107, and the black matrix on the color filter substrate needs to be correspondingly manufactured to have a size matched with the area of the source electrode 104 so as to shield the source electrode 104, so that the aperture ratio of a pixel unit in the finally manufactured liquid crystal display panel is low.
Disclosure of Invention
The invention aims to provide a thin film transistor array substrate, a manufacturing method thereof and a liquid crystal display panel, which solve the problem of low aperture opening ratio of a pixel unit in the liquid crystal display panel and further reduce the power consumption of a product.
The present invention provides a thin film transistor array substrate, which includes:
a substrate;
a first metal layer on the substrate; the first metal layer comprises a grid and a scanning line connected with the grid;
a gate insulating layer covering the first metal layer;
an active layer on the gate insulating layer;
a second metal layer on the gate insulating layer; the second metal layer comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively contacted with the active layer;
a first insulating layer covering the second metal layer;
a common electrode layer on the first insulating layer; the common electrode layer is provided with through holes corresponding to the source electrode and the drain electrode, and the through holes expose the first insulating layer covering the source electrode and the drain electrode;
a second insulating layer covering the common electrode layer and the first insulating layer;
a pixel electrode layer on the second insulating layer; the pixel electrode layer is electrically connected with the source electrode through a first contact hole, and the first contact hole penetrates through the second insulating layer and the first insulating layer;
a third insulating layer covering the pixel electrode layer and the second insulating layer;
a third metal layer on the third insulating layer; the third metal layer comprises a data line, the data line is electrically connected with the drain electrode through a second contact hole, and the second contact hole penetrates through the third insulating layer, the second insulating layer and the first insulating layer.
Further, the first contact hole and the second contact hole are sequentially disposed in an extending direction of the data line.
Further, the projection of the data line on the substrate covers the first contact hole.
Further, the projection of the data line on the substrate also covers the source electrode, the drain electrode and a channel between the source electrode and the drain electrode.
Furthermore, the source electrode and the drain electrode are sequentially arranged in the extending direction of the data line, and a channel between the source electrode and the drain electrode is in a linear shape perpendicular to the data line.
Further, the data line is provided with a plurality of expansions and a plurality of connecting parts, and the expansions and the connecting parts are arranged at intervals in the extending direction of the data line; the projection of the widening on the substrate covers the source electrode, the drain electrode, a channel between the source electrode and the drain electrode, the first contact hole and the second contact hole.
Further, the common electrode layer covers the first insulating layer in a planar manner except for the through holes.
Further, the pixel electrode layer comprises a plurality of pixel electrodes, each pixel electrode comprises an outer frame and a plurality of comb strips connected in the outer frame, each comb strip comprises a straight line part extending perpendicular to the data line and two folding line parts respectively located on two sides of the straight line part, and the distance between the straight line part and the data line is smaller than 5 μm.
The invention also provides a liquid crystal display panel which comprises a color film substrate, a thin film transistor array substrate and a liquid crystal layer positioned between the color film substrate and the thin film transistor array substrate, wherein the thin film transistor array substrate is any one of the thin film transistor array substrates.
The invention also provides a manufacturing method of the thin film transistor array substrate, which comprises the following steps:
depositing a first metal film on a substrate, and patterning the first metal film to form a first metal layer, wherein the first metal layer comprises a grid and a scanning line connected with the grid;
depositing a gate insulating layer on the substrate covering the first metal layer;
depositing an active layer film on the gate insulating layer, and patterning the active layer film to form an active layer;
depositing a second metal film on the gate insulating layer, and patterning the second metal film to form a second metal layer, wherein the second metal layer comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively in contact with the active layer;
depositing a first insulating layer covering the second metal layer on the gate insulating layer;
depositing a first transparent conductive film on the first insulating layer, and patterning the first transparent conductive film to form a common electrode layer, wherein the common electrode layer is provided with through holes arranged corresponding to the source electrode and the drain electrode, and the first insulating layer covering the source electrode and the drain electrode is exposed out of the through holes;
depositing a second insulating layer covering the common electrode layer and the first insulating layer on the common electrode layer;
patterning the second insulating layer and the first insulating layer to form a first contact hole penetrating through the second insulating layer and the first insulating layer, wherein the bottom of the first contact hole exposes part of the surface of the source electrode;
depositing a second transparent conductive film on the second insulating layer, patterning the second transparent conductive film to form a pixel electrode layer, and filling the pixel electrode layer into the first contact hole to be electrically connected with the source electrode;
depositing a third insulating layer covering the pixel electrode layer on the second insulating layer;
patterning the third insulating layer, the second insulating layer and the first insulating layer to form a second contact hole penetrating through the third insulating layer, the second insulating layer and the first insulating layer, wherein the bottom of the second contact hole exposes a part of the surface of the drain electrode;
and depositing a third metal film on the third insulating layer, and patterning the third metal film to form a third metal layer, wherein the third metal layer comprises a data line, and the data line is filled in the second contact hole and is electrically connected with the drain electrode.
The invention provides a thin film transistor array substrate, a manufacturing method thereof and a liquid crystal display panel, wherein a source electrode, a drain electrode and a data line are stacked, a first contact hole for connecting the source electrode and a pixel electrode, and a second contact hole for connecting the data line and the drain electrode are also stacked with the data line, the first contact hole and the source electrode in contact with the first contact hole do not need to additionally occupy the layout space between the data line and the pixel electrode, in a pixel unit with the same length and width, the pixel electrode can occupy larger space in the first direction, the width of an opening area along the extension direction of a scanning line can be further increased, and the opening ratio is increased.
Drawings
Fig. 1 is a schematic partial plan view of a thin film transistor array substrate in the prior art.
Fig. 2 is a schematic partial plan view of a tft array substrate according to an embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of the thin film transistor array substrate shown in fig. 2 along a sectional line a-a.
Fig. 4 is a schematic plan view of a part of the elements in the thin film transistor array substrate shown in fig. 2.
Fig. 5a to 5h are schematic plan views illustrating a manufacturing process of the thin film transistor array substrate shown in fig. 2.
Fig. 6a to 6h are schematic cross-sectional views of the thin film transistor array substrate shown in fig. 2 during a manufacturing process.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
The thin film transistor array substrate of the present embodiment includes a plurality of scan lines 11 and a plurality of data lines 18, and the plurality of scan lines 11 and the plurality of data lines 18 are insulated from each other and cross to define a plurality of pixel units.
Fig. 2 is a partial plan view of the tft array substrate in this embodiment, which shows a complete pixel unit and a partial peripheral structure, and omits a plurality of insulating layers, and fig. 3 is a schematic cross-sectional view of the tft array substrate along a line a-a in fig. 2. As shown in fig. 2 and 3, the thin film transistor array substrate includes a substrate 10, a first metal layer on the substrate 10, a gate insulating layer 12 covering the first metal layer, an active layer 13 on the gate insulating layer 12, a second metal layer on the gate insulating layer 12, a first insulating layer 151 covering the second metal layer, a common electrode layer 16 on the first insulating layer 151, a second insulating layer 152 covering the common electrode layer 16 and the first insulating layer 151, a pixel electrode layer 17 on the second insulating layer 152, a third insulating layer 153 covering the pixel electrode layer 17 and the second insulating layer 152, and a third metal layer on the third insulating layer 153.
The first metal layer includes a gate 111 and a scan line 11 connected to the gate 111, the scan line 11 extends along a first direction X, and the gate 111 is connected to an upper side or a lower side of the scan line 11.
The active layer 13 is island-shaped, and the gate insulating layer 12 is disposed above the gate electrode 111.
The second metal layer includes a source electrode 141 and a drain electrode 142, the source electrode 141 and the drain electrode 142 are in contact with the active layer 13, respectively, and a channel is formed between the source electrode 141 and the drain electrode 142. It should be noted that in this embodiment, the source electrode 141 and the drain electrode 142 respectively refer to two channel terminals of the thin film transistor, and in practical applications, the two terminals may be interchanged.
The common electrode layer 16 is provided with a through hole 161 disposed corresponding to the source and drain electrodes 141 and 142, and the through hole 161 exposes the first insulating layer 151 covering over the source and drain electrodes 141 and 142.
A first contact hole 171 penetrating the second insulating layer 152 and the first insulating layer 151 is formed above the source electrode 141, and the pixel electrode layer 17 is electrically connected to the source electrode 141 through the first contact hole 171. The pixel electrode layer 17 includes a plurality of discrete pixel electrodes 170, and each pixel electrode 170 is located in a corresponding pixel region.
A second contact hole 181 penetrating the third insulating layer 153, the second insulating layer 152, and the first insulating layer 151 is disposed above the drain electrode 142, the data line 18 is electrically connected to the drain electrode 142 through the second contact hole 181, and the data line 18 extends in a second direction Y perpendicular to the first direction X.
Specifically, the substrate 10 may be a glass substrate or a plastic substrate. The gate insulating layer 12, the first insulating layer 151, the second insulating layer 152, and the third insulating layer 153 are formed of an inorganic insulating material, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (sion x), or an organic insulating material. The first metal layer, the second metal layer, and the third metal layer may be a metal or an alloy such as Cr, W, Ti, Ta, Mo, Al, or Cu, or may be a composite film formed of a plurality of metal films. The active layer 13 may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), a metal oxide semiconductor (e.g., IGZO, ITZO), or the like. The common electrode and the pixel electrode 170 are made of a transparent conductive material, such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or aluminum zinc oxide.
In this embodiment, the first contact hole 171 and the second contact hole 181 are sequentially disposed in the extending direction of the data line 18, the source electrode 141 and the drain electrode 142 are sequentially disposed in the extending direction of the data line 18, and the channel between the source electrode 141 and the drain electrode 142 is in a straight line shape perpendicular to the data line 18, that is, the source electrode 141 and the drain electrode 142 are oppositely disposed at the edges of the channel at both sides perpendicular to the data line 18. The projection of the data line 18 on the substrate 10 covers the first contact hole 171, and accordingly the data line 18 covers a portion of the pixel electrode layer 17 filling the first contact hole 171, and also covers the source electrode 141, the drain electrode 142, and the channel between the source electrode 141 and the drain electrode 142.
As shown in fig. 2 and 3, the source electrode 141, the drain electrode 142 and the data line 18 are stacked, and the first contact hole 171 connecting the source electrode 141 and the pixel electrode 170, and the second contact hole 181 connecting the data line 18 and the drain electrode 142 are also stacked on the data line 18, and the first contact hole 171 and the source electrode 141 in contact therewith do not need to additionally occupy a layout space between the data line 18 and the pixel electrode 170, and in a pixel unit with the same length and width, the pixel electrode 170 can occupy a larger space in the first direction X, and thus the width of the opening area AA along the extending direction of the scan line 11 can be increased, and the aperture ratio can be increased.
Further, the data line 18 is provided with a plurality of widened portions 183 and a plurality of connecting portions 182, and the plurality of widened portions 183 and the plurality of connecting portions 182 are provided at intervals in the extending direction of the data line 18. The projection of the widened portion 183 on the substrate 10 covers the source electrode 141, the drain electrode 142, the channel between the source electrode 141 and the drain electrode 142, the first contact hole 171, and the second contact hole 181, and the connection portion 182 intersects with the scan line 11 in an insulated manner. The width of the widened portion 183 in the first direction X is, for example, 10 μm to 20 μm, the width of the connection portion 182 in the first direction X is, for example, 3 μm to 8 μm, and the widths of the first contact hole 171 and the second contact hole 181 in the first direction X are, for example, 3 μm to 8 μm. The widened portion 183 has a width greater than that of the connection portion 182 so that the data line 18 and the drain electrode 142 can be stably electrically connected at the second contact hole 181, and the widened portion 183 can correspondingly cover the source electrode 141, the drain electrode 142, and the first contact hole 171. The width of the connection portion 182 is small, and parasitic capacitance between the data line 18 and the scan line 11 is reduced.
Further, the present embodiment is described by taking an FFS (fringe field switching) display mode as an example, but the present invention is not limited thereto. The common electrode layer 16 is spread over the first insulating layer 151 except for the through-holes 161. Fig. 4, in conjunction with fig. 2 and fig. 4, shows a schematic plan view of a part of the elements in fig. 2, in which only the scan lines 11, the data lines 18, and the pixel electrodes 170 are shown. The pixel electrodes 170 are in a comb-like structure, each pixel electrode 170 includes a peripheral frame 172 and a plurality of comb bars 173 connected in the peripheral frame 172, fig. 4 shows the structure of only one comb bar 173 for clarity, and in practical application, the plurality of comb bars are sequentially arranged in the second direction Y. Each comb finger 173 includes a straight line portion 17a extending perpendicular to the data line 18 and two fold line portions 17b respectively disposed at both sides of the straight line portion 17a, the straight line portion 17a and the fold line portions 17b form an included angle therebetween, and a proximal end distance L3 between the straight line portion 17a and the data line 18 is less than 5 μm.
The embodiment also discloses a liquid crystal display panel, which comprises a color film substrate, a thin film transistor array substrate and a liquid crystal layer positioned between the color film substrate and the thin film transistor array substrate, wherein the thin film transistor array substrate is any one of the thin film transistor array substrates. The liquid crystal display panel is provided with a plurality of opening areas AA corresponding to the plurality of pixel units, and the opening areas AA are positioned in the corresponding pixel units and have smaller areas than the pixel units. The color film substrate comprises a black matrix and a color filter layer, the black matrix is provided with a notch corresponding to the opening area AA and covers the area of the color film substrate except the opening area AA, and the color filter layer is filled in the opening of the black matrix. The black matrix is required to cover the scan line 11, the data line 18, the source 141, the drain 142, and the area around the same within a certain range, so as to avoid light leakage and metal layer reflection, and ensure display quality. The folding line portion 17b of the comb stripe 173 in the pixel electrode 170 is used to improve the response speed of the liquid crystal layer, and the black matrix covers the folding line portion 17b entirely or at least partially because the display effect of the region corresponding to the folding line portion 17b is not good.
The comparison is made by taking as an example that the length of the pixel cell along the first direction X is 90 μm and the width along the second direction Y is 30 μm. Referring to FIG. 1, in the prior art, the length L1 of the opening area AA in a pixel cell is 53 μm, and the width H1 is 22 μm. Referring to fig. 2, in the embodiment, the length L2 of the opening area AA in the pixel unit is 64 μm, and the width H2 is 22 μm, and the source electrode 141, the drain electrode 142 and the data line 18 are stacked, so that the distance between the straight portion 17a of the pixel electrode 170 and the data line 18 is reduced, the length of the pixel electrode 170 along the extending direction of the scan line 11 is increased, and the opening ratio of the pixel unit is increased. As compared with the above, the black matrix covers all the folding line portions 17b of the pixel electrodes 170, and it can be understood that the tft array substrate of the present embodiment has an aperture ratio larger than that of the prior art even if the area of the pixel unit is changed or the range of the black matrix covering the folding line portions 17b of the pixel electrodes 170 is changed simultaneously.
Referring to fig. 5a to 5h and fig. 6a to 6h, the present embodiment further provides a method for manufacturing a thin film transistor array substrate, where fig. 5a to 5h show a schematic plan structure diagram of the thin film transistor array substrate in the manufacturing process of the present embodiment, fig. 6a to 6h show a schematic cross-sectional structure diagram of the thin film transistor array substrate in the manufacturing process of the present embodiment, and the manufacturing method includes the following steps:
referring to fig. 5a and fig. 6a, a first metal film is deposited on a substrate 10, and the first metal film is patterned to form a first metal layer, where the first metal layer includes a gate 111 and a scan line 11 connected to the gate 111;
depositing a gate insulating layer 12 covering the first metal layer on the substrate 10;
referring to fig. 5b and 6b, an active layer film is deposited on the gate insulating layer 12, and the active layer film is patterned to form an active layer 13; the active layer 13 may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), a metal oxide semiconductor (e.g., IGZO, ITZO), or the like;
referring to fig. 5c and 6c, a second metal film is deposited on the gate insulating layer 12, and the second metal film is patterned to form a second metal layer, where the second metal layer includes a source electrode 141 and a drain electrode 142, and the source electrode 141 and the drain electrode 142 are respectively in contact with the active layer 13;
depositing a first insulating layer 151 covering the second metal layer on the gate insulating layer 12;
referring to fig. 5d and fig. 6d, a first transparent conductive film is deposited on the first insulating layer 151, and the first transparent conductive film is patterned to form a common electrode layer 16, wherein the common electrode layer 16 has a through hole 161 corresponding to the source electrode 141 and the drain electrode 142, and the through hole 161 exposes the first insulating layer 151 covering the source electrode 141 and the drain electrode 142; preferably, the common electrode layer 16 is spread over the first insulating layer 151 except for the through-hole 161;
referring to fig. 5e and fig. 6e, a second insulating layer 152 covering the common electrode layer 16 and the first insulating layer 151 is deposited on the common electrode layer 16; patterning the second insulating layer 152 and the first insulating layer 151 to form a first contact hole 171 penetrating the second insulating layer 152 and the first insulating layer 151, a bottom of the first contact hole 171 exposing a portion of the surface of the source electrode 141;
referring to fig. 5f and fig. 6f, a second transparent conductive film is deposited on the second insulating layer 152, the second transparent conductive film is patterned to form a pixel electrode layer 17, and the pixel electrode layer 17 is filled in the first contact hole 171 and electrically connected to the source electrode 141;
referring to fig. 5g and fig. 6g, a third insulating layer 153 covering the pixel electrode layer 17 is deposited on the second insulating layer 152; patterning the third insulating layer 153, the second insulating layer 152, and the first insulating layer 151 to form a second contact hole 181 penetrating the third insulating layer 153, the second insulating layer 152, and the first insulating layer 151, a bottom of the second contact hole 181 exposing a portion of the surface of the drain electrode 142;
referring to fig. 5h and 6h, a third metal film is deposited on the third insulating layer 153, and the third metal film is patterned to form a third metal layer, where the third metal layer includes the data line 18, and the data line 18 is filled in the second contact hole 181 and electrically connected to the drain electrode 142.
The first contact hole 171 and the second contact hole 181 are sequentially disposed in the extending direction of the data line 18, the source electrode 141 and the drain electrode 142 are sequentially disposed in the extending direction of the data line 18, and a channel between the source electrode 141 and the drain electrode 142 is in a straight line shape perpendicular to the data line 18, that is, the source electrode 141 and the drain electrode 142 are oppositely disposed at edges of two sides of the channel and perpendicular to the data line 18. The projection of the data line 18 on the substrate 10 covers the first contact hole 171, and accordingly the data line 18 covers a portion of the pixel electrode layer 17 filling the first contact hole 171, and also covers the source electrode 141, the drain electrode 142, and the channel between the source electrode 141 and the drain electrode 142.
The patterning step is, for example, dry etching or wet etching, and is not limited thereto.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features are not contradictory, the scope of the present description should be considered as being described in the present specification.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. A thin film transistor array substrate, comprising:
a substrate (10);
a first metal layer located on the substrate (10); the first metal layer comprises a grid (111) and a scanning line (11) connected with the grid (111);
a gate insulating layer (12) covering the first metal layer;
an active layer (13) on the gate insulating layer (12);
a second metal layer on the gate insulating layer (12); the second metal layer comprises a source electrode (141) and a drain electrode (142), the source electrode (141) and the drain electrode (142) being in contact with the active layer (13), respectively;
a first insulating layer (151) covering the second metal layer;
a common electrode layer (16) on the first insulating layer (151); the common electrode layer (16) is provided with a through hole (161) arranged corresponding to the source electrode (141) and the drain electrode (142), and the through hole (161) exposes the first insulating layer (151) covering the source electrode (141) and the drain electrode (142);
a second insulating layer (152) covering the common electrode layer (16) and the first insulating layer (151);
a pixel electrode layer (17) on the second insulating layer (152); the pixel electrode layer (17) is electrically connected with the source electrode (141) through a first contact hole (171), and the first contact hole (171) penetrates through the second insulating layer (152) and the first insulating layer (151);
a third insulating layer (153) covering the pixel electrode layer (17) and the second insulating layer (152);
a third metal layer on the third insulating layer (153); the third metal layer comprises a data line (18), the data line (18) is electrically connected with the drain electrode (142) through a second contact hole (181), the second contact hole (181) penetrates through the third insulating layer (153), the second insulating layer (152) and the first insulating layer (151), the projection of the data line (18) on the substrate (10) covers the first contact hole (171), the source electrode (141), the drain electrode (142) and a channel between the source electrode (141) and the drain electrode (142), and the first contact hole (171) and the second contact hole (181) are sequentially arranged in the extending direction of the data line (18).
2. The thin film transistor array substrate of claim 1, wherein the source electrode (141) and the drain electrode (142) are sequentially disposed in an extending direction of the data line (18), and a channel between the source electrode (141) and the drain electrode (142) is in a straight line shape perpendicular to the data line (18).
3. The thin film transistor array substrate of claim 1, wherein the data line (18) is provided with a plurality of widenings (183) and a plurality of connection portions (182), the plurality of widenings (183) and the plurality of connection portions (182) being arranged at intervals in an extending direction of the data line (18); the projection of the widening (183) on the substrate (10) covers the source (141), the drain (142), a channel between the source (141) and the drain (142), the first contact hole (171) and the second contact hole (181).
4. The thin film transistor array substrate of claim 1, wherein the common electrode layer (16) is formed to cover a region of the first insulating layer (151) except for the through hole (161).
5. The thin film transistor array substrate of claim 1, wherein the pixel electrode layer (17) comprises a plurality of pixel electrodes (170), each of the pixel electrodes (170) comprises a peripheral frame (172) and a plurality of comb strips (173) connected within the peripheral frame (172), the comb strips (173) comprise a straight line portion (17a) extending perpendicular to the data line (18) and two folded line portions (17b) respectively located at both sides of the straight line portion (17a), and a proximal end distance (L3) between the straight line portion (17a) and the data line (18) is less than 5 μm.
6. A liquid crystal display panel comprises a color film substrate, a thin film transistor array substrate and a liquid crystal layer positioned between the color film substrate and the thin film transistor array substrate, and is characterized in that the thin film transistor array substrate is the thin film transistor array substrate according to any one of claims 1 to 5.
7. A manufacturing method of a thin film transistor array substrate is characterized by comprising the following steps:
depositing a first metal film on a substrate (10), and patterning the first metal film to form a first metal layer, wherein the first metal layer comprises a grid (111) and a scanning line (11) connected with the grid (111);
depositing a gate insulating layer (12) on the substrate (10) covering the first metal layer;
depositing an active layer thin film on the gate insulating layer (12), and patterning the active layer thin film to form an active layer (13);
depositing a second metal film on the gate insulating layer (12), and patterning the second metal film to form a second metal layer, wherein the second metal layer comprises a source electrode (141) and a drain electrode (142), and the source electrode (141) and the drain electrode (142) are respectively in contact with the active layer (13);
depositing a first insulating layer (151) on the gate insulating layer (12) covering the second metal layer;
depositing a first transparent conductive film on the first insulating layer (151), patterning the first transparent conductive film to form a common electrode layer (16), wherein the common electrode layer (16) is provided with a through hole (161) corresponding to the source electrode (141) and the drain electrode (142), and the through hole (161) exposes the first insulating layer (151) covering the source electrode (141) and the drain electrode (142);
depositing a second insulating layer (152) on the common electrode layer (16) covering the common electrode layer (16) and the first insulating layer (151);
patterning the second insulating layer (152) and the first insulating layer (151) to form a first contact hole (171) penetrating through the second insulating layer (152) and the first insulating layer (151), wherein the bottom of the first contact hole (171) exposes a part of the surface of the source electrode (141);
depositing a second transparent conductive film on the second insulating layer (152), patterning the second transparent conductive film to form a pixel electrode layer (17), wherein the pixel electrode layer (17) fills the first contact hole (171) and is electrically connected with the source electrode (141);
depositing a third insulating layer (153) covering the pixel electrode layer (17) on the second insulating layer (152);
patterning the third insulating layer (153), the second insulating layer (152), and the first insulating layer (151) to form a second contact hole (181) penetrating the third insulating layer (153), the second insulating layer (152), and the first insulating layer (151), a bottom of the second contact hole (181) exposing a portion of a surface of the drain electrode (142), the first contact hole (171) and the second contact hole (181) being sequentially disposed in an extending direction of a data line (18);
depositing a third metal film on the third insulating layer (153), patterning the third metal film to form a third metal layer, wherein the third metal layer comprises a data line (18), a projection of the data line (18) on the substrate (10) covers the first contact hole (171), the source electrode (141), the drain electrode (142) and a channel between the source electrode (141) and the drain electrode (142), and the data line (18) is filled in the second contact hole (181) and electrically connected with the drain electrode (142).
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| CN113690254A (en) * | 2021-08-16 | 2021-11-23 | 昆山龙腾光电股份有限公司 | Array substrate and display panel |
| CN114156285B (en) * | 2021-11-30 | 2023-08-22 | 武汉华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN114690493B (en) * | 2022-03-18 | 2024-04-09 | 武汉华星光电技术有限公司 | Display Panel |
| CN114690490A (en) * | 2022-03-18 | 2022-07-01 | 武汉华星光电技术有限公司 | Array substrate and display panel thereof |
| CN115064560A (en) * | 2022-07-08 | 2022-09-16 | 福建华佳彩有限公司 | Low-stress insulating layer and oxide TFT array substrate carrying same |
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