CN111226308A - Semiconductor device with high-stability bonding layer and preparation method thereof - Google Patents

Semiconductor device with high-stability bonding layer and preparation method thereof Download PDF

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Publication number
CN111226308A
CN111226308A CN201880067522.XA CN201880067522A CN111226308A CN 111226308 A CN111226308 A CN 111226308A CN 201880067522 A CN201880067522 A CN 201880067522A CN 111226308 A CN111226308 A CN 111226308A
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China
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metal
semiconductor chip
layer
substrate
semiconductor device
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CN201880067522.XA
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Chinese (zh)
Inventor
杨人毅
许�鹏
滕辉
李晓勇
陈特伟
韩梅
张韧
魏雷
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication of CN111226308A publication Critical patent/CN111226308A/en
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Abstract

The embodiment of the application discloses a semiconductor device (400) and a preparation method thereof, wherein in the semiconductor device (400), an adhesive layer (43) for adhering a semiconductor chip (41) and a substrate (42) is composed of sintered metal prepared by a metal powder sintering process with high electric and heat conductivity. In the present embodiment, at least a part of the hollow (431) existing inside the sintered metal is filled with a specific material. Thus, the cavity 431 is filled with a specific material, which is advantageous for reducing moisture accommodation, thereby reducing the possibility of delamination of the chip 41 and the substrate 42 when the semiconductor device 400 is reflow-mounted on a printed wiring board. In addition, the filled holes (431) do not interfere with the layered detection result, so that the accuracy of the layered detection result of the semiconductor device (400) is improved.

Description

Semiconductor device with high-stability bonding layer and preparation method thereof Technical Field
The present disclosure relates to the field of semiconductor chip packaging technologies, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
Because Epoxy Molding Compound (EMC) has low material cost and is suitable for large-scale automated production, the semiconductor chip is usually packaged by EMC. The structure obtained by adopting EMC packaging is called an EMC packaging structure or a plastic packaging structure.
At present, the semiconductor chip plastic package structure adopted in the industry has the following defects:
firstly, the method comprises the following steps: after the semiconductor chip package structure is exposed in a humid environment for a long time, when a device of the semiconductor chip package structure is attached to a printed circuit board through reflow soldering, adhesive materials of the semiconductor chip and the circuit substrate may fail, resulting in delamination of the semiconductor chip and the circuit substrate.
Secondly, the method comprises the following steps: the detection accuracy of whether layering exists inside the semiconductor chip plastic packaging structure is low.
Disclosure of Invention
In view of the above, embodiments of the present application provide a semiconductor device and a method for manufacturing the same to overcome the above-mentioned drawbacks.
In order to solve the technical problem, the following technical scheme is adopted in the application:
a first aspect of the present application provides a semiconductor device comprising:
the semiconductor chip comprises a semiconductor chip, a substrate and an adhesive layer which is positioned between the semiconductor chip and the substrate and is used for adhering the semiconductor chip and the substrate; the bonding layer comprises a sintered metal; the sintered metal comprises a plurality of hollow holes, and at least part of the hollow holes are filled with specific materials; wherein the specific material has certain fluidity when being higher than the preset temperature, and can be solidified and molded after being heated and melted.
According to the semiconductor device, at least part of the hollow cavities in the sintered metal are filled with the specific material, so that the probability that moisture in the external environment is gathered in the semiconductor device is reduced, and the possibility of delamination of a chip and a substrate caused when the semiconductor device is attached to a printed circuit board through reflow (reflow) is reduced; in addition, the ultrasonic scanning microscope image of the cavity filled with the specific material is obviously different from the image of the semiconductor internal lamination, so that the detection accuracy of the internal lamination of the semiconductor device is high.
With reference to the first aspect of the present application, in a first possible implementation manner, the semiconductor device further includes: and the specific material is the same as the plastic package material corresponding to the plastic package body.
In this embodiment, the plastic package can protect the semiconductor chip and the adhesive layer inside thereof, and thus, the reliability of the semiconductor device can be improved. In addition, the embodiment can simplify the manufacturing process of the semiconductor device and reduce the manufacturing cost.
With reference to the first aspect of the present application and the first possible implementation manner thereof, in a second possible implementation manner, more than 85% of the voids inside the sintered metal are filled with the specific material.
In a second possible embodiment combined with the first aspect of the present application, in a third possible embodiment, more than 90% of the voids inside the sintered metal are filled with the specific material.
When a higher proportion of the voids are filled with a particular material, the voids are less likely to contain moisture and the internal delamination conditions are more accurately detected by ultrasonic scanning microscopy.
With reference to the first aspect of the present application and the foregoing various possible embodiments thereof, in a fourth possible embodiment, a first metal layer is disposed on a surface of the semiconductor chip bonded to the adhesive layer, and a first metal alloy layer is formed between the first metal layer and the adhesive layer due to a metal bonding force.
The embodiment can improve the connection performance between the semiconductor chip and the bonding layer and reduce the possibility of layering between the semiconductor chip and the bonding layer.
With reference to the first aspect of the present application and the above-described various possible embodiments thereof, in a fifth possible embodiment, a second metal layer is disposed on a surface of the substrate bonded to the bonding layer, and a second metal alloy layer is formed between the second metal layer and the bonding layer due to a metal bonding force.
This embodiment can improve the connection performance between the substrate and the adhesive layer, and reduce the possibility of delamination between the substrate and the adhesive layer.
In a sixth possible embodiment, in combination with the first aspect of the present application, the specific material is introduced into the void from the outside of the bonding layer after the bonding layer is formed by a sintering and curing process, so as to fill the void.
With reference to the first aspect of the present application and the various possible embodiments thereof described above, in a seventh possible embodiment, the sintered metal is sintered silver. The embodiment can improve the heat conduction and the electric conduction of the bonding layer.
In combination with the first aspect of the present application and the above-described various possible embodiments thereof, in an eighth possible embodiment, the metal powder includes: at least one of nano-sized and micro-sized metal particles.
In a ninth possible embodiment, in combination with the first aspect of the present application and the various possible embodiments thereof described above, the sintered metal is made from a metal powder through a sintering process.
A second aspect of the present application provides a method of manufacturing a semiconductor device, the method including:
forming a bonding layer between the semiconductor chip and the substrate by a sintering and curing process, wherein the bonding layer is used for bonding the semiconductor chip and the substrate, the bonding layer is composed of sintered metal, and the sintered metal comprises a plurality of cavities inside; filling at least part of the hollow with a specific material; the specific material has certain fluidity when being higher than the preset temperature, and can be solidified and molded after being heated and melted.
Because at least part of the hollow cavities in the sintered metal are filled with specific materials, the probability that moisture in the external environment is gathered in the semiconductor device is reduced, and the possibility of delamination of the chip and the substrate caused when the semiconductor device is attached to the printed circuit board through reflow (reflow) is reduced; in addition, the ultrasonic scanning microscope image of the cavity filled with the specific material is obviously different from the image of the semiconductor internal lamination, so that the detection accuracy of the internal lamination of the semiconductor device is high.
In combination with the second aspect of the present application, in a first possible embodiment, the preparation method further includes: and forming a plastic package body wrapping the semiconductor chip and the bonding layer, wherein the specific material is the same as the plastic package material corresponding to the plastic package body.
In this possible embodiment, the plastic package can protect the semiconductor chip and the adhesive layer inside thereof, and thus, the reliability of the semiconductor device can be improved.
With reference to the first possible implementation manner of the second aspect of the present application, in a second possible implementation manner, the filling at least a portion of the void with a specific material specifically includes: and when the plastic package body is formed, flowing plastic package material flows into at least part of the hollow hole, so that the plastic package material is filled in at least part of the hollow hole.
The possible implementation mode can simplify the packaging process of the semiconductor device and reduce the packaging cost.
With reference to the second aspect of the present application and the above-mentioned various possible embodiments thereof, in a third possible embodiment, after the forming the plastic package body wrapping the semiconductor chip and the adhesive layer, the method further includes: and carrying out shaping and curing on the plastic package body.
In a fourth possible embodiment, in combination with the second aspect of the present application, the filling at least part of the hollow space with a specific material specifically includes: heating the specific material to a temperature higher than the preset temperature to enable the specific material to flow; the flowable particulate material is injected into at least some of the voids within the bonding layer.
This possible embodiment enables an improved filling of the cavity.
With reference to the fourth possible implementation manner of the second aspect of the present application, in a fifth possible implementation manner, after the injecting the fluid into at least some of the voids in the adhesive layer by using capillary force, the method further includes:
and placing the structure filled with the specific material under a certain temperature condition, and performing post-curing on the fluid injected into the hollow hole. This possible embodiment can improve the reliability of the semiconductor device.
In a sixth possible embodiment, in combination with the second aspect of the present application and the above-mentioned various possible embodiments thereof, more than 85% of the voids inside the sintered metal are filled with the specific material.
This possible embodiment can reduce the possibility of delamination of the chip and the substrate caused when the semiconductor device is mounted on the printed wiring board through reflow (reflow). And improving the detection accuracy of the internal delamination of the semiconductor device.
In a seventh possible implementation manner, in combination with the second aspect of the present application and the above-mentioned various possible implementation manners thereof, a first metal layer is disposed on a surface of the semiconductor chip adhered to the adhesive layer, and a first metal alloy layer is formed between the first metal layer and the adhesive layer due to a metal bonding force.
The possible implementation mode can improve the connection performance between the semiconductor chip and the bonding layer and reduce the possibility of layering between the semiconductor chip and the bonding layer.
In an eighth possible implementation manner, in combination with the second aspect of the present application and the above-mentioned various possible implementation manners thereof, a second metal layer is disposed on a surface of the substrate bonded to the bonding layer, and a second metal alloy layer is formed between the second metal layer and the bonding layer due to a metal bonding force.
This possible embodiment can improve the connection performance between the substrate and the adhesive layer, and reduce the possibility of delamination between the two.
In a ninth possible embodiment, in combination with the second aspect of the present application and its various possible embodiments described above, the sintered metal is sintered silver.
Compared with the prior art, the method has the following beneficial effects:
based on the above technical solution, in the semiconductor device provided in the embodiment of the present application, the bonding layer for bonding the semiconductor chip and the circuit substrate is made of a sintered metal made by a metal powder sintering process with high electrical and thermal conductivity. In the embodiment of the present application, at least a part of the hollow space existing inside the sintered metal is filled with a specific material. So, the cavity is filled the back by specific material, is favorable to reducing the holding of moisture, avoids the relatively large-scale moisture gathering in semiconductor chip plastic envelope structure in external environment inside, and is further, avoids leading to the layering of chip and base plate because the gathering of external moisture in inside. Therefore, when the semiconductor device is exposed to a humid environment, the probability that moisture in the external environment collects inside the semiconductor molding structure is greatly reduced, thereby reducing the possibility of delamination of the chip and the substrate caused when the semiconductor device is mounted on the printed wiring board by reflow (reflow).
In addition, the means for detecting whether or not there is delamination inside the semiconductor device is Scanning Acoustic microscopy (SAT), but the voids of the sintered metal and the layered ultrasonic Scanning microscope images are difficult to distinguish, and the ultrasonic Scanning microscope images of the voids of the sintered metal after filling are clearly distinguished from the ultrasonic Scanning microscope images of the chip and circuit substrate layered inside the semiconductor device, so that the filled voids can be easily excluded by the ultrasonic Scanning microscope images, thereby reducing the interference with the delamination detection.
Drawings
FIG. 1 is a schematic diagram of a plastic package structure of a semiconductor chip commonly used in the art;
FIG. 2 is a schematic diagram of a prior art structure for connecting a semiconductor chip and a circuit substrate using sintered silver;
FIG. 3 is a schematic diagram of the internal delamination of the plastic encapsulated structure of the semiconductor chip;
fig. 4' is a perspective view of a semiconductor device provided in an embodiment of the present application;
fig. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present application;
fig. 5 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 6A to 6C are schematic cross-sectional views illustrating a series of processes of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 7 is a schematic flow chart illustrating another method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Reference numerals:
11. 21, 41: a semiconductor chip having a plurality of semiconductor chips,
12. 22, 42: a substrate, a first electrode and a second electrode,
13: the conductive adhesive is coated with a conductive adhesive,
23: the silver paste is prepared by mixing silver paste,
231. 611: the nano-scale or micro-scale silver powder particles,
232. 612: an auxiliary solvent is added to the reaction mixture,
24: the silver block is sintered, and the silver block,
400: a plastic package structure for a semiconductor chip,
43: a bonding layer (such as a sintered silver structure),
44: a plastic-sealed body is formed by the plastic-sealed body,
45: the specific material(s) is (are),
431: a hollow space is formed in the upper surface of the body,
411: a first metal layer, a second metal layer,
421: a second metal layer formed on the first metal layer,
46: a first metal alloy layer, a second metal alloy layer,
47: a second metal alloy layer,
48: a metal bonding wire is arranged on the substrate,
61: sintering the original slurry of silver.
Detailed Description
It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B can be single or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
The semiconductor chip package structure is generally shown in fig. 1, and includes a semiconductor chip 11 and a substrate 12, where the semiconductor chip 11 is generally bonded to the substrate 12 by a conductive adhesive 13. By way of example, the substrate 12 may be a printed wiring board or a ceramic-type wiring board. In an alternative case, when the substrate is a printed circuit board or a ceramic-type circuit board, the circuit board may be used to lay down a printed circuit to achieve the transmission of electrical signals. In addition, since the semiconductor chip 11 generates heat during operation, and the main heat dissipation path of the semiconductor chip is heat conduction, the circuit board can also perform a heat dissipation function to transfer the heat generated by the semiconductor chip 11 to the outside of the plastic package structure, and specifically, as shown in fig. 1, the heat generated by the semiconductor chip 11 can be conducted and dissipated via the conductive adhesive 13 and the substrate 12 below the semiconductor chip 11.
Because the epoxy resin Silver adhesive (Silver epoxy) has the advantages of simple operation, stable performance and good conductive performance when bonding the chip, the epoxy resin Silver adhesive is generally used as a commonly used material in semiconductor chip plastic package. . However, the thermal conductivity of the epoxy resin silver paste is lower, generally less than 10 w/m · k, and in the application of high power chips, the epoxy resin silver paste cannot rapidly and effectively dissipate heat generated by the semiconductor chip 11 during operation, which may cause the temperature of the PN junction (hereinafter referred to as junction temperature) of the semiconductor chip to rise, thereby shortening the service life of the chip. In addition, the surface of the semiconductor chip 11 and the surface of the substrate 12 which are in contact with the conductive paste 13 are generally metal layer surfaces, and the conductive paste 13 is generally an organic resin system, and therefore, the conductive paste 13 and the material to which it is in contact are not one system, resulting in poor adhesion. When the stress at the interface is too large, for example, the stress generated when the temperature of the chip application environment changes greatly is generated when the material expands with heat and contracts with cold, the bonding between the chip and the substrate is easy to fall off, and delamination is generated.
In order to solve the defects of the conductive paste, another new adhesive material, which is a sintered metal such as sintered silver, has recently appeared and been applied to EMC packages. The sintered metal is formed by sintering metal particles at high temperature (for sintered silver, the sintering temperature is 170-300 ℃). As shown in fig. 2, a specific bonding process is illustrated by sintering silver as an example: a silver paste 23 is provided between the semiconductor chip 21 and the substrate 22. The silver paste 23 is composed of nano-sized or micro-sized silver powder particles 231 and an auxiliary solvent 232. The auxiliary solvent 232 may be, for example: one of butyl anhydride acetate, diethylene glycol butyl ether acetate, diethylene glycol ethyl ether acetate, or isophorone, it should be understood that the auxiliary solvent 232 is not limited to the above-listed solvents. The auxiliary solvent 232 has a certain volatility, which can be volatilized at a certain temperature, and the auxiliary solvent 232 has a certain lubricating effect in the silver paste 23, so that the silver powder particles 231 can flow.
After the silver paste 23 is baked at a high temperature, the auxiliary solvent 232 is completely volatilized, nano-scale or micron-scale metal powder particles are crystallized and agglomerated into a sintered silver block 24, and a plurality of cavities 25 are remained in the sintered silver block 24.
The sintered metal has the functions of bonding, electric conduction and heat conduction. Compared with the conductive adhesive, the thermal conductivity of the sintered metal is higher, for example, the thermal conductivity of the sintered silver reaches more than 100w/m.k, and the defect of low thermal conductivity of the epoxy silver adhesive is completely overcome. In addition, the sintered metal forms metal bonding gold (metal bond alloy) with the metal of the contact interface during the sintering process, so that the sintered metal forms good adhesion with the chip surface and the substrate surface which are in contact with the sintered metal, and the defects that the adhesion is poor and the semiconductor chip and the substrate are easy to delaminate caused by the fact that the interface material is not a system are solved.
However, the semiconductor chip plastic package structure in which the semiconductor chip and the substrate are bonded by the sintered metal has the drawbacks described in the background art, which are as follows:
firstly, the method comprises the following steps: when the semiconductor chip package structure is exposed to a humid environment for a long time, delamination between the chip and the substrate may be caused when a device of the semiconductor chip package structure is attached to the printed circuit board by reflow soldering.
Secondly, the method comprises the following steps: the detection accuracy of whether layering exists inside the semiconductor chip plastic packaging structure is low.
During the high-temperature sintering and forming process of the sintered metal, a large number of voids (void) are generated, that is, the interior of the sintered metal is filled with a large number of voids. When the semiconductor chip and the substrate are bonded using a sintered metal, the void exists in the semiconductor chip package structure. Therefore, when the semiconductor chip plastic package structure is exposed in humid air for a long time, the humid air can be gathered in the sintered metal cavity, and the gas environment in the sintered metal cavity can be consistent with the external gas environment of the plastic package structure. Referring to fig. 3, if a device baking and dehumidifying step is not added before the mounting of the device with the plastic package structure, when the device with the plastic package structure is mounted on the printed circuit board by reflow soldering, pressure caused by rapid thermal expansion of moisture in the cavity is easily generated inside the device with the plastic package structure, so that the chip and the substrate are delaminated, and the device with the plastic package structure is seriously even cracked.
At present, an effective means for verifying the internal layering of the semiconductor chip plastic package structure is an ultrasonic scanning microscope image, and a cavity inside a sintered metal and the ultrasonic scanning microscope image of the internal layering of the plastic package structure are difficult to distinguish, so that the cavity existing inside the sintered metal interferes with the layered detection, and the detection accuracy of whether the layering exists inside the semiconductor chip plastic package structure is low.
In the embodiments of the present application, the internal delamination of the molding structure mainly refers to the delamination between the semiconductor chip and the connection structure and the delamination between the connection structure and the substrate.
In order to solve the above-mentioned defects of the semiconductor chip plastic package structure, the present application provides a semiconductor device. See in particular the examples below.
It should be noted that, in an alternative case, the semiconductor device in the embodiment of the present application may have a plastic package structure.
Fig. 4' is a perspective view of a semiconductor device provided in an embodiment of the present application; fig. 4 is a schematic cross-sectional view of a semiconductor device having a plastic package structure according to an embodiment of the present disclosure. As shown in fig. 4' and 4, the semiconductor device 400 includes:
a semiconductor chip 41, a substrate 42, and an adhesive layer 43 between the semiconductor chip 41 and the substrate 42 for bonding the semiconductor chip 41 and the substrate 42;
the semiconductor device 400 further includes: a plastic package body 44 wrapped around the semiconductor chip 41 and the adhesive layer 43;
wherein the bonding layer 43 is composed of sintered silver; the sintered silver comprises a plurality of hollow holes 431, at least part of the hollow holes 431 are filled with a specific material 45, and the specific material has certain fluidity when being higher than a preset temperature and can be solidified and molded after being heated and melted.
In the present embodiment, the term "solidification" means that a chemical crosslinking reaction occurs in a specific material after the material is heated and melted, and a chemical crosslinking bond is formed. After reheating, the solidified material does not melt and flow.
In the present embodiment, after the bonding layer 43 is formed by the sintering and curing process, the specific material 45 may be injected into the cavity from the outside of the bonding layer 43, thereby achieving the effect of filling the cavity.
Further, the amount of the voids 431 inside the sintered silver is greatly related to the internal accumulation of external moisture of the entire semiconductor device. The fewer the voids, the less ambient moisture collects inside, the more the voids, and the more ambient moisture collects inside. Therefore, in order to prevent the whole semiconductor device from delaminating the chip and the substrate due to external moisture accumulated inside, as an optional embodiment of the present application, the specific material may have better fluidity when being higher than the preset temperature, so that the specific material can flow into as many cavities as possible to fill in as many cavities as possible, thereby reducing the cavities inside the whole semiconductor device, finally making the moisture accumulated inside the semiconductor device zero or less, and removing the risk of delaminating the chip and the substrate of the semiconductor device. In the embodiment of the present application, the proportion of the filled cavities can be controlled by controlling the viscosity of the specific material, in an optional case, the lower the viscosity of the material, the better the fluidity of the material, the more the flowable material can flow into more cavities, so that more cavities are filled, and for example, in order to fill as many cavities as possible, the material with the lower viscosity can be selected as the specific material for filling the cavities.
As another alternative embodiment of the present application, in order to simplify the packaging process and reduce the packaging cost, the specific material described in the embodiment of the present application may be a molding compound for forming the molding compound 44. Therefore, the filling of the cavity can be carried out simultaneously with the formation of the plastic package body, so that the step of filling the cavity can be omitted, and the aims of simplifying the packaging process and reducing the packaging cost are fulfilled.
In addition, because the main components of the plastic package material are resin, filler and curing agent, in addition, other components of the plastic package material can also comprise catalyst, release agent and the like. The molding compound can flow and deform only when the processing temperature is higher than the melting temperature of the resin, and therefore, in this embodiment, the preset temperature may be the melting temperature of the resin constituting the molding compound, and in order to make the molding compound have better fluidity, the preset temperature may be a temperature higher than the melting temperature by a certain range, which is not limited in this embodiment.
After the plastic package material is heated and melted, the internal resin and the curing agent are subjected to chemical reaction, so that the plastic package material can be cured and molded.
In another alternative case, the specific material may also be other materials, such as silica gel type material.
In addition, as another alternative embodiment of the present application, in order to ensure that the semiconductor device provided in the embodiments of the present application can overcome the aforementioned defects, the voids filled with the specific material account for more than 85% of all the voids, and even more than 90%. In other words, more than 85% or even more than 90% of the voids are filled with the specific material. Illustratively, the proportion of the cavity filled with the specific material can be controlled by controlling the viscosity of the molding compound during the molding process, and illustratively, the lower the viscosity of the molding compound, the more the molding compound can flow into the cavity, and thus the higher the proportion of the cavity filled with the specific material will be.
Further, in the embodiment of the present application, in the semiconductor chip 41, it is optional that the back surface of the semiconductor chip 41 is bonded to the substrate 42. The back surface of the semiconductor chip 41 is a surface opposite to a surface on which a chip active region (active region) is located. When a metal layer is provided on the back surface of the semiconductor chip 41, that is, on the surface of the semiconductor chip bonded to the adhesive layer 43, a metal bonding bond is formed between the silver particles in the silver paste and the metal layer on the back surface of the semiconductor chip 41 during the sintering of the silver paste in which silver is sintered, thereby forming a metal alloy layer. As such, as an alternative embodiment of the present application, the first metal layer 411 is disposed on the surface of the semiconductor chip adhered to the adhesive layer 43, and the first metal alloy layer 46 is formed between the first metal layer 411 and the adhesive layer 43 due to a metal bonding force.
In addition, a metal layer is generally provided on the surface of the substrate 42 bonded to the adhesive layer 43, and during the sintering of the silver paste in which silver is sintered, a metal bond is formed on the surface of the metal layer in contact with silver in the silver paste, thereby forming a metal alloy layer between the substrate 42 and the adhesive layer 43. As such, as an alternative embodiment of the present application, the second metal layer 421 is provided on the surface of the substrate to be bonded in contact with the adhesive layer 43, and the second metal alloy layer 47 is formed between the second metal layer 421 and the adhesive layer 43 due to a metal bonding force.
In an optional case, in this embodiment of the application, the metal material constituting the first metal layer 411 may be gold, because gold is not easily oxidized, is not easily reacted with other materials at normal temperature, and has a good adhesion property, and optionally, the first metal layer may also be other metals such as silver, tin, or copper. Alternatively, the metal material constituting the second metal layer 431 may be gold, silver, tin, or copper. In addition, the metal material composing the first metal layer 411 or the second metal layer 431 may also be other metals that can form a metal alloy layer with the adhesive layer, and the application does not limit the types of the metals of the first metal layer and the second metal layer.
In addition, as another alternative embodiment of the present application, the plastic package body 44 may further include a periphery of the substrate 42 in addition to the semiconductor chip 41 and the adhesive layer 43, so as to protect the substrate 42 and prevent the substrate 42 from being damaged by an external force.
The foregoing is a specific implementation of the semiconductor device provided in the embodiments of the present application. In this embodiment, the adhesive layer 43 for connecting the semiconductor chip 41 and the substrate 42 is formed using sintered silver, which has good electrical and thermal conductivity of 100w/m.k or more. Therefore, the heat generated by the semiconductor chip 41 during operation can be dissipated to the outside of the semiconductor device through the adhesive layer 43 and the substrate 42, thereby reducing the overall thermal resistance of the semiconductor chip 41 from the front PN junction to the chip case, and contributing to the improvement of the service life of the semiconductor chip 41. In addition, the input power of the semiconductor chip is increased, the power density of the semiconductor chip is improved, and the use power of the semiconductor chip is improved.
In the present embodiment, at least a part of the hollow 431 existing inside the sintered metal is filled with the specific material. Therefore, after the cavity 431 is filled with a specific material, moisture can be accommodated in the cavity, moisture in the external environment can be prevented from gathering inside the plastic package structure of the semiconductor chip, and further, delamination between the chip and the substrate caused by gathering of external moisture inside the semiconductor chip can be prevented. Therefore, when the semiconductor package structure is exposed to a humid environment, the probability that moisture in the external environment collects inside the semiconductor package structure is greatly reduced, thereby reducing the possibility of delamination of the semiconductor chip 41 and the substrate 42 caused when the semiconductor device is reflow-mounted on the printed wiring board.
In addition, when an ultrasonic scanning microscope is used for detecting whether layering exists in the semiconductor chip plastic packaging structure, the filled cavity can be easily eliminated through the ultrasonic scanning microscope image because the filled cavity is obviously different from the internally layered ultrasonic scanning microscope image of the semiconductor chip plastic packaging structure, so that the interference of layering detection is reduced, and therefore, the internal layering detection accuracy of the semiconductor chip plastic packaging structure provided by the embodiment of the application is high.
In addition, in the application example, since the back surface of the semiconductor chip 41 is generally the surface of the metal layer, which belongs to the metal system, and the adhesive layer 43 is composed of sintered silver, which also belongs to the metal system, during the formation of the adhesive layer 43, the sintered silver forms a metal bonding bond with the metal on the surface of the semiconductor chip 41, which is in contact with the sintered silver, so that a firm connection between the semiconductor chip 41 and the adhesive layer 43 can be formed, which can reduce the possibility of delamination between the semiconductor chip 41 and the adhesive layer 43.
Based on the same principle as described above, a firm connection is formed between the substrate 42 and the adhesive layer 43, and the formation of the firm connection can also reduce the possibility of delamination between the substrate 42 and the adhesive layer 43.
In the above embodiment, the specific structure of the adhesive layer 43 is described by taking sintered silver as an example. In fact, as a development of the embodiment of the present application, the adhesive layer 43 is not limited to a sintered silver material, and may be made of any kind of sintered metal. As such, semiconductor devices in which the adhesive layer 43 is made of sintered metal produced by a metal powder sintering process are within the scope of the present application. As an example, when the bonding layer is composed of a sintered metal made by a metal powder sintering process, the metal powder may include at least one of nano-sized and micro-sized metal particles.
The foregoing is a specific implementation of the semiconductor device provided in the embodiments of the present application. Based on the specific implementation manner of the semiconductor device, the embodiment of the application also provides a specific implementation manner of a preparation method of the semiconductor device. See in particular the examples below.
It should be noted that, in the embodiments of the present application, a specific implementation manner of the method for manufacturing a semiconductor device provided in the embodiments of the present application is described with an example of sintering silver as a sintering metal. In addition, when other kinds of sintered metals than sintered silver are used in the examples of the present application, the specific implementation is the same as that of sintered silver, except that the solidification molding conditions of the sintered metals are different. Accordingly, those skilled in the art will readily recognize implementations using other types of sintered metals based on the specific implementation of sintered silver, and the specific implementation of other types of sintered metals will not be described in detail herein.
Referring to fig. 5 to fig. 6C, a method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes the following steps:
s501: the semiconductor chip 41 is bonded to the substrate 42 using a green paste 61 of sintered silver.
As an example, as shown in fig. 6A. The semiconductor chip 41 may be bonded to the substrate 42 by sintering the silver precursor paste 61 using a die bonder.
As a specific example of the present application, S501 may specifically be: the original slurry of sintered silver is coated on the substrate 42, and then the semiconductor chip 41 adsorbed thereto is placed on the original slurry of sintered silver 61 coated above the substrate 42 using a die bonder, thus completing the process of bonding the semiconductor chip 41 on the substrate 42.
It should be noted that in the present embodiment, the original slurry 61 of sintered silver is composed of nano-sized or micro-sized silver powder particles 611 and an auxiliary assistant 612. As an example, the auxiliary agent 612 may be: butyl anhydride acetate, diethylene glycol butyl ether acetate, diethylene glycol ethyl ether acetate or isophorone, etc.
S502: the original paste 61 of sintered silver is cured to form the adhesive layer 43 adhering the semiconductor chip 41 and the substrate 42, the adhesive layer 43 being composed of cured and molded sintered silver, the sintered silver including a plurality of voids 431 in its inside.
The step may specifically be: the raw slurry 61 of sintered silver (also referred to as sintered silver paste) is subjected to solidification sintering in an oven or on a heating stage according to the oven temperature profile of the sintered silver and the corresponding baking gas. During the curing and sintering process, the auxiliary solvent 612 in the original slurry 61 of sintered silver is emitted, and the nano-sized or micro-sized silver powder particles 611 are crystallized and agglomerated into sintered silver masses, thereby forming the adhesive layer 43 connecting the semiconductor chip 41 and the substrate 42. As such, the adhesive layer 43 is composed of solidified sintered silver, and the sintered silver includes a plurality of voids 431 therein.
As an alternative embodiment of the present application, when the first metal layer 411 is disposed on the surface of the semiconductor chip bonded to the bonding layer 43, the method for manufacturing the semiconductor device according to the embodiment of the present application may further include the following steps:
the first metal alloy layer 46 is sintered between the first metal layer 411 and the adhesive layer 43 while the original paste 61 of sintered silver is cured.
It should be noted that, while the original paste 61 of sintered silver is solidified, the metal atoms in the first metal layer 411 and the silver in the sintered silver are bonded to form a metal bond under the action of high-temperature sintering, so that the first metal alloy layer 46 is sintered and formed between the first metal layer 411 and the adhesive layer 43.
As another alternative embodiment of the present application, when the second metal layer 421 is disposed on the surface of the substrate 42 in contact with the adhesive layer 43, the method for manufacturing the semiconductor device according to the embodiment of the present application may further include:
the second metal alloy layer 47 is sintered between the second metal layer 421 and the adhesive layer 43 while the original paste 61 of sintered silver is cured.
It should be noted that, while the original paste 61 of sintered silver is solidified, the metal atoms in the second metal layer 421 and the silver in the sintered silver are bonded to form a metal bond under the action of high-temperature sintering, so that the first metal alloy layer 47 is sintered between the second metal layer 421 and the bonding layer 43.
The cross-sectional structure of the step is shown in fig. 6B.
S503: the voids 431 are filled at least partially with a particular material.
It should be noted that, in the embodiments of the present application, the specific material has a certain fluidity above a preset temperature, and can be solidified and molded after being heated and melted.
In order to enable a specific material to fill as many cavities as possible and achieve a better filling effect, the embodiment of the present application selects a material with better fluidity as the specific material for filling the cavities. For example, the specific material may be a molding compound with better fluidity. As a specific example, the particular material selected can fill at least a portion of the voids. In addition, in order to ensure that the finally formed semiconductor plastic package structure can overcome the defects of the semiconductor plastic package structure in the prior art, as an optional embodiment of the present application, the selected specific material can fill more than 85% or even more than 90% of the cavities.
As an example, step S503 may specifically include the following steps:
s5031: the specific material is heated to above a preset temperature so that the specific material becomes a fluid capable of flowing.
S5032: a flowable fluid is injected into at least a portion of the voids within the bonding layer.
It will be appreciated that the injection of a fluid capable of flowing into at least some of the voids in the adhesive layer is based on the principle of capillary force, which refers to the phenomenon of an imbibing liquid rising in the tubule and the phenomenon of a non-imbibing liquid falling in the tubule. The conduit in the plant stem is a superfine capillary tube in the plant body, the capillary tube can absorb water in soil, and the common capillary phenomena of brick water absorption, towel sweat absorption and pen ink absorption are common. In these bodies, many fine channels act as capillaries, and the surface tension, cohesion and adhesion of the liquid act together to allow moisture to rise to a certain height in the capillaries having a small diameter, which is called a capillary phenomenon.
The capillary force is a force that can cause the fluid to automatically rise in the capillary tube.
In the embodiment of the present application, the voids existing in the adhesive layer are all openings with a very small caliber, so that the voids have a structure similar to a capillary tube, and thus, the adhesive layer structure is placed inside a fluid capable of flowing, and the fluid can be injected into at least part of the voids in the adhesive layer under the capillary force.
S5033: and placing the structure filled with the specific material under a certain temperature condition, and performing post-curing on the fluid injected into the hollow hole.
It should be noted that the temperature and time of post-curing can be determined based on the properties of the particular material itself. As an example, the temperature at the time of post-curing may be related to the melting temperature of the resin inside the specific material and the curing temperature of the curing agent.
The cross-sectional structure after the step is completed is shown in fig. 6C.
S504: the semiconductor chip 41 and the substrate 42 connected together are mold-packaged with a molding compound to form a molding compound 44 which wraps the periphery of the semiconductor chip 41 and the adhesive layer 43.
The step may specifically be: according to the performance of the molding compound, a suitable molding temperature is selected, and the semiconductor chip 41 and the substrate 42 which are connected together are molded and packaged, so that a molding compound body 44 which wraps the periphery of the semiconductor chip 41 and the bonding layer 43 is formed. The resulting structure is shown in fig. 4.
In addition, as another alternative embodiment of the present application, a plastic package body wrapping the substrate 42 may be further formed on the periphery of the substrate 42, so that the substrate 42 is protected and the substrate 42 is prevented from being damaged by an external force.
It should be noted that in the embodiment of the present application, before performing mold packaging, other chip packaging steps from die bonding to mold packaging may also be performed, such as making metal bonding wires 48 connecting the front surface of the semiconductor chip 41 and the substrate 42, and so on. It should be understood that the metal bonding wires 48 are metal leads for electrically connecting pads on the front surface of the semiconductor chip 41 and pads on the substrate 42.
S505: and (4) carrying out setting and curing on the plastic package body 44.
And placing the semiconductor chip plastic package structure after molding under corresponding temperature and atmosphere conditions according to the curing and forming conditions of the plastic package material, and shaping and curing the plastic package body 44 to finally obtain the semiconductor chip plastic package structure after curing and forming.
The foregoing is a specific implementation manner of the method for manufacturing a semiconductor device according to the embodiments of the present application.
In this embodiment, the filling of the voids inside the sintered silver is achieved by a special filling process.
Because the specific material filled in the hollow hole can be plastic packaging material, in order to simplify the packaging process and reduce the packaging cost, the process of filling the hollow hole can be simultaneously completed in the process of molding and packaging. See in particular the examples below.
Referring to fig. 7, another method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes the following steps:
s701 to S702 are the same as S501 to S502 in the above embodiment, and for the sake of brevity, will not be described in detail here.
S703: and performing molding packaging on the semiconductor chip 41 and the substrate 42 which are bonded together by using a molding compound to form a molding compound body 44 which wraps the periphery of the semiconductor chip 41 and the bonding layer 43, wherein the molding compound flows into at least part of the hollow 431 during the molding packaging so that at least part of the hollow 431 is filled with the molding compound.
When the semiconductor chip 41 and the substrate 42 connected together are molded and packaged by using the molding compound, the molding compound in a molten state can flow into at least part of the hollow space under the action of molding pressure and capillary force, so that the molding compound is filled in at least part of the hollow space.
In the embodiment of the present application, the molding compound in a molten state flows into the cavity while molding the package, thereby filling the cavity. In the molding and packaging process, the molding compound flows into the hollow space under the combined action of molding pressure and capillary force. Compared with the situation with only capillary force, the filling of the cavity is realized by utilizing the molding and packaging process, and a better filling effect can be achieved.
S704 is the same as S505 described above and, for brevity, will not be described in detail herein.
The above is a specific implementation manner of another method for manufacturing a semiconductor device provided in the embodiments of the present application. In the specific implementation mode, the filling of the cavities is completed simultaneously in the molding and packaging process, so that a cavity filling process is reduced, the packaging process is simplified, and the packaging cost is reduced.
The foregoing is a detailed implementation of the semiconductor device and the method for manufacturing the semiconductor device provided in the embodiments of the present application. It should be understood that the above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims (13)

  1. A semiconductor device, comprising:
    the semiconductor chip comprises a semiconductor chip, a substrate and an adhesive layer which is positioned between the semiconductor chip and the substrate and is used for adhering the semiconductor chip and the substrate;
    the bonding layer comprises a sintered metal; the interior of the sintered metal comprises a plurality of hollow holes, and at least part of the hollow holes are filled with specific materials; wherein the specific material has certain fluidity when being higher than the preset temperature, and can be solidified and molded after being heated and melted.
  2. The semiconductor device according to claim 1, further comprising: and the plastic package body wraps the semiconductor chip and the periphery of the bonding layer, and the specific material is the same as the plastic package material corresponding to the plastic package body.
  3. The semiconductor device according to claim 1 or 2, wherein 85% or more of voids inside the sintered metal are filled with the specific material.
  4. A semiconductor device according to any one of claims 1 to 3, wherein a first metal layer is provided on a surface of the semiconductor chip to which the adhesive layer is adhered, and a first metal alloy layer is formed between the first metal layer and the adhesive layer due to a metal bonding force.
  5. The semiconductor device according to any one of claims 1 to 4, wherein a second metal layer is provided on a surface of the substrate to which the adhesive layer is adhered, and wherein a second metal alloy layer is formed between the second metal layer and the adhesive layer due to a metal bonding force.
  6. A method of manufacturing a semiconductor device, the method comprising:
    forming a bonding layer between a semiconductor chip and a substrate through a sintering and curing process, wherein the bonding layer is used for bonding the semiconductor chip and the substrate, the bonding layer is made of sintered metal, and the sintered metal comprises a plurality of cavities inside;
    filling at least part of the hollow hole with a specific material; the specific material has certain fluidity when being higher than the preset temperature, and can be solidified and molded after being heated and melted.
  7. The method of manufacturing according to claim 6, further comprising:
    and forming a plastic package body wrapping the semiconductor chip and the bonding layer, wherein the specific material is the same as the plastic package material corresponding to the plastic package body.
  8. The production method according to claim 6 or 7, wherein 85% or more of voids inside the sintered metal are filled with the specific material.
  9. The method according to claim 7 or 8, wherein the filling at least a portion of the cavities with a specific material comprises:
    and when the plastic package body is formed, flowing plastic package material flows into at least part of the hollow hole, so that the plastic package material is filled in at least part of the hollow hole.
  10. The method for manufacturing a semiconductor device according to any one of claims 6 to 9, wherein after the forming of the molding body encapsulating the semiconductor chip and the adhesive layer, the method further comprises: and carrying out shaping and curing on the plastic package body.
  11. The method according to any one of claims 6 to 10, wherein the filling at least a portion of the voids with a specific material comprises:
    heating the specific material to above the preset temperature to enable the specific material to flow;
    injecting the particular material capable of flowing into the at least partial void within the bonding layer.
  12. The production method according to any one of claims 6 to 11, wherein a first metal layer is provided on a surface of the semiconductor chip bonded to the adhesive layer, and a first metal alloy layer is formed between the first metal layer and the adhesive layer due to a metal bonding force.
  13. The production method according to any one of claims 6 to 12, wherein a second metal layer is provided on a surface of the substrate to which the adhesive layer is adhered, and a second metal alloy layer is formed between the second metal layer and the adhesive layer due to a metal bonding force.
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