CN111213241A - 半导体器件、半导体设备及其制造方法 - Google Patents

半导体器件、半导体设备及其制造方法 Download PDF

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CN111213241A
CN111213241A CN201980005111.2A CN201980005111A CN111213241A CN 111213241 A CN111213241 A CN 111213241A CN 201980005111 A CN201980005111 A CN 201980005111A CN 111213241 A CN111213241 A CN 111213241A
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epitaxial layer
semiconductor device
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CN111213241B (zh
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魏进
陈敬
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Abstract

一种半导体设备包括具有单个衬底的多个半导体器件和多个沟槽区域，每个沟槽区域包括沟槽，其中单个衬底包括衬底层、设置在衬底层上的第一导电类型的第一外延层，以及设置在第一外延层上的第二导电类型的第二外延层，其中多个沟槽区域的每个沟槽穿过第二外延层延伸到第一外延层中，从而隔离多个半导体器件中的相邻半导体器件。

Description

半导体器件、半导体设备及其制造方法
相关申请的交叉引用
本申请要求于2018年6月30日提交的美国临时申请62/692,780的优先权，其标题为“III族氮化物功率器件和基于III族氮化物功率器件的高压集成电路平台”。出于所有目的，以上引用的申请的全部公开内容以引用的方式全部并入到本文中。
技术领域
本发明总体上涉及半导体领域，更具体地，涉及半导体器件、半导体设备以及制造相同半导体设备的方法。
背景技术
以下背景信息可能呈现现有技术的特定方面的示例(例如但不限于方法、事实或常识)，尽管预期它们将有助于进一步教导读者关于现有技术的其他方面，但是不应将它们解释为将本发明或其他任何实施例限制于其中叙述或暗示或在其基础上推断出的任何内容。
通常，III族氮化物具有适合于高压功率应用的高带隙。根据已知的设计，可通过在硅衬底上形成III族氮化物异质结来制造III族氮化物半导体器件。本领域中已知，与传统的硅基半导体器件相比，宽带隙半导体GaN器件的切换速度更快。应用工程师可利用这一特性来增加电力***的操作频率，从而减少***的体积和重量。
然而，尽管GaN器件能够以比硅基半导体器件高得多的频率操作，但是电力***的开关频率有时会受到功率回路中的寄生电感的限制。本领域技术人员将意识到，当半导体器件高速开关时，这些寄生电感可能会在半导体器件上产生高电压尖峰，从而导致器件和***故障。
一般来说，半导体器件的单片集成可显著降低寄生电感。典型的GaN器件的横向配置有益于多个器件的单片集成。在诸如桥式电路的功率开关应用中，有高压侧器件和低压侧器件。然而，为了将高压侧GaN器件与低压侧GaN器件集成在一起，存在与导电衬底的端接有关的技术挑战。
一般来说，当单片集成高压侧GaN器件和低压侧GaN器件时，衬底可连接到低压侧GaN器件的源极或高压侧GaN器件的源极。在两种情况下，衬底都会对源极未连接到衬底的器件产生背栅效应。此外，在功率开关应用中，半导体器件通常需要具有抵抗雪崩事件的能力。传统的GaN器件雪崩能力不足，因此它们不能应用于某些领域。
其它提议涉及GaN和III族氮化物半导体器件。这些半导体器件的问题是，它们不能克服背栅，并且它们没有足够的能力在雪崩事件中幸存。并且，这些半导体器件不能克服功率回路中的寄生电感。即使上文引用的GaN和III族氮化物半导体器件满足一些市场需求，但是仍然需要可在功率转换电路的设计和实现中作为开关进行操作的集成式III族氮化物半导体器件，并且能够克服雪崩能力不足、背栅和功率回路中的寄生电感。
发明内容
一个示例实施例提供一种半导体器件。该半导体器件包括：具有第一面和第二面的衬底层；第一导电类型的第一外延层，设置在衬底层的第一面上；第二导电类型的第二外延层，设置在第一外延层上，第二导电类型不同于第一导电类型；设置在第二外延层上的过渡层；设置在过渡层上的沟道层；设置在沟道层上的势垒层；以及接触势垒层并且电连接到第二外延层的第一电极。
本文中将解释其它示例实施例。
附图说明
现在将参考附图通过示例的方式描述本发明，图中：
图1示出根据第一实施例的半导体器件的示意性结构；
图2示出根据第二实施例的半导体器件的示意性结构；
图3示出根据实施例的半导体设备的部分结构，其中两个晶体管被沟槽隔开；
图4示出根据实施例的半导体设备的部分结构，其中两个二极管被沟槽隔开；
图5示出根据实施例的半导体设备的部分结构，其中晶体管和二极管被沟槽隔开；以及
在附图的各个视图中，相似的附图标记指代相似的部分。
具体实施方式
以下详细描述在本质上仅仅是示例性的，而不是要限制描述的实施例或描述的实施例的应用和使用。如本文中所使用，词语“示例性”或“说明性”是指“充当示例、实例或例证”。本文中被描述为“示例性”或“说明性”的任何实施方式不一定被解释为比其他实施方式优选或有利。以下描述的所有实施方式都是提供的示例性实施方式，以使本领域技术人员能够制造或使用本公开的实施方式，而不是要限制本公开的范围，本公开的范围由权利要求定义。出于本文中的描述的目的，“上”、“下”、“左”、“后”、“右”、“前”、“垂直”、“水平”及其衍生词应与图1所示的发明有关。此外，不希望受到上述技术领域、背景技术、发明内容或以下详细描述中介绍的任何表示或暗示的理论的约束。还将了解，在附图中示出并在以下说明书中描述的特定器件和过程只是在随附权利要求书中定义的本发明构思的示例性实施例。因此，除非权利要求书另外明确地规定，否则不应将与本文中公开的实施例有关的特定尺寸和其它物理特性视为是限制性。
一个或多个实施例认识到在常规器件和方法中存在的一个或多个技术问题。由于GaN能够携带大电流并支持高电压，所以III族氮化物半导体器件对于操作功率半导体器件是有效的。该半导体器件还提供非常低的导通电阻和快速的开关时间。该半导体器件由GaN的多种极性定义，包括Ga-极性、N-极性、半极性和非极性。该半导体器件单片集成到各种组件中，以便控制电流，例如控制LED。该半导体器件还为功率转换器、功率逆变器、电机驱动器和电机软起动器提供开关电源。
多个半导体器件可单片集成在单个衬底上。本领域中已知，半导体器件的单片集成可显著减少寄生电感。典型的GaN器件的横向配置有益于多个器件的单片集成。在诸如桥式电路的功率开关应用中，有高压侧器件和低压侧器件。然而，为了将高压侧GaN器件与低压侧GaN器件集成在一起，存在与导电衬底的端接有关的技术挑战，它会在某些偏置条件下建立背栅效应。此外，现有的GaN半导体器件的能力不足以抵抗雪崩事件。
如图1的示意图所示，根据第一实施例的半导体器件150包括衬底层100。衬底层100包括诸如硅的导电衬底。衬底层100包括n-型掺杂或p-型掺杂的硅衬底。在半导体器件150中使用的另一个层包括覆盖衬底层100的第一外延层101。第一外延层101由第一掺杂类型限定，第一掺杂类型可包括n-型掺杂。在一个非限制性实施例中，第一外延层101包括硅。
第二外延层102也覆盖衬底层100。第二外延层102由第二掺杂类型限定，第二掺杂类型可包括p-型掺杂。第二外延层102与第一外延层101形成结，由此可通过由第一外延层101和第二外延层102形成的结来维持特定电压。在一个非限制性实施例中，第二外延层102包括硅。
本发明的器件还包括过渡层201、沟道层202、势垒层203、源极电极301、栅极电极302、漏极电极303和衬底触点306。过渡层201与第二外延层102形成结。在一些实施例中，过渡层201包括以下至少之一：GaN、AlN、InN、AlGaN、InGaN和AlInGaN。半导体器件150的又一个层是与过渡层201形成结的沟道层202。沟道层202由沟道带隙限定。在一些实施例中，沟道层202包括以下至少之一：GaN、AlN、InN、AlGaN、InGaN和AlInGaN。
继续图1，势垒层203与沟道层202形成结。势垒层203的带隙大于沟道层202的带隙。在一些实施例中，势垒层203包括以下至少之一：GaN、AlN、InN、AlGaN、InGaN和AlInGaN。在一些实施例中，半导体器件150包括源极电极301。源极电极301电连接到第二外延层102。源极电极301和第二外延层102之间的连接位置有多个选择。例如，该连接可直接位于源极电极301下方，它也可以在器件的有源区之外。在诸如桥式电路的应用中，衬底触点306可电连接到高压侧器件的漏极。在诸如桥式电路的应用中，衬底触点306也可电连接到高压侧器件的阴极。衬底触点306也可以是浮动触点。
在一些实施例中，半导体器件150包括栅极电极302。在一个实施例中，在栅极电极302下方形成凹陷区域。在另一个实施例中，在栅极电极302下方形成电介质层。在又一个实施例中，在栅极电极302下方形成p-型帽盖层。在一些实施例中，半导体器件150还包括衬底触点306。在一个实施例中，衬底触点306电连接到漏极电极303。因此，从漏极电极303到第二外延层102形成垂直击穿电压。
为了提供在雪崩事件中幸存的能力，第一外延层101和第二外延层102之间的击穿电压低于漏极电极303和源极电极301之间的横向击穿电压。另外，第一外延层101和第二外延层102之间的击穿电压低于漏极电极303和栅极电极302之间的横向击穿电压。此外，第一外延层101和第二外延层102之间的击穿电压低于漏极电极303和第二外延层102之间的垂直击穿电压。因此，当发生雪崩事件时，可利用第一外延层101和第二外延层102之间的结来传递雪崩电流。
现在转到图2，根据另一个示意性实施例的半导体器件250包括许多相同的层，包括衬底层100、第一外延层101、第二外延层102、过渡层201、沟道层202和势垒层203。此外，阳极电极304电连接到第二外延层102。另外，还提供阴极电极305和衬底触点306。如上，过渡层201可包括GaN、AlN、InN、AlGaN、InGaN和AlInGaN之一或其组合。沟道层202可以是GaN、AlN、InN、AlGaN、InGaN和AlInGaN之一或其组合。势垒层203可包括GaN、AlN、InN、AlGaN、InGaN和AlInGaN之一或其组合。
半导体器件250还包括衬底触点306。在应用中，衬底触点306电连接到阴极电极305。在诸如桥式电路的应用中，衬底触点306可电连接到高压侧器件的漏极。在诸如桥式电路的应用中，衬底触点306也可电连接到高压侧器件的阴极。衬底触点306也可以是浮动触点。第一外延层101和第二外延层102之间的结配置成具有比从阴极电极305到阳极电极304的横向击穿电压更低的击穿电压。在另一个电压差中，从阴极电极305到第二外延层102形成垂直击穿电压。因此，当发生雪崩事件时，可利用第一外延层101和第二外延层102之间的结来传递雪崩电流。
在第二实施例中，第一外延层101和第二外延层102之间的击穿电压低于从阴极电极305到阳极电极304的横向击穿电压。在另一个实施例中，第一外延层101和第二外延层102之间的击穿电压低于从阴极电极305到第二外延层102的垂直击穿电压。以此方式，可利用第一外延层101和第二外延层102之间的结来传递雪崩电流。
本质上，根据实施例的半导体设备包括具有单个衬底的多个半导体器件和多个沟槽区域，并且每个沟槽区域包括沟槽，其中单个衬底包括衬底层、设置在衬底层上的第一导电类型的第一外延层以及设置在第一外延层上的第二导电类型的第二外延层，其中所述多个沟槽区域的每个沟槽穿过第二外延层延伸到第一外延层中，从而隔离所述多个半导体器件中的相邻半导体器件。
图3示出根据实施例的半导体设备350的部分结构。该示例实施例由两个集成晶体管组成，但是在实际实践中，可在一个芯片中集成两个以上的器件。该实施例包括单个衬底。该单个衬底包括衬底100、具有一种掺杂类型的外延层101、具有与外延层101的掺杂类型相反的掺杂类型的第二外延层102。第二外延层102被沟槽401分割成区域102a和102b。初始衬底100可以是硅衬底，并且它可掺杂成n-型或p-型。外延层101可以是n-型掺杂的硅层。第二外延层102可以是p-型掺杂的硅层。器件-1 001包括过渡层201a、沟道层202a、势垒层203a、源极电极301a、栅极电极302a和漏极电极303a。过渡层201a可包括GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。沟道层202a可以是GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。势垒层203a可包括GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。势垒层203a中的至少一个层具有比沟道层202a更大的带隙。器件-1 001的源极电极301a电连接到第二外延层102a。器件-2 002包括过渡层201b、沟道层202b、势垒层203b、源极电极301b、栅极电极302b和漏极电极303b。过渡层201b可包括GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。沟道层202b可以是GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。势垒层203b可包括GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。势垒层203b中的至少一个层具有比沟道层202b更大的带隙。器件-2的源极电极301b电连接到第二外延层102b。器件-1001和器件-2 002被沟槽隔离区域003隔开。沟槽隔离区域003包括延伸到外延层101中的沟槽401。可以用诸如SiO2、SiNx、Al2O3等的绝缘材料来填充沟槽401。也可用诸如SiO2、SiNx、Al2O3等的绝缘材料与诸如金属、多晶硅等的导电材料的组合来填充沟槽401，但是至少应当有绝缘材料。本发明的平台具有衬底触点306。在诸如桥式电路的应用中，衬底触点306可电连接到高压侧器件的漏极或高压侧器件的阴极。衬底触点306也可以是浮动触点。根据本发明的高压集成电路平台，该平台中的器件相互隔离，因此避免了背栅问题。此外，外延层101和外延层102之间的结提供了传递雪崩电流的能力。
图4示出根据另一个实施例的半导体设备450的部分结构，其中两个二极管被沟槽隔开。该示例实施例由两个集成二极管组成，但是在实际实践中，可在一个芯片中集成两个以上的器件。该实施例包括单个衬底。该单个衬底包括衬底层100、具有一种掺杂类型的外延层101、具有与外延层101的掺杂类型相反的掺杂类型的第二外延层102。第二外延层102被沟槽401分割成区域102a和102b。初始衬底100可以是硅衬底，并且它可掺杂成n-型或p-型。外延层101可以是n-型掺杂的硅层。第二外延层102可以是p-型掺杂的硅层。器件-1 001包括过渡层201a、沟道层202a、势垒层203a、阳极电极304a和阴极电极305a。过渡层201a可包括GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。沟道层202a可以是GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。势垒层203a可包括GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。势垒层203a中的至少一个层具有比沟道层202a更大的带隙。器件-1 001的阳极电极304a电连接到第二外延层102a。器件-2 002包括过渡层201b、沟道层202b、势垒层203b、阳极电极304b和阴极电极305b。过渡层201b可包括GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。沟道层202b可以是GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。势垒层203b可包括GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。势垒层203b中的至少一个层具有比沟道层202b更大的带隙。器件-2 002的阳极电极304b电连接到第二外延层102b。器件-1 001和器件-2 002被沟槽隔离区域003隔开。沟槽隔离区域003包括延伸到外延层101中的沟槽401。可以用诸如SiO2、SiNx、Al2O3等的绝缘材料来填充沟槽401。也可以用诸如SiO2、SiNx、Al2O3等的绝缘材料与诸如金属、多晶硅等的导电材料的组合来填充沟槽401，但是至少应当有绝缘材料。本发明的平台具有衬底触点306。在诸如桥式电路的应用中，衬底触点306可电连接到高压侧器件的阴极或高压侧器件的漏极。衬底触点306也可以是浮动触点。根据本发明的高压集成电路平台，该平台中的器件相互隔离，因此避免了背栅问题。此外，外延层101和外延层102之间的结提供了传递雪崩电流的能力。
图5示出根据另一个实施例的半导体设备550的部分结构，其中晶体管和二极管被沟槽隔开。该示例实施例由一个晶体管和一个二极管组成，但是在实际实践中，可在一个芯片中集成两个以上的器件。该平台包括衬底。衬底包括初始衬底100、具有一种掺杂类型的外延层101、具有与外延层101的掺杂类型相反的掺杂类型的第二外延层102。第二外延层102被沟槽401分割成区域102a和102b。初始衬底100可以是硅衬底，并且它可掺杂成n-型或p-型。外延层101可以是n-型掺杂的硅层。第二外延层102可以是p-型掺杂的硅层。器件-1001包括过渡层201a、沟道层202a、势垒层203a、源极电极301a、栅极电极302a和漏极电极303a。过渡层201a可包括GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。沟道层202a可以是GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。势垒层203a可包括GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。势垒层203a中的至少一个层具有比沟道层202a更大的带隙。器件-1 001的源极电极301a电连接到第二外延层102a。器件-2 002包括过渡层201b、沟道层202b、势垒层203b、阳极电极304b和阴极电极305b。过渡层201b可包括GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。沟道层202b可以是GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。势垒层203b可包括GaN、AlN、InN、AlGaN、InGaN、AlInGaN等之一或其组合。势垒层203b中的至少一个层具有比沟道层202b更大的带隙。器件-2 002的阳极电极304b电连接到第二外延层102b。器件-1 001和器件-2 002被沟槽隔离区域003隔开。沟槽隔离区域003包括延伸到外延层101中的沟槽401。可以用诸如SiO2、SiNx、Al2O3等的绝缘材料填充沟槽401。也可以用诸如SiO2、SiNx、Al2O3等的绝缘材料与金属、多晶硅等的导电材料的组合来填充沟槽401，但是至少要有绝缘材料。本发明的平台具有衬底触点306。在诸如桥式电路的应用中，衬底触点306可电连接到高压侧器件的漏极或阴极。衬底触点306也可以是浮动触点。根据本发明的高压集成电路平台，该平台中的器件相互隔离，因此避免了背栅问题。此外，外延层101和外延层102之间的结提供了传递雪崩电流的能力。
由于可对描述的本发明的优选实施例进行许多修改、变化和改变，因此希望将以上描述中以及在附图中示出的所有事项解释为是说明性而不是限制性的。因此，本发明的范围应当由所附权利要求及其法律等效物来确定。

Claims (19)

1.一种半导体器件，包括：
具有第一面和第二面的衬底层；
第一导电类型的第一外延层，设置在所述衬底层的所述第一面上；
第二导电类型的第二外延层，设置在所述第一外延层上，所述第二导电类型与所述第一导电类型不同；
设置在所述第二外延层上的过渡层；
设置在所述过渡层上的沟道层；
设置在所述沟道层上的势垒层；以及
接触所述势垒层并电连接到所述第二外延层的第一电极。
2.如权利要求1所述的半导体器件，其中所述第一电极通过延伸穿过所述势垒层、所述沟道层和所述过渡层而物理接触所述第二外延层。
3.如权利要求1所述的半导体器件，其中所述势垒层包括带隙大于所述沟道层的带隙的材料。
4.如权利要求1所述的半导体器件，还包括设置在所述势垒层上的第二电极，以及设置在所述衬底层的所述第二面上的第三电极。
5.如权利要求4所述的半导体器件，还包括设置在所述势垒层上并位于所述第一电极和所述第二电极之间的第四电极。
6.如权利要求1所述的半导体器件，其中所述半导体器件是III族氮化物半导体器件。
7.如权利要求1所述的半导体器件，其中所述第一导电类型是n-型，并且所述第二导电类型是p-型。
8.一种半导体设备，包括：
具有单个衬底的多个半导体器件；以及
多个沟槽区域，每个沟槽区域包括沟槽，
其中所述单个衬底包括衬底层、设置在所述衬底层上的第一导电类型的第一外延层，以及设置在所述第一外延层上的第二导电类型的第二外延层，
其中所述多个沟槽区域中的每个沟槽穿过所述第二外延层延伸到所述第一外延层中，从而隔离所述多个半导体器件中的相邻半导体器件。
9.如权利要求8所述的半导体设备，其中所述多个半导体器件选自二极管和/或晶体管。
10.如权利要求8所述的半导体设备，其中所述多个沟槽区域的每个沟槽填充有绝缘材料。
11.如权利要求10所述的半导体设备，其中所述绝缘材料选自SiO2、SiNx和/或Al2O3。
12.如权利要求10所述的半导体设备，其中每个沟槽进一步填充有导电材料。
13.如权利要求8所述的半导体设备，其中所述多个半导体器件中的每个半导体器件包括：
设置在所述第二外延层上的过渡层；
设置在所述过渡层上的沟道层；
设置在所述沟道层上的势垒层，所述势垒层包括带隙大于所述沟道层的带隙的材料；以及
接触所述势垒层并电连接到所述第二外延层的电极。
14.如权利要求13所述的半导体设备，其中所述过渡层包括一种或多种选自GaN、AlN、InN、AlGaN、InGaN和AlInGaN的材料。
15.如权利要求13所述的半导体设备，其中所述沟道层包括一种或多种选自GaN、AlN、InN、AlGaN、InGaN和AlInGaN的材料。
16.如权利要求13所述的半导体设备，其中所述势垒层包括一种或多种选自GaN、AlN、InN、AlGaN、InGaN和AlInGaN的材料。
17.一种制造半导体设备的方法，包括：
提供单个衬底；
在所述单个衬底上形成多个半导体器件，所述多个半导体器件是III族氮化物半导体器件；以及
通过形成多个沟槽区域以使所述多个沟槽区域延伸到所述单个衬底中来隔离相邻的半导体器件。
18.如权利要求17所述的方法，其中提供单个衬底包括：
提供衬底；
在所述衬底上形成第一导电类型的第一外延层；以及
在所述第一外延层上形成第二导电类型的第二外延层，使得所述第二外延层与所述第一外延层形成PN结。
19.如权利要求18所述的方法，其中形成所述多个沟槽区域包括：
进行蚀刻以便在所述多个沟槽区域中的每个沟槽区域中形成沟槽，使得所述沟槽穿过所述第二外延层并延伸到所述第一外延层中；以及
用至少一种绝缘材料填充所述沟槽。
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