CN111210783A - Pixel structure and display panel thereof - Google Patents
Pixel structure and display panel thereof Download PDFInfo
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- CN111210783A CN111210783A CN201811398303.8A CN201811398303A CN111210783A CN 111210783 A CN111210783 A CN 111210783A CN 201811398303 A CN201811398303 A CN 201811398303A CN 111210783 A CN111210783 A CN 111210783A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
The application provides a pixel structure and display panel thereof, the pixel structure includes: the pixel units are coupled with the corresponding scanning lines and the corresponding data lines and comprise: a first pixel unit having at least one first pixel circuit; a second pixel unit having at least one second pixel circuit; a first sharing switch, a first end of the first sharing switch being coupled to a common electrode; the first end of the second sharing switch is coupled with the common electrode; the first pixel unit and the second pixel unit are coupled to different scan lines arranged at intervals, the control terminal of the first sharing switch and the first pixel circuit are coupled to the same scan line, the control terminal of the second sharing switch and the first pixel circuit are coupled to the same scan line, and the first pixel unit and the second pixel unit are connected to the same data line.
Description
Technical Field
The present disclosure relates to display technologies, and particularly to a pixel structure and a display panel thereof.
Background
Liquid Crystal Displays (LCDs) have been widely used recently, and have advantages of low power consumption, light weight, and low voltage driving with the improvement of driving technology, and are widely used in video recorders, notebook computers, desktop displays, and various projection devices.
The liquid crystal display panel usually includes a gate driving circuit, a source driving circuit and a pixel array. The pixel array is provided with a plurality of pixel circuits, and each pixel circuit is turned on and off according to a scanning signal provided by the grid driving circuit and displays a data picture according to a data signal provided by the source driving circuit.
The liquid crystal display device includes a liquid crystal panel in which a plurality of pixels are arranged in a matrix form, and a driving circuit including a gate driver for driving gate lines of the liquid crystal panel and a data driver for driving data lines of the liquid crystal panel. In order to reduce the cost of the liquid crystal display device, it has been considered to reduce the number of output channels of the data driver by reducing the number of data lines while maintaining the resolution of the liquid crystal panel.
For example, a Double Rate Driving (DRD) type or Triple Rate Driving (TRD) type liquid crystal display device has been proposed, in which two or three horizontally adjacent sub-pixels are connected to a single data line and sequentially driven by different gate lines, so that the number of data lines and the number of output channels of a data driver can be reduced to half or one third compared to the conventional data lines and output channels.
And the DRD design can halve the number of the data lines, reduce the number of chips for driving the data lines, reduce the consumption of printed circuit boards and save the cost. However, DRD designs have a natural drawback: vertical bright and dark lines. Therefore, the application provides a new driving method to eliminate the vertical bright and dark lines.
Disclosure of Invention
An object of the present application is to provide a pixel structure, including: the pixel units are coupled with the corresponding scanning lines and the corresponding data lines and comprise: a first pixel unit having at least one first pixel circuit; a second pixel unit having at least one second pixel circuit; a first sharing switch, a first end of the first sharing switch being coupled to a common electrode; the first end of the second sharing switch is coupled with the common electrode; the first pixel unit and the second pixel unit are coupled to different scanning lines which are arranged at intervals, the control end of the first sharing switch and the first pixel circuit are coupled to the same scanning line, the control end of the second sharing switch and the first pixel circuit are coupled to the same scanning line, and the first pixel unit and the second pixel unit are connected to the same data line; wherein the first pixel unit and the second pixel unit can be charged and discharged simultaneously or only one of them is charged and discharged.
Another object of the present application is a pixel structure, comprising: a first pixel unit having at least one first pixel circuit; a second pixel unit having at least one second pixel circuit; a first sharing switch, a first end of the first sharing switch being coupled to a common electrode; the first end of the second sharing switch is coupled with the common electrode; the first pixel unit and the second pixel unit are coupled to different scanning lines which are arranged at intervals, the control end of the first sharing switch and the first pixel circuit are coupled to the same scanning line, the control end of the second sharing switch and the first pixel circuit are coupled to the same scanning line, and the first pixel unit and the second pixel unit are connected to the same data line; wherein the first pixel unit and the second pixel unit are arranged in an array; the first pixel unit and the second pixel unit are rectangular; the first pixel unit and the second pixel unit can be charged and discharged simultaneously or only one of them is charged and discharged.
Yet another object of the present application is a display panel including: a substrate; and a pixel structure, comprising: the pixel units are coupled with the corresponding scanning lines and the corresponding data lines and comprise: a first pixel unit having at least one first pixel circuit; a second pixel unit having at least one second pixel circuit; a first sharing switch, a first end of the first sharing switch being coupled to a common electrode; the first end of the second sharing switch is coupled with the common electrode; the first pixel unit and the second pixel unit are coupled to different scanning lines which are arranged at intervals, the control end of the first sharing switch and the first pixel circuit are coupled to the same scanning line, the control end of the second sharing switch and the first pixel circuit are coupled to the same scanning line, and the first pixel unit and the second pixel unit are connected to the same data line; wherein the first pixel unit and the second pixel unit are arranged in an array; the first pixel unit and the second pixel unit are rectangular; the first pixel unit and the second pixel unit can be charged and discharged simultaneously or only one of them is charged and discharged; the pixel structure is arranged on the substrate.
The purpose of the application and the technical problem to be solved are realized by adopting the following technical scheme.
In an embodiment of the present application, the first pixel units and the second pixel units are arranged in parallel and staggered.
In an embodiment of the present application, a second terminal of the first common switch is coupled to the second pixel circuit; the second end of the second sharing switch is coupled to the second pixel circuit.
In an embodiment of the present application, during a first scan period, the nth scan line and the (n + 4) th scan line are at high voltage, the first pixel circuit is charged, the first sharing switch is turned on, the second sharing switch is turned on, and the second pixel circuit is charge-shared, where n is a positive number.
In an embodiment of the present invention, during the second scan period, the (n + 1) th scan line and the (n + 5) th scan line are at high voltage, the first sharing switch is turned off, the second sharing switch is turned off, and the second pixel circuit is charged, wherein n is a positive number.
In an embodiment of the present application, a second terminal of the first common switch is coupled to the first pixel circuit; the second end of the second sharing switch is coupled to the first pixel circuit.
In an embodiment of the present application, during a first scan period, the nth scan line and the (n + 4) th scan line are at high voltage, the first pixel circuit is charged, the first sharing switch is turned on, the second sharing switch is turned on, and the first pixel circuit of the next pixel row performs charge sharing, where n is a positive number.
In an embodiment of the present application, during the second scan period, the (n + 1) th scan line and the (n + 5) th scan line are at high voltage, the first sharing switch is turned off, the second sharing switch is turned off, and the first pixel circuit of the next pixel row is charged, where n is a positive number.
The application eliminates vertical bright and dark lines and improves the product quality.
Drawings
FIG. 1 is a schematic diagram of an exemplary dual-rate drive faceplate;
FIG. 2a is a waveform of an exemplary N-1 th row of scan lines;
FIG. 2b is an exemplary Nth row waveform of a scan line;
FIG. 2c is a waveform diagram of an exemplary N +1 th row of scan lines;
FIG. 3a is a waveform diagram of the N-1 th row of the scan line according to an embodiment of the present application;
FIG. 3b is a diagram of an Nth row waveform of a scan line according to an embodiment of the present application;
FIG. 3c is a waveform diagram of the N +1 th row of the scan line according to an embodiment of the present application;
FIG. 4a is a waveform diagram of the N-4 th row of the scan line according to another embodiment of the present application;
FIG. 4b is a drawing of an Nth row waveform of a scan line according to another embodiment of the present application;
FIG. 4c is a waveform diagram of the N +4 th row of the scan line according to another embodiment of the present application;
FIG. 5 is a schematic diagram of active switch connections in a dual-rate-driving panel pixel structure according to an embodiment of the present application;
fig. 6 is a schematic diagram of active switch connections in a dual-rate-driving panel pixel structure according to another embodiment of the present application.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. In the present application, directional terms such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", and the like are merely referring to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting.
The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, elements having similar structures are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for understanding and ease of description, but the present application is not limited thereto.
In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thickness of some layers and regions are exaggerated for understanding and convenience of description. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.
In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components. Further, in the specification, "on.
To further illustrate the technical means and effects adopted by the present application to achieve the predetermined objects, the following detailed description is provided with reference to the accompanying drawings and specific embodiments for a pixel structure and a display panel thereof according to the present application, and specific embodiments, structures, features and effects thereof are described below.
FIG. 1 is a schematic diagram of an exemplary dual rate drive faceplate. Referring to fig. 1, a dual rate driving panel 10 includes a pixel composed of first and second sub-pixels of different colors, the first to second sub-pixels sharing a data line and being respectively connected to first and second scan lines, wherein one of the first and second sub-pixels is turned off on a per pixel basis, the other sub-pixel is charged with a data voltage having a reverse polarity compared to a data voltage previously applied through the data line for a first charging time including a charging time of the turned-off sub-pixel, and the other sub-pixels are charged with a data voltage having the same polarity as the data voltage previously applied through the data line for a second charging time.
Referring to fig. 1, in an embodiment, a dual-rate driving panel 10 is generally designed by using a 2-line or 1+ 2-line driving manner, for example, a 1+ 2-line driving manner; because of the delay of the data line information signal, the data signal obtained from the pixel of the N +1 th row of the scanning line is more complete than the Nth row of the scanning line of the previous row, so the difference of brightness can be generated in the gray scale picture; the pixels switched between positive and negative signals are always dark, and vertical bright and dark lines appear.
FIG. 2a is an exemplary N-1 column waveform of a scan line, FIG. 2b is an exemplary N column waveform of a scan line, and FIG. 2c is an exemplary N +1 column waveform of a scan line. Referring to fig. 1, fig. 2a, fig. 2b and fig. 2c, the DRD is generally designed by using a 2-line driving method or a 1+ 2-line driving method, and we take the 2-line driving method as an example; because the signal delay makes the waveform 21 of the data signal obtained by the pixels in the Gate N row more perfect than the waveform 22 of the Gate N +1 in the next row and the waveform 20 of the Gate N-1 in the previous row, the charge amount of the pixels in the Gate N row is more than that of the pixels in the Gate N +1 row and the Gate N-1 row (Sn is more than Sn +1 and Sn is more than Sn-1) in the same charge time, so the difference of brightness and darkness appears in the gray-scale picture; all pixels switched between positive and negative signals are always dark, and vertical bright and dark lines appear under a gray scale picture.
Fig. 3a is a waveform diagram of an N-1 th row of a scan line according to an embodiment of the present application, fig. 3b is a waveform diagram of an N-th row of a scan line according to an embodiment of the present application, and fig. 3c is a waveform diagram of an N +1 th row of a scan line according to an embodiment of the present application. Referring to fig. 1, fig. 3a, fig. 3b and fig. 3c, the Gate 1 and Gate 5 are precharged first, the charging time of each pixel is doubled, the charging amount of the two pixels before and after the charging time is maximized, and the charging amount of the Gate N +1 row waveform 32 and the charging amount of the Gate N row waveform 31 and the charging amount of the Gate N-1 row waveform 30 are consistent.
FIG. 4a is a waveform diagram of the N-4 th row of scan lines according to another embodiment of the present application, FIG. 4b is a waveform diagram of the N-th row of scan lines according to another embodiment of the present application, and FIG. 4c is a waveform diagram of the N +4 th row of scan lines according to another embodiment of the present application. Referring to fig. 1, 4a, 4b and 4c, the Gate 1 and Gate 5 are precharged first, and when the N-4 th row is scanned, the pixels of the waveform 40 of the Gate N-4 row start to be charged, and at this time, the Gate N row is opened in advance and also starts to be charged; when scanning the Nth row, the pixels of the Gate N row waveform 41 start to charge, and at the moment, the Gate N +4 row is opened in advance and also starts to charge; when the N +4 th row is scanned, the pixels of the waveform 42 of the Gate N +4 row start to be charged, and at the moment, the Gate N +8 row is opened in advance and also starts to be charged, so that the pixels of each row have twice charging time, the charging rate of the pixels is saturated, and the vertical bright and dark lines are eliminated.
Fig. 5 is a schematic diagram of active switch connections in a dual-rate-driving panel pixel structure according to an embodiment of the present application. Referring to fig. 5, in an embodiment of the present application, a pixel structure 50 includes: the pixel units 610, 611, 612, 613, 620, 621, 622, 623 in array configuration coupled to corresponding scan lines G1, G2, G3, G4, G5, G6, G7, G8 and data line D1 include: the first pixel units 610, 611, 612, 613, having at least one first pixel circuit 610, 611, 612, 613; second pixel units 620, 621, 622, 623 having at least one second pixel circuit 620, 621, 622, 623; a first switch T10, wherein a first terminal 101b of the first switch T10 is coupled to the common electrode Vcom, and a second terminal 101c of the first switch T10 is coupled to the second pixel circuit 621; a second sharing switch T20, wherein a first terminal 201b of the second sharing switch T20 is coupled to the common electrode Vcom, and a second terminal 201c of the second sharing switch T20 is coupled to the second pixel circuit 623; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are coupled to different scan lines G1, G2, G3, G4, G5, G6, G7, G8, the control terminal 101a of the first shared switch T10 and the first pixel circuit 610 are coupled to the same scan line G1, the control terminal 201a of the second shared switch T20 and the first pixel circuit 612 are coupled to the same scan line G5, and the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are connected to the same data line D1; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 can be charged and discharged simultaneously or only one of them can be charged and discharged.
Referring to fig. 5, in an embodiment of the present disclosure, the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are arranged in parallel and staggered.
Referring to fig. 5, in an embodiment of the present application, during a first scan period, an nth scan line G1 and an n +4 th scan line G5 are at a high voltage level, the first pixel circuits 610 and 612 are charged, the first sharing switch T10 is turned on, the second sharing switch T20 is turned on, and the second pixel circuits 621 and 623 share charges, where n is a positive number.
Referring to fig. 5, in an embodiment of the present application, during the second scan period, the (n + 1) th scan line G2 and the (n + 5) th scan line G6 are at high voltage, the first sharing switch T10 is turned off, the second sharing switch T20 is turned off, and the second pixel circuits 621 and 623 are charged, wherein n is a positive number.
Fig. 6 is a schematic diagram of active switch connections in a dual-rate-driving panel pixel structure according to another embodiment of the present application. Referring to fig. 6, in an embodiment of the present application, a pixel structure 60 includes: the pixel units 610, 611, 612, 613, 620, 621, 622, 623 in array configuration coupled to corresponding scan lines G1, G2, G3, G4, G5, G6, G7, G8 and data line D1 include: the first pixel units 610, 611, 612, 613, having at least one first pixel circuit 610, 611, 612, 613; second pixel units 620, 621, 622, 623 having at least one second pixel circuit 620, 621, 622, 623; a first switch T10, wherein a first terminal 101b of the first switch T10 is coupled to the common electrode Vcom, and a second terminal 101c of the first switch T10 is coupled to the first pixel circuit 611; a second sharing switch T20, wherein a first terminal 201b of the second sharing switch T20 is coupled to the common electrode Vcom, and a second terminal 201c of the second sharing switch T20 is coupled to the first pixel circuit 613; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are coupled to different scan lines G1, G2, G3, G4, G5, G6, G7, G8, the control terminal 101a of the first shared switch T10 and the first pixel circuit 610 are coupled to the same scan line G1, the control terminal 201a of the second shared switch T20 and the first pixel circuit 612 are coupled to the same scan line G5, and the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are connected to the same data line D1; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 can be charged and discharged simultaneously or only one of them can be charged and discharged.
Referring to fig. 6, in an embodiment of the present disclosure, the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are arranged in parallel and staggered.
Referring to fig. 6, in an embodiment of the present application, during a first scan period, the nth scan line G1 and the (n + 4) th scan line G5 are at high voltage, the first pixel circuits 610 and 612 are charged, the first sharing switch T10 is turned on, the second sharing switch T20 is turned on, and the first pixel circuits 611 and 613 of the next pixel row are charge-shared, where n is a positive number.
Referring to fig. 6, in an embodiment of the present invention, during the second scan period, the (n + 1) th scan line G2 and the (n + 5) th scan line G6 are at high voltage, the first sharing switch T10 is turned off, the second sharing switch T20 is turned off, and the first pixel circuits 611 and 613 of the next pixel row are charged, where n is a positive number.
Referring to fig. 5, in an embodiment of the present application, a pixel structure 50 includes: the pixel units 610, 611, 612, 613, 620, 621, 622, 623 in array configuration coupled to corresponding scan lines G1, G2, G3, G4, G5, G6, G7, G8 and data line D1 include: the first pixel units 610, 611, 612, 613, having at least one first pixel circuit 610, 611, 612, 613; second pixel units 620, 621, 622, 623 having at least one second pixel circuit 620, 621, 622, 623; a first switch T10, wherein a first terminal 101b of the first switch T10 is coupled to the common electrode Vcom, and a second terminal 101c of the first switch T10 is coupled to the second pixel circuit 621; a second sharing switch T20, wherein a first terminal 201b of the second sharing switch T20 is coupled to the common electrode Vcom, and a second terminal 201c of the second sharing switch T20 is coupled to the second pixel circuit 623; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are coupled to different scan lines G1, G2, G3, G4, G5, G6, G7, G8, the control terminal 101a of the first shared switch T10 and the first pixel circuit 610 are coupled to the same scan line G1, the control terminal 201a of the second shared switch T20 and the first pixel circuit 612 are coupled to the same scan line G5, and the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are connected to the same data line D1; wherein the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are arranged in an array; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are rectangular; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 can be charged and discharged simultaneously or only one of them can be charged and discharged.
Referring to fig. 5, in an embodiment of the present application, a display panel includes: a substrate (not shown); and a pixel structure 50, comprising: the pixel units 610, 611, 612, 613, 620, 621, 622, 623 in array configuration coupled to corresponding scan lines G1, G2, G3, G4, G5, G6, G7, G8 and data line D1 include: the first pixel units 610, 611, 612, 613, having at least one first pixel circuit 610, 611, 612, 613; second pixel units 620, 621, 622, 623 having at least one second pixel circuit 620, 621, 622, 623; a first switch T10, wherein a first terminal 101b of the first switch T10 is coupled to the common electrode Vcom, and a second terminal 101c of the first switch T10 is coupled to the second pixel circuit 621; a second sharing switch T20, wherein a first terminal 201b of the second sharing switch T20 is coupled to the common electrode Vcom, and a second terminal 201c of the second sharing switch T20 is coupled to the second pixel circuit 623; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are coupled to different scan lines G1, G2, G3, G4, G5, G6, G7, G8, the control terminal 101a of the first shared switch T10 and the first pixel circuit 610 are coupled to the same scan line G1, the control terminal 201a of the second shared switch T20 and the first pixel circuit 612 are coupled to the same scan line G5, and the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are connected to the same data line D1; wherein the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are arranged in an array; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are rectangular; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 can be charged and discharged simultaneously or only one of them is charged and discharged; the pixel structure 50 is disposed on the substrate.
Referring to fig. 6, in an embodiment of the present application, a pixel structure 60 includes: the pixel units 610, 611, 612, 613, 620, 621, 622, 623 in array configuration coupled to corresponding scan lines G1, G2, G3, G4, G5, G6, G7, G8 and data line D1 include: the first pixel units 610, 611, 612, 613, having at least one first pixel circuit 610, 611, 612, 613; second pixel units 620, 621, 622, 623 having at least one second pixel circuit 620, 621, 622, 623; a first switch T10, wherein a first terminal 101b of the first switch T10 is coupled to the common electrode Vcom, and a second terminal 101c of the first switch T10 is coupled to the first pixel circuit 611; a second sharing switch T20, wherein a first terminal 201b of the second sharing switch T20 is coupled to the common electrode Vcom, and a second terminal 201c of the second sharing switch T20 is coupled to the first pixel circuit 613; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are coupled to different scan lines G1, G2, G3, G4, G5, G6, G7, G8, the control terminal 101a of the first shared switch T10 and the first pixel circuit 610 are coupled to the same scan line G1, the control terminal 201a of the second shared switch T20 and the first pixel circuit 612 are coupled to the same scan line G5, and the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are connected to the same data line D1; wherein the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are arranged in an array; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are rectangular; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 can be charged and discharged simultaneously or only one of them can be charged and discharged.
Referring to fig. 6, in an embodiment of the present application, a display panel includes: a substrate (not shown); and a pixel structure 60, comprising: the pixel units 610, 611, 612, 613, 620, 621, 622, 623 in array configuration coupled to corresponding scan lines G1, G2, G3, G4, G5, G6, G7, G8 and data line D1 include: the first pixel units 610, 611, 612, 613, having at least one first pixel circuit 610, 611, 612, 613; second pixel units 620, 621, 622, 623 having at least one second pixel circuit 620, 621, 622, 623; a first switch T10, wherein a first terminal 101b of the first switch T10 is coupled to the common electrode Vcom, and a second terminal 101c of the first switch T10 is coupled to the first pixel circuit 611; a second sharing switch T20, wherein a first terminal 201b of the second sharing switch T20 is coupled to the common electrode Vcom, and a second terminal 201c of the second sharing switch T20 is coupled to the first pixel circuit 613; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are coupled to different scan lines G1, G2, G3, G4, G5, G6, G7, G8, the control terminal 101a of the first shared switch T10 and the first pixel circuit 610 are coupled to the same scan line G1, the control terminal 201a of the second shared switch T20 and the first pixel circuit 612 are coupled to the same scan line G5, and the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are connected to the same data line D1; wherein the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are arranged in an array; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 are rectangular; the first pixel units 610, 611, 612, 613 and the second pixel units 620, 621, 622, 623 can be charged and discharged simultaneously or only one of them is charged and discharged; the pixel structure 60 is disposed on the substrate.
In some embodiments of the present application, the Display panel may comprise a Liquid Crystal Display (LCD) panel, wherein the Liquid Crystal Display (LCD) panel comprises: a TFT (thin film transistor) substrate, a Color Filter (CF) substrate, and a liquid crystal layer formed between the two substrates, and the display panel is also an Organic Light-Emitting Diode (OLED) panel or a Quantum dot Light-Emitting Diode (QLED) panel.
The application eliminates vertical bright and dark lines and improves the product quality.
The terms "in some embodiments" and "in various embodiments" are used repeatedly. The terms generally do not refer to the same embodiment; it may also refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise.
Although the present application has been described with reference to specific embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.
Claims (10)
1. A pixel structure, comprising: the pixel units are coupled with the corresponding scanning lines and the corresponding data lines and comprise:
a first pixel unit having at least one first pixel circuit;
a second pixel unit having at least one second pixel circuit;
a first sharing switch, a first end of the first sharing switch being coupled to a common electrode; and
a second shared switch, a first end of the second shared switch being coupled to the common electrode;
the first pixel unit and the second pixel unit are coupled to different scanning lines which are arranged at intervals, the control end of the first sharing switch and the first pixel circuit are coupled to the same scanning line, the control end of the second sharing switch and the first pixel circuit are coupled to the same scanning line, and the first pixel unit and the second pixel unit are connected to the same data line; wherein the first pixel unit and the second pixel unit can be charged and discharged simultaneously or only one of them is charged and discharged.
2. The pixel structure of claim 1, wherein the first pixel units and the second pixel units are arranged in a parallel-staggered manner.
3. The pixel structure of claim 1, wherein a second terminal of the first common switch is coupled to the second pixel circuit; the second end of the second sharing switch is coupled to the second pixel circuit.
4. The pixel structure as claimed in claim 3, wherein during a first scan period, the nth scan line and the (n + 4) th scan line are at high voltage, the first pixel circuit is charged, the first sharing switch is turned on, the second sharing switch is turned on, and the second pixel circuit is charge-shared, wherein n is a positive number.
5. The pixel structure of claim 3, wherein during a second scan period, the (n + 1) th scan line and the (n + 5) th scan line are at a high voltage level, the first sharing switch is turned off, the second sharing switch is turned off, and the second pixel circuit is charged, wherein n is a positive number.
6. The pixel structure of claim 1, wherein a second terminal of the first common switch is coupled to the first pixel circuit; the second end of the second sharing switch is coupled to the first pixel circuit.
7. The pixel structure as claimed in claim 6, wherein during the first scan period, the nth scan line and the (n + 4) th scan line are high, the first pixel circuit is charged, the first sharing switch is turned on, the second sharing switch is turned on, and the first pixel circuit of the next pixel row is charge-shared, wherein n is a positive number.
8. The pixel structure of claim 6, wherein during a second scan period, the (n + 1) th scan line and the (n + 5) th scan line are at a high voltage level, the first sharing switch is turned off, the second sharing switch is turned off, and the first pixel circuit of the next pixel row is charged, wherein n is a positive number.
9. A pixel structure, comprising:
a first pixel unit having at least one first pixel circuit;
a second pixel unit having at least one second pixel circuit;
a first sharing switch, a first end of the first sharing switch being coupled to a common electrode; and
a second shared switch, a first end of the second shared switch being coupled to the common electrode;
the first pixel unit and the second pixel unit are coupled to different scanning lines which are arranged at intervals, the control end of the first sharing switch and the first pixel circuit are coupled to the same scanning line, the control end of the second sharing switch and the first pixel circuit are coupled to the same scanning line, and the first pixel unit and the second pixel unit are connected to the same data line; wherein the first pixel unit and the second pixel unit are arranged in an array; the first pixel unit and the second pixel unit are rectangular; the first pixel unit and the second pixel unit can be charged and discharged simultaneously or only one of them is charged and discharged.
10. A display panel, comprising:
a substrate; and
a pixel structure, comprising: the pixel units are coupled with the corresponding scanning lines and the corresponding data lines and comprise:
a first pixel unit having at least one first pixel circuit;
a second pixel unit having at least one second pixel circuit;
a first sharing switch, a first end of the first sharing switch being coupled to a common electrode; and
a second shared switch, a first end of the second shared switch being coupled to the common electrode;
the first pixel unit and the second pixel unit are coupled to different scanning lines which are arranged at intervals, the control end of the first sharing switch and the first pixel circuit are coupled to the same scanning line, the control end of the second sharing switch and the first pixel circuit are coupled to the same scanning line, and the first pixel unit and the second pixel unit are connected to the same data line; wherein the first pixel unit and the second pixel unit are arranged in an array; the first pixel unit and the second pixel unit are rectangular; the first pixel unit and the second pixel unit can be charged and discharged simultaneously or only one of them is charged and discharged;
the pixel structure is arranged on the substrate.
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| CN201811398303.8A CN111210783A (en) | 2018-11-22 | 2018-11-22 | Pixel structure and display panel thereof |
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