CN111209199B - Method and device for verifying relevance of instruction, electronic equipment and storage medium - Google Patents

Method and device for verifying relevance of instruction, electronic equipment and storage medium Download PDF

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CN111209199B
CN111209199B CN201911421715.3A CN201911421715A CN111209199B CN 111209199 B CN111209199 B CN 111209199B CN 201911421715 A CN201911421715 A CN 201911421715A CN 111209199 B CN111209199 B CN 111209199B
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verification
instruction
instructions
program
programs
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CN111209199A (en
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苏东阁
孙成璐
杨寒雪
刘红红
纪楠
薛凌艺
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Xian Xiangteng Microelectronics Technology Co Ltd
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Xian Xiangteng Microelectronics Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G06F11/3688—Test management for test execution, e.g. scheduling of test suites
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a method and a device for verifying relevance of instructions, electronic equipment and a storage medium. The method comprises the following steps: respectively executing a plurality of first verification programs, a plurality of second verification programs and a plurality of third verification programs to obtain verification results; wherein the first verification program and the second verification program are each comprised of one or more stimulus test programs; the third verification program consists of a first verification program and a second verification program which are randomly selected; each stimulus test program contains a set of data-related, structure-related, or control-related instructions. The number of instructions contained in the first verification program is smaller than or equal to the size of an instruction emission window of the graphic processor; the number of the instructions contained in the second verification program is larger than the size of the instruction emission window; the invention can comprehensively acquire various conditions related to the instruction which are easy to appear in the graphic processor, thereby improving the guiding value of the instruction correlation verification result on the condition of avoiding the instruction correlation.

Description

Method and device for verifying relevance of instruction, electronic equipment and storage medium
Technical Field
The invention belongs to the field of computer graphics, and particularly relates to a method and a device for verifying the relevance of instructions, electronic equipment and a storage medium.
Background
In the field of computer graphics, whether instructions run in a graphics processor are relevant is an important factor affecting the execution efficiency and execution accuracy of a program. Here, instruction correlation includes data correlation, structure correlation, and control correlation. Wherein, the instruction correlation refers to the data correlation involved in the operation of the instruction; the structural correlation refers to the hardware structural resource correlation required by the running instruction; control correlation refers to the pipelined processing of instructions. In order to improve the execution efficiency and execution accuracy of the program, it is necessary to perform verification of instruction correlation in advance in the graphics processor, and further to avoid the instruction correlation that is easily generated in the graphics processor by taking the verification result as a guide.
In the related art, in a correlation verification method applied to instructions in a graphics processor, a verification program is generally written separately for each type of instruction correlation; and then, sequentially running each written verification program to obtain a correlation verification result of the instruction in the graphic processor.
However, the inventors found that the result of the correlation verification of the instruction obtained in the related art is not sufficient to comprehensively learn various conditions of the instruction correlation which are easily occurred in the graphics processor, so that the result of the correlation verification of the instruction has low guiding value for avoiding the conditions of the instruction correlation.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a correlation verification method, apparatus, electronic device and storage medium. The technical problems to be solved by the invention are realized by the following technical scheme:
in a first aspect, an embodiment of the present invention provides a method for verifying relevance of an instruction, which is applied to an electronic device, where the electronic device includes a graphics processor, and the method includes:
respectively executing a plurality of preset first verification programs to obtain a first verification result; wherein any one of the first verification programs is composed of one or more excitation test programs selected from a plurality of preset excitation test programs; each excitation test program comprises a group of data-related, structure-related or control-related instructions, and the sum of the numbers of the instructions contained in the excitation test program forming any first verification program is not more than the number of instruction emission indicated by the size of an instruction emission window of the graphic processor;
Respectively executing a plurality of preset second verification programs to obtain a second verification result; wherein any one of the second verification programs is composed of one or more excitation test programs selected from the plurality of excitation test programs, and the sum of the numbers of instructions contained in the excitation test programs composing any one of the second verification programs is larger than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor;
respectively executing a plurality of preset third verification programs to obtain a third verification result; any one of the third verification programs is composed of at least one first verification program and at least one second verification program which are selected randomly.
In an embodiment of the present invention, the step of respectively executing a plurality of preset second verification procedures to obtain a second verification result includes:
aiming at each second verification program, transmitting the instructions in the excitation test program contained in the second verification program into an instruction execution unit of the graphic processor in groups for execution according to the instruction transmission number indicated by the size of the instruction transmission window, and obtaining an execution result of each group of instructions;
and determining whether the instruction in the group of instructions and the instruction which does not execute the write-back operation in the previous group of instructions are related to verification information according to the execution result of the instructions in each group of instructions which are not the first group, obtaining a plurality of verification information, and taking the plurality of verification information as a second verification result.
In one embodiment of the present invention, any one of the excitation test procedures is a procedure constructed with at least one of a plurality of preset reference information as a reference;
wherein the plurality of reference information includes: the register read-write path of the graphics processor, the types of the various instruction execution units contained in the graphics processor, the number of each type of instruction execution units, the processing pipeline structure of each type of instruction execution units, the instruction execution period of each type of instruction execution units, and the read-write operation type of each type of instruction execution units read-write instructions.
In one embodiment of the present invention, when constructing an excitation test program containing data-dependent instructions, reference information as a reference includes:
the instruction execution unit reads and writes the read-write operation type of the instruction, the flow processing structure of the instruction execution unit and the instruction execution period of the instruction execution unit.
In one embodiment of the invention, an excitation test program containing structurally related instructions includes: an excitation test program containing instructions related to the instruction execution unit, and an excitation test program containing instructions related to the register read-write path;
Wherein, when constructing the stimulus test program including the instruction related to the instruction execution unit, the reference information as the reference includes:
the graphics processor includes a variety of instruction execution units, a number of instruction execution units of each type, a processing pipeline structure of the instruction execution units of each type, and an instruction execution cycle of the instruction execution units of each type;
when constructing an excitation test program containing instructions related to a register read-write path, reference information as a reference includes:
the register read-write channel of the graphic processor, the read-write operation type of each type of instruction execution unit read-write instruction and the instruction execution period of each type of instruction execution unit.
In one embodiment of the invention, when constructing an excitation test program containing control-related instructions, the reference information as a reference includes: a processing pipeline structure of each instruction execution unit and an instruction execution cycle of each instruction execution unit.
In one embodiment of the invention, the instruction is embodied as a shader instruction in the graphics processor.
In a second aspect, an embodiment of the present invention provides a device for verifying relevance of an instruction, where the device is applied to an electronic device, and the electronic device includes a graphics processor, and the device includes:
The first execution module is used for respectively executing a plurality of preset first verification programs to obtain a first verification result; wherein any one of the first verification programs is composed of one or more excitation test programs selected from a plurality of preset excitation test programs; each excitation test program comprises a group of data-related, structure-related or control-related instructions, and the sum of the numbers of the instructions contained in the excitation test program forming any first verification program is not more than the number of instruction emission indicated by the size of an instruction emission window of the graphic processor;
the second execution module is used for respectively executing a plurality of preset second verification programs to obtain a second verification result; wherein any one of the second verification programs is composed of one or more excitation test programs selected from the plurality of excitation test programs, and the sum of the numbers of instructions contained in the excitation test programs composing any one of the second verification programs is larger than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor;
the third execution module is used for respectively executing a plurality of preset third verification programs to obtain a third verification result; any one of the third verification programs is composed of at least one first verification program and at least one second verification program which are selected randomly.
In one embodiment of the present invention, the second execution unit is specifically configured to:
aiming at each second verification program, transmitting the instructions in the excitation test program contained in the second verification program into an instruction execution unit of the graphic processor in groups for execution according to the instruction transmission number indicated by the size of the instruction transmission window, and obtaining an execution result of each group of instructions;
and determining whether the instruction in the group of instructions and the instruction which does not execute the write-back operation in the previous group of instructions are related to verification information according to the execution result of the instructions in each group of instructions which are not the first group, obtaining a plurality of verification information, and taking the plurality of verification information as a second verification result.
In one embodiment of the present invention, any one of the excitation test procedures is a procedure constructed with at least one of a plurality of preset reference information as a reference;
wherein the plurality of reference information includes: the register read-write path of the graphics processor, the types of the various instruction execution units contained in the graphics processor, the number of each type of instruction execution units, the processing pipeline structure of each type of instruction execution units, the instruction execution period of each type of instruction execution units, and the read-write operation type of each type of instruction execution units read-write instructions.
In one embodiment of the present invention, when constructing an excitation test program containing data-dependent instructions, reference information as a reference includes:
the instruction execution unit reads and writes the read-write operation type of the instruction, the flow processing structure of the instruction execution unit and the instruction execution period of the instruction execution unit.
In one embodiment of the invention, an excitation test program containing structurally related instructions includes: an excitation test program containing instructions related to the instruction execution unit, and an excitation test program containing instructions related to the register read-write path;
wherein, when constructing the stimulus test program including the instruction related to the instruction execution unit, the reference information as the reference includes:
the graphics processor includes a variety of instruction execution units, a number of instruction execution units of each type, a processing pipeline structure of the instruction execution units of each type, and an instruction execution cycle of the instruction execution units of each type;
when constructing an excitation test program containing instructions related to a register read-write path, reference information as a reference includes:
the register read-write channel of the graphic processor, the read-write operation type of each type of instruction execution unit read-write instruction and the instruction execution period of each type of instruction execution unit.
In one embodiment of the invention, when constructing an excitation test program containing control-related instructions, the reference information as a reference includes: a processing pipeline structure of each instruction execution unit and an instruction execution cycle of each instruction execution unit.
In one embodiment of the invention, the instruction is embodied as a shader instruction in the graphics processor.
In a third aspect, an embodiment of the present invention provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;
a memory for storing a computer program;
and the processor is used for realizing the method steps of the correlation verification method of any instruction when executing the program stored in the memory.
In a fourth aspect, an embodiment of the present invention provides a computer readable storage medium, where a computer program is stored, where the computer program when executed by a processor implements the method steps of the correlation verification method of any of the instructions described above.
The invention has the beneficial effects that:
in the method for verifying the correlation of the instruction provided by the embodiment of the invention, a plurality of first verification programs, a plurality of second verification programs and a plurality of third verification programs are preset; each first verification program and each second verification program are composed of one or more excitation test programs selected from a plurality of preset excitation test programs; each third verification program is composed of at least one first verification program selected randomly and at least one second verification program selected randomly. And the sum of the numbers of the instructions contained in the excitation test program of any one of the first verification programs is not more than the number of the instruction emission indicated by the size of the instruction emission window of the graphic processor; the number of instructions included in the stimulus test program of any one of the second verification programs together with the sum of the numbers of instructions greater than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor may be used to verify a correlation for each of the stimulus test programs. Because each excitation test program contains a group of data-related, structure-related or control-related instructions, one type of correlation can be verified, and therefore, various possible instruction-related conditions in an instruction emission window can be comprehensively verified by executing a plurality of preset first verification programs; by executing a plurality of preset second verification programs, various possible conditions related to the instruction among the instruction emission windows can be comprehensively verified; by executing a plurality of preset third verification programs, various possible instruction-related conditions caused by different instruction execution timings in and among the instruction emission windows can be comprehensively verified. Therefore, various conditions related to the instruction which are easy to appear in the graphic processor can be comprehensively known, so that the guiding value of the instruction correlation verification result for avoiding the conditions related to the instruction is improved.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a flow chart of a method for verifying the relevance of an instruction according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of correlation verification performed by the steps in the method of FIG. 1;
FIG. 3 is a schematic diagram illustrating a construction manner of a plurality of preset first verification procedures, a plurality of preset second verification procedures, and a plurality of preset third verification procedures in the method shown in FIG. 1;
FIG. 4 is a schematic diagram of stimulus test procedures respectively included in a preset plurality of first verification procedures, a preset plurality of second verification procedures and a preset plurality of third verification procedures in the method shown in FIG. 1;
FIG. 5 is a flowchart illustrating another method for verifying the relevance of an instruction according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an apparatus for verifying correlation of instructions according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
It should be noted that, the execution body of the method for verifying the correlation of the instruction provided by the embodiment of the invention may be a graphics processor, and the graphics processor may be applied to an electronic device. In a specific application, the electronic device may be a desktop computer, a portable computer, an intelligent mobile terminal, a server or other electronic device with a graphics processor, etc. In addition, the electronic device may also be a circuit board of a semi-finished product. It will be appreciated that when the graphics processor is implemented in a circuit board, the circuit board has peripheral circuitry communicatively coupled to the graphics processor to support the operation of the circuit board.
In the embodiment of the invention, a plurality of excitation test programs are constructed in advance according to one or more of a plurality of reference information. Wherein each stimulus test program contains a set of data-related, structure-related, or control-related instructions. It will be appreciated that since the stimulus test program contains associated instructions, the stimulus test program is a program that can trigger correlations between instructions. Wherein, if an excitation test program includes a set of data-related instructions, it indicates that the data related to the set of instructions included in the excitation test program is related; if an excitation test program contains a group of instructions related to structure, the hardware structure resources required by executing the group of instructions contained in the excitation test program are related; if an excitation test program contains a set of control-related instructions, it is indicated that the pipeline is relevant when the excitation test program executes the set of instructions contained in the excitation test program. Thus, for each stimulus test program, any one of data correlation, structural correlation, or control correlation may be used to verify.
Then, selecting one or more excitation test programs from the constructed plurality of excitation test programs in multiple times, and respectively forming a plurality of first verification programs and a plurality of second verification programs. Wherein the sum of the numbers of instructions contained in the stimulus test program constituting the first verification program is not greater than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor; the stimulus test program constituting the second verification program includes a sum of the numbers of instructions greater than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor.
It will be appreciated that since the sum of the numbers of instructions included in the stimulus test program constituting the first verification program is not greater than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor, the instruction emission window of the graphics processor can emit each instruction included in the first verification program into the instruction execution unit at one time for execution. That is, the first verification program may be used to verify the correlation of instructions within the instruction issue window. The second verification procedure may then be adapted to verify the correlation of instructions between instruction issue windows.
In addition, it can be understood that, in order to more comprehensively learn various conditions related to instructions that easily occur in the graphics processor, when constructing a plurality of stimulus test programs, different stimulus test programs can be respectively constructed for the conditions related to various instructions that may occur. In this way, when a plurality of stimulus test programs are selected from the constructed plurality of stimulus test programs to form the first verification program or the second verification program, the constructed first verification program or the constructed second verification program can include the stimulus test program capable of verifying one correlation and the stimulus test program capable of verifying a plurality of correlations simultaneously, so that the effect of combined verification is achieved. In addition, in order to comprehensively know the conditions related to various combinations of instructions which are easy to occur in the graphics processor, different first verification programs and different second verification programs can be respectively formed aiming at the conditions related to various combinations of instructions which are likely to occur. For the sake of clear solution and clear layout, the stimulus test procedure included in each of the preset first verification procedures and the second verification procedures will be described in the following exemplary manner.
Example 1
Referring to fig. 1, fig. 1 is a flowchart of a method for verifying relevance of an instruction according to an embodiment of the present invention, where the method may include the following steps:
step S101: and respectively executing a plurality of preset first verification programs to obtain a first verification result.
Wherein, any first verification program is composed of one or more excitation test programs selected from a plurality of preset excitation test programs; each stimulus test program includes a set of data-related, structure-related, or control-related instructions, and the sum of the numbers of instructions included in the stimulus test program that constitute any one of the first verification programs is not greater than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor.
It will be appreciated that for each first verification program, if the first verification program consists of an incentive test program, the first verification program may verify a correlation; if the first verification program is composed of a plurality of excitation test programs, the first verification program can verify various correlations to achieve the effect of combined verification. It should be emphasized that since the sum of the numbers of instructions included in the stimulus test programs constituting any one of the first verification programs is not greater than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor, each of the first verification programs, including several stimulus test programs, can be executed in the instruction execution unit that emits the instructions to the graphics processor within one instruction emission window.
In this step, a plurality of first verification programs may be executed in the graphics processor in a predetermined arrangement order. Specifically, for each first verification program, according to the number of instruction emission indicated by the size of an instruction emission window of the graphics processor, the instructions in the excitation test program contained in the first verification program are emitted into an instruction execution unit of the graphics processor in groups for execution, so that an execution result of each group of instructions is obtained; and determining whether the instructions in the group of instructions are related to verification information according to the execution result of each group of instructions, obtaining a plurality of verification information, and taking the verification information as a first verification result.
The first verification results obtained by executing the plurality of first verification programs may be determined based on the execution results of the plurality of first verification programs. Specifically, for the graphics processor, if the condition related to the instruction occurs in the executed first verification program, the flow of processing the instruction by the graphics processor may be changed, or even a processing error may occur, and at this time, the graphics processor may detect the change or the error of the flow. In practical application, the circuit board or the electronic device to which the graphics processor belongs is connected with a computer provided with simulation software, so that the flow change or error detected by the graphics processor can be intuitively observed in the simulation software. It can be understood that, in addition to the verification information about whether the instruction is related, the execution result of the first verification program may further include other information such as an operation result of the instruction itself, and the other information is not related to the present solution, so that details are not described here.
Step S102: and respectively executing a plurality of preset second verification programs to obtain a second verification result.
Wherein any one of the second verification programs is constituted by one or more stimulus test programs selected from the plurality of stimulus test programs, and the sum of the numbers of instructions contained in the stimulus test programs constituting any one of the second verification programs is larger than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor.
It will be appreciated that since the sum of the numbers of instructions contained in the stimulus test program constituting any one of the second verification programs is greater than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor, each of the second verification programs is executed in the instruction execution units that are emitted to the graphics processor within the plurality of instruction emission windows.
And, for each second verification program, if the second verification program is constituted by an incentive test program, the second verification program can verify a correlation; if the second verification program is composed of a plurality of excitation test programs, the second verification program can verify a plurality of correlations, so that the effect of realizing combined verification of the plurality of correlations among instruction emission windows is achieved.
In this step, a plurality of second verification programs may be executed in the graphics processor in a predetermined arrangement order, respectively. Specifically, for each second verification program, according to the number of instruction emission indicated by the size of the instruction emission window, the instructions in the excitation test program contained in the second verification program are emitted into an instruction execution unit of the graphics processor in groups for execution, and an execution result of each group of instructions is obtained; and determining whether the instructions in the group of instructions and the instructions which do not execute the write-back operation in the previous group of instructions are related to verification information according to the execution result of the instructions in each group of instructions which are not the first group, obtaining a plurality of verification information, and taking the verification information as a second verification result.
Here, according to the execution result of each set of instructions other than the first set of instructions, verification information about whether the instructions in the set of instructions and the instructions in the previous set of instructions that do not execute the write-back operation are related to each other is determined, and in step S101, a specific implementation manner of determining the first verification result according to the execution results of the plurality of first verification programs is similar to that described in detail herein.
It is understood that the plurality of pieces of verification information constituting the second verification result are verification information on whether or not the instructions between the plurality of instruction emission windows are related, which is different from the first verification result obtained in step S101. Of course, in another implementation, the second verification result obtained in step S102 may include verification information about whether the instructions transmitted in the same instruction transmission window are related or not, and verification information about whether the instructions transmitted in the multiple instruction transmission windows are related or not.
In addition, it can be understood that the execution result of the second verification program may include other information such as an operation result of the instruction itself, besides the verification information about whether the instruction is related, and the other information is irrelevant to the present scheme, so that no description is repeated here.
Step S103: and respectively executing a plurality of preset third verification programs to obtain a third verification result.
Wherein, any one of the third verification programs is composed of at least one first verification program and at least one second verification program which are selected randomly.
It can be understood that, since the third verification program includes both the first verification program and the second verification program, when the third verification program is executed, the specific implementation manner of the first verification program may be referred to in step S101, and the first verification program included in the third verification program may be executed; referring to step S102, a specific implementation manner of the second verification program is executed, and the second verification program included in the third verification program is executed. And determining a third verification result according to the execution result of each first verification program and the execution result of each second verification program. Here, the specific implementation manner of determining the third verification result according to the execution results of the various verification programs may refer to step S101, and the specific implementation manner of determining the first verification result according to the execution results of the plurality of first verification programs is similar, which is not described herein.
In practical applications, when the execution time of a program is different, the pipeline processing process of the same program in the graphics processor is different due to the influence of factors such as the number and types of instructions supportable by an instruction execution unit of the graphics processor, and the difference may cause the difference of the results of the instruction correlation in the program. Therefore, in the embodiment of the present invention, at least one first authentication program and at least one second authentication program are randomly selected from the existing plurality of first authentication programs and the existing plurality of second authentication programs to form a third authentication program; thus, when these third verification programs are run in the graphic processor, it is possible to simulate different situations of the first verification program and the second verification program included in the third verification program at different timings, thereby achieving a verification effect similar to the stress test. Here, the stress test is a software test means common in the software field. The purpose of performing the stress test is to run the software program under unusual conditions, thereby stimulating potential faults in the software program.
It can be appreciated that after the first verification result, the second verification result, and the third verification result are obtained, the correlation verification result of the instruction of the complete graphics processor is obtained.
In order to better embody the comprehensiveness of the instruction verification method provided by the embodiment of the present invention, fig. 2 is used to illustrate the specific execution of the correlation verification of each step in the instruction correlation verification method provided by the embodiment of the present invention.
As shown in fig. 2, the correlation verification specifically performed in step S101 includes: performing data dependency verification, structure dependency verification, control dependency verification, and combination verification of three dependencies of an instruction within an instruction emission window of a graphics processor;
the correlation verification specifically performed in step S102 includes: performing data correlation verification, structure correlation verification, control correlation verification and combination verification of three correlations of instructions among instruction emission windows of the graphic processor;
the correlation verification specifically performed in step S103 includes: and randomly combining various correlation verifications in the instruction emission window of the image processor and various correlation verifications among the instruction emission windows to form a combined verification.
Therefore, in the method for verifying the correlation of the instruction provided by the embodiment of the invention, the correlation verification is relatively comprehensive.
In the method for verifying the correlation of the instruction provided by the embodiment of the invention, a plurality of first verification programs, a plurality of second verification programs and a plurality of third verification programs are preset; each first verification program and each second verification program are composed of one or more excitation test programs selected from a plurality of preset excitation test programs; each third verification program is composed of at least one first verification program selected randomly and at least one second verification program selected randomly. And the sum of the numbers of the instructions contained in the excitation test program of any one of the first verification programs is not more than the number of the instruction emission indicated by the size of the instruction emission window of the graphic processor; the number of instructions included in the stimulus test program of any one of the second verification programs together with the sum of the numbers of instructions greater than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor may be used to verify a correlation for each of the stimulus test programs. Because each excitation test program contains a group of data-related, structure-related or control-related instructions, the correlation of one instruction can be verified, and therefore, various possible instruction-related conditions in an instruction emission window can be comprehensively verified by executing a plurality of preset first verification programs; by executing a plurality of preset second verification programs, various possible conditions related to the instruction among the instruction emission windows can be comprehensively verified; by executing a plurality of preset third verification programs, various possible instruction-related conditions caused by different instruction execution timings in and among the instruction emission windows can be comprehensively verified. Therefore, various conditions related to the instruction which are easy to appear in the graphic processor can be comprehensively known, so that the guiding value of the instruction correlation verification result for avoiding the conditions related to the instruction is improved.
Example two
For clarity of the scheme, the following exemplarily describes the construction manner of the preset first verification programs, second verification programs and third verification programs. As shown in fig. 3, the construction method may include the following steps:
step S301: and acquiring various reference information.
The plurality of reference information may include: the register read-write path of the graphics processor, the types of the various instruction execution units contained in the graphics processor, the number of each type of instruction execution units, the processing pipeline structure of each type of instruction execution units, the instruction execution period of each type of instruction execution units, and the read-write operation type of each type of instruction execution units read-write instructions.
In this step, there are various specific implementations of acquiring various reference information. For example, in one implementation, pre-written code for testing various configuration parameters of the graphics processor may be run to obtain test results; then, based on the test result, the above-described various reference information is determined. In another implementation, the various reference information may be obtained from a user manual of the graphics processor by means of manual acquisition.
Step S302: and respectively constructing a plurality of excitation test programs containing data-related instructions, a plurality of excitation test programs containing structure-related instructions and a plurality of excitation test programs containing control-related instructions by taking the acquired plurality of reference information as references.
Wherein, when constructing the stimulus test program containing the data-related instructions, the reference information as the reference may include: the instruction execution unit reads and writes the read-write operation type of the instruction, the flow processing structure of the instruction execution unit and the instruction execution period of the instruction execution unit. The read-write operation type of the instruction execution unit for reading and writing the instruction may include a type of several reads and several writes when the instruction execution unit reads and writes the register, which is not limited to this.
When constructing an excitation test program containing control-related instructions, the reference information as a reference may include: a processing pipeline structure of each instruction execution unit and an instruction execution cycle of each instruction execution unit.
In addition, to refine the type of correlation that the stimulus test program can verify, the stimulus test program containing instructions that are structurally related can be further subdivided into: an excitation test program including instructions associated with the instruction execution unit, and an excitation test program including instructions associated with the register read-write path.
Wherein, when constructing the stimulus test program containing the instructions related to the instruction execution unit, the reference information as the reference may include:
the graphics processor includes a variety of instruction execution units, a number of instruction execution units of each type, a processing pipeline of instruction execution units of each type, and an instruction execution cycle of instruction execution units of each type.
When constructing an excitation test program containing instructions related to a register read-write path, reference information as a reference may include:
the register read-write path of the graphics processor, the read-write operation type of each type of instruction execution unit read-write instruction, and the instruction execution period of each type of instruction execution unit.
In practical applications, with reference to the above-listed reference information, there are various specific implementations for constructing the corresponding excitation test program. For example, two or more instructions with the same operation type and pipeline processing structure and overlapping time periods in the instruction execution cycle can be constructed as an excitation test program containing data-related instructions; constructing two or more instructions with identical processing pipeline structures and overlapping time periods in the instruction execution period, and taking the two or more instructions as an excitation test program containing instructions related to control; constructing a plurality of instructions with the same instruction execution units and overlapping time periods in the instruction execution period as an excitation test program containing the instructions related to the instruction execution units; and constructing a plurality of instructions with the same register read-write path and overlapping time periods in the instruction execution cycle as an excitation test program containing the instructions related to the register read-write path.
It should be noted that the specific implementation of the excitation test procedure listed here is merely exemplary and should not be construed as limiting the embodiments of the invention.
Step S303: and constructing a plurality of first verification programs and a plurality of second verification programs according to the constructed plurality of stimulus test programs.
In this step, a plurality of first verification programs and a plurality of second verification programs are constructed according to the constructed plurality of stimulus test programs, and specifically, one or a plurality of stimulus test programs are selected from the constructed plurality of stimulus test programs each time to form a first verification program or a second verification program, so as to obtain a plurality of first verification programs and a plurality of second verification programs. When selecting, for each first verification program, the sum of the numbers of the instructions contained in the selected one or more excitation test programs is smaller than or equal to the number of instructions indicated by the size of an instruction emission window of the graphics processor; for each second validation program, the sum of the number of instructions contained by the selected one or more stimulus test programs is greater than the number of instructions indicated by the size of the instruction issue window of the graphics processor.
For clarity of the solution, the stimulus test program respectively included in the first verification programs, the second verification programs, and the third verification programs constructed in step S303 is illustrated below.
First, a plurality of first verification procedures constructed in step S303 are exemplified. As shown in fig. 4, the plurality of first verification procedures constructed in step S303 may include:
the first verification program a includes: stimulus test program 1 comprising a set of data-dependent instructions;
the first verification program B, the stimulus test program constituting the first verification program B includes: stimulus test program 2 comprising a set of structurally related instructions;
the first verification program C, the stimulus test program constituting the first verification program C includes: an excitation test program 3 containing a set of control-related instructions;
the first verification program D, the stimulus test program constituting the first verification program D includes: an excitation test program 4 comprising a set of data-dependent instructions and an excitation test program 5 comprising a set of structure-dependent instructions;
the first verification program E, the stimulus test program constituting the first verification program E includes: an excitation test program 6 comprising a set of structurally related instructions and an excitation test program 7 comprising a set of control related instructions;
The first verification program F, the stimulus test program constituting the first verification program F includes: an excitation test program 8 containing a set of data-dependent instructions and an excitation test program 9 containing a set of control-dependent instructions;
the first verification program G, the stimulus test program constituting the first verification program G includes: an excitation test program 10 comprising a set of data-dependent instructions, an excitation test program 11 comprising a set of control-dependent instructions, and an excitation test program 12 comprising a set of control-dependent instructions;
the first verification program H includes: the excitation test program 1 described above and the excitation test program 4 described above;
the first verification program I includes the excitation test program 6 described above and the excitation test program 9 described above.
It can be seen that the stimulus test program that verifies the same correlation in the different first verification programs may be the same or different. For the same situation, for example, the first verification program a and the first verification program H, both of which include the stimulus test program 1 that can verify the data correlation; for different cases, such as a first verification program E and a first verification program I, of which one is the stimulus test program 7 and the other is the stimulus test program 9, for verifying the control correlation.
Then, a plurality of second verification procedures constructed in step S303 are exemplified. As shown in fig. 4, the plurality of second verification procedures constructed in step S303 may include:
the second verification program J, the stimulus test program constituting the second verification program J includes: an excitation test program 13 containing a set of data-dependent instructions;
the second verification program K, the stimulus test program constituting the second verification program K includes: an excitation test program 14 containing a set of structurally related instructions;
the second verification program L, the stimulus test program constituting the second verification program L includes: an excitation test program 15 containing a set of control-related instructions;
the second verification program M, the stimulus test program constituting the second verification program M includes: the stimulus test program 13 described above and the stimulus test program 16 comprising a set of structurally related instructions;
the second verification program N, the stimulus test program constituting the second verification program N includes: the excitation test program 14 described above and the excitation test program 15 described above;
a second verification program O, the stimulus test program constituting the second verification program O including: the excitation test program 13 and the excitation test program 14;
The second verification program P includes: the excitation test program 13, the excitation test program 14, and the excitation test program 15.
It can be seen that the stimulus test program that verifies the same correlation in the second, different verification program can be the same or different. For the same case, for example, the second verification program J and the second verification program M, both of which include the stimulus test program 13 that can verify the correlation of data; for different cases, such as a second verification program K and a second verification program M, of which one is the excitation test program 14 and the other is the excitation test program 16, for verifying the structural correlation.
It should be understood that, in practical applications, the plurality of first verification procedures and the plurality of second verification procedures constructed in step S303 are not limited to the above-listed examples, but are not limited to the descriptions herein.
Step S304: and constructing a plurality of third verification programs according to the constructed plurality of first verification programs and the constructed plurality of second verification programs.
In this step, specifically, at least one first verification program and at least one second verification program may be randomly selected from the constructed plurality of first verification programs and the constructed plurality of second verification programs at a time to form a third verification program, thereby obtaining a plurality of third verification programs.
For example, as shown in fig. 4, the plurality of third verification procedures constructed in step S304 may include:
a third verification program Q composed of the first verification program a and the second verification program J;
a third verification program R composed of the first verification program B, the first verification program C, and the second verification program K;
and a third verification program S including the first verification program D, the second verification program L, and the second verification program M.
It should be understood that, since the third verification process constructed in step S304 is randomly constructed, the third verification process is exemplified herein only to illustrate the composition of the third verification process, and does not constitute a limitation on the number of the third verification processes. In practical applications, in order to more fully learn about various conditions related to instructions that easily occur in a graphics processor, program codes for randomly constructing the third verification program may be developed, so that a larger number of third verification programs are constructed. Of course, a plurality of third verification procedures may also be constructed by means of manual construction.
Optionally, in one implementation manner, as shown in fig. 5, before executing step S101, the method for verifying the correlation of the instruction provided by the embodiment of the present invention may further include:
step S100: judging whether the size of an instruction transmitting window of the graphic processor is larger than 1;
when the judgment result is yes, continuing to execute the step S101;
if the determination result is no, step S101 is skipped and step S102 is executed.
It can be understood that if the instruction emission window of the graphics processor has a size of 1, the instruction emission window of the graphics processor can only emit one instruction at a time, and there is no instruction-related situation in the instruction emission window, so step S102 is directly executed to verify the instruction-related situation between the instruction emission windows.
Alternatively, in one implementation, the instructions contained in each excitation test routine described above may be embodied as a stainer instruction.
The dyeing device is a module for realizing the functions of texture coordinate calculation, grating position calculation, illumination calculation and the like in the graphic processor.
Example III
Corresponding to the above method for verifying the correlation of the instruction, the embodiment of the invention further provides a device for verifying the correlation of the instruction, as shown in fig. 6, the device may include:
The first execution module 601 is configured to execute a plurality of preset first verification programs respectively, so as to obtain a first verification result; wherein any one of the first verification programs is composed of one or more excitation test programs selected from a plurality of preset excitation test programs; each excitation test program comprises a group of data-related, structure-related or control-related instructions, and the sum of the numbers of the instructions contained in the excitation test program forming any first verification program is not more than the number of instruction emission indicated by the size of an instruction emission window of the graphic processor;
the second execution module 602 is configured to execute a plurality of preset second verification procedures respectively, so as to obtain a second verification result; wherein any one of the second verification programs is composed of one or more excitation test programs selected from the plurality of excitation test programs, and the sum of the numbers of instructions contained in the excitation test programs composing any one of the second verification programs is larger than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor;
a third execution module 603, configured to execute a plurality of preset third verification procedures respectively, to obtain a third verification result; any one of the third verification programs is composed of at least one first verification program and at least one second verification program which are selected randomly.
Optionally, the second execution module 602 may specifically be configured to:
aiming at each second verification program, transmitting the instructions in the excitation test program contained in the second verification program into an instruction execution unit of the graphic processor in groups for execution according to the instruction transmission number indicated by the size of the instruction transmission window, and obtaining an execution result of each group of instructions;
and determining whether the instruction in the group of instructions and the instruction which does not execute the write-back operation in the previous group of instructions are related to verification information according to the execution result of the instructions in each group of instructions which are not the first group, obtaining a plurality of verification information, and taking the plurality of verification information as a second verification result.
Optionally, any of the excitation test procedures is a procedure constructed with at least one of a plurality of preset reference information as a reference;
wherein the plurality of reference information includes: the register read-write path of the graphics processor, the types of the various instruction execution units contained in the graphics processor, the number of each type of instruction execution units, the processing pipeline structure of each type of instruction execution units, the instruction execution period of each type of instruction execution units, and the read-write operation type of each type of instruction execution units read-write instructions.
Alternatively, when constructing an excitation test program containing data-dependent instructions, the reference information as a reference includes:
the instruction execution unit is used for reading and writing instructions, the type of read-write operation, the flow processing structure of the instruction execution unit and the instruction execution period of the instruction execution unit.
Optionally, the stimulus test program including the structurally related instructions comprises: an excitation test program containing instructions related to the instruction execution unit, and an excitation test program containing instructions related to the register read-write path;
wherein, when constructing the stimulus test program including the instruction related to the instruction execution unit, the reference information as the reference includes:
the graphics processor includes a variety of instruction execution units, a number of instruction execution units of each type, a processing pipeline structure of the instruction execution units of each type, and an instruction execution cycle of the instruction execution units of each type;
when constructing an excitation test program containing instructions related to a register read-write path, reference information as a reference includes:
the register read-write access of the graphic processor, the read-write operation type when each type of instruction execution unit reads and writes instructions, and the instruction execution period of each type of instruction execution unit.
Alternatively, when constructing an excitation test program containing control-related instructions, the reference information as a reference includes: a processing pipeline structure of each of the instruction execution units and an instruction execution cycle of each of the instruction execution units.
Optionally, the instruction is specifically a shader instruction in the graphics processor.
In the correlation verification device of the instruction provided by the embodiment of the invention, a plurality of first verification programs, a plurality of second verification programs and a plurality of third verification programs are preset; each first verification program and each second verification program are composed of one or more excitation test programs selected from a plurality of preset excitation test programs; each third verification program is composed of at least one first verification program selected randomly and at least one second verification program selected randomly. And the sum of the numbers of the instructions contained in the excitation test program of any one of the first verification programs is not more than the number of the instruction emission indicated by the size of the instruction emission window of the graphic processor; the number of instructions included in the stimulus test program of any one of the second verification programs together with the sum of the numbers of instructions greater than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor may be used to verify a correlation for each of the stimulus test programs. Because each excitation test program contains a group of data-related, structure-related or control-related instructions, one type of correlation can be verified, and therefore, various possible instruction-related conditions in an instruction emission window can be comprehensively verified by executing a plurality of preset first verification programs; by executing a plurality of preset second verification programs, various possible conditions related to the instruction among the instruction emission windows can be comprehensively verified; by executing a plurality of preset third verification programs, various possible instruction-related conditions caused by different instruction execution timings in and among the instruction emission windows can be comprehensively verified. Therefore, various conditions related to the instruction which are easy to appear in the graphic processor can be comprehensively known, so that the guiding value of the instruction correlation verification result for avoiding the conditions related to the instruction is improved.
Example IV
The embodiment of the present invention further provides an electronic device, as shown in fig. 7, including a processor 701, a communication interface 702, a memory 703 and a communication bus 704, where the processor 701, the communication interface 702, and the memory 703 perform communication with each other through the communication bus 704,
a memory 703 for storing a computer program;
the processor 701 is configured to implement any of the above-described methods for verifying the correlation of instructions when executing the program stored in the memory 703.
The communication bus mentioned above for the electronic devices may be a peripheral component interconnect standard (Peripheral Component Interconnect, PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, etc. The communication bus may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.
The communication interface is used for communication between the electronic device and other devices.
The Memory may include random access Memory (Random Access Memory, RAM) or may include Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the aforementioned processor.
The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; but also digital signal processors (Digital Signal Processing, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
The invention also provides a computer readable storage medium. The computer-readable storage medium stores a computer program which, when executed by a processor, implements the method for verifying the correlation of instructions according to any of the embodiments described above.
Alternatively, the computer readable storage medium may be a Non-Volatile Memory (NVM), such as at least one disk Memory.
Optionally, the computer readable memory may also be at least one memory device located remotely from the aforementioned processor.
In the embodiments of the present invention, the description is relatively simple, and the relevant points are only referred to in the description of the method embodiments, since the apparatus/electronic device/storage medium embodiments are basically similar to the method embodiments.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present specification, reference to the terms "embodiment," "example," or "particular implementation," etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
Although the present application has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (8)

1. A method for verifying relevance of instructions, the method being applied to an electronic device, the electronic device including a graphics processor, the method comprising:
respectively executing a plurality of preset first verification programs to obtain a first verification result; wherein any one of the first verification programs is composed of one or more excitation test programs selected from a plurality of preset excitation test programs; each excitation test program comprises a group of data-related, structure-related or control-related instructions, and the sum of the numbers of the instructions contained in the excitation test program forming any first verification program is not more than the number of instruction emission indicated by the size of an instruction emission window of the graphic processor;
respectively executing a plurality of preset second verification programs to obtain a second verification result; wherein any one of the second verification programs is composed of one or more excitation test programs selected from the plurality of excitation test programs, and the sum of the numbers of instructions contained in the excitation test programs composing any one of the second verification programs is larger than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor;
Respectively executing a plurality of preset third verification programs to obtain a third verification result; any one of the third verification programs is composed of at least one first verification program and at least one second verification program which are selected randomly;
the step of respectively executing a plurality of preset second verification programs to obtain a second verification result comprises the following steps:
aiming at each second verification program, transmitting the instructions in the excitation test program contained in the second verification program into an instruction execution unit of the graphic processor in groups for execution according to the instruction transmission number indicated by the size of the instruction transmission window, and obtaining an execution result of each group of instructions;
determining whether the instruction in the group of instructions and the instruction which does not execute the write-back operation in the previous group of instructions are related to verification information according to the execution result of the instructions in each group of instructions which are not the first group, obtaining a plurality of verification information, and taking the plurality of verification information as a second verification result;
any excitation test program is a program constructed by taking at least one of preset multiple reference information as a reference;
wherein the plurality of reference information includes: the register read-write path of the graphics processor, the types of the various instruction execution units contained in the graphics processor, the number of each type of instruction execution units, the processing pipeline structure of each type of instruction execution units, the instruction execution period of each type of instruction execution units, and the read-write operation type of each type of instruction execution units read-write instructions.
2. The method of claim 1, wherein the reference information as a reference when constructing the stimulus test program containing the data-dependent instructions comprises:
the instruction execution unit reads and writes the read-write operation type of the instruction, the flow processing structure of the instruction execution unit and the instruction execution period of the instruction execution unit.
3. The method of claim 2, wherein the stimulus test program including the structure-related instructions comprises: an excitation test program containing instructions related to the instruction execution unit, and an excitation test program containing instructions related to the register read-write path;
wherein, when constructing the stimulus test program including the instruction related to the instruction execution unit, the reference information as the reference includes:
the graphics processor includes a variety of instruction execution units, a number of instruction execution units of each type, a processing pipeline structure of the instruction execution units of each type, and an instruction execution cycle of the instruction execution units of each type;
when constructing an excitation test program containing instructions related to a register read-write path, reference information as a reference includes:
The register read-write channel of the graphic processor, the read-write operation type of each type of instruction execution unit read-write instruction and the instruction execution period of each type of instruction execution unit.
4. The method of claim 1, wherein the reference information as a reference when constructing the stimulus test program containing the control-related instructions includes: a processing pipeline structure of each instruction execution unit and an instruction execution cycle of each instruction execution unit.
5. The method according to any of claims 1-4, wherein the instruction is in particular a shader instruction in the graphics processor.
6. A correlation verification apparatus for instructions, the apparatus being applied to an electronic device, the electronic device including a graphics processor, the apparatus comprising:
the first execution module is used for respectively executing a plurality of preset first verification programs to obtain a first verification result; wherein any one of the first verification programs is composed of one or more excitation test programs selected from a plurality of preset excitation test programs; each excitation test program comprises a group of data-related, structure-related or control-related instructions, and the sum of the numbers of the instructions contained in the excitation test program forming any first verification program is not more than the number of instruction emission indicated by the size of an instruction emission window of the graphic processor;
The second execution module is used for respectively executing a plurality of preset second verification programs to obtain a second verification result; wherein any one of the second verification programs is composed of one or more excitation test programs selected from the plurality of excitation test programs, and the sum of the numbers of instructions contained in the excitation test programs composing any one of the second verification programs is larger than the number of instruction emissions indicated by the size of the instruction emission window of the graphics processor;
the third execution module is used for respectively executing a plurality of preset third verification programs to obtain a third verification result; any one of the third verification programs is composed of at least one first verification program and at least one second verification program which are selected randomly;
the step of respectively executing a plurality of preset second verification programs to obtain a second verification result comprises the following steps:
aiming at each second verification program, transmitting the instructions in the excitation test program contained in the second verification program into an instruction execution unit of the graphic processor in groups for execution according to the instruction transmission number indicated by the size of the instruction transmission window, and obtaining an execution result of each group of instructions;
Determining whether the instruction in the group of instructions and the instruction which does not execute the write-back operation in the previous group of instructions are related to verification information according to the execution result of the instructions in each group of instructions which are not the first group, obtaining a plurality of verification information, and taking the plurality of verification information as a second verification result;
any excitation test program is a program constructed by taking at least one of preset multiple reference information as a reference;
wherein the plurality of reference information includes: the register read-write path of the graphics processor, the types of the various instruction execution units contained in the graphics processor, the number of each type of instruction execution units, the processing pipeline structure of each type of instruction execution units, the instruction execution period of each type of instruction execution units, and the read-write operation type of each type of instruction execution units read-write instructions.
7. The electronic equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;
a memory for storing a computer program;
a processor for carrying out the method steps of any one of claims 1-4 when executing a program stored on a memory.
8. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored therein a computer program which, when executed by a processor, implements the method steps of any of claims 1-4.
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