CN111198310B - Data transmission link fault monitoring technology based on alternating current coupling LVDS standard - Google Patents

Data transmission link fault monitoring technology based on alternating current coupling LVDS standard Download PDF

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CN111198310B
CN111198310B CN202010031958.2A CN202010031958A CN111198310B CN 111198310 B CN111198310 B CN 111198310B CN 202010031958 A CN202010031958 A CN 202010031958A CN 111198310 B CN111198310 B CN 111198310B
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覃正才
肖宏
马祖飞
严成凡
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Hefei Xinxiang Microelectronics Co ltd
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Abstract

The invention discloses a data transmission link fault monitoring technology based on an alternating current coupling LVDS standard.A bias voltage establishing circuit of an input signal establishes a proper direct current bias working voltage for an alternating current coupling input data signal, then the input data signal is transmitted to a signal amplitude amplifying circuit to be amplified by a rated voltage gain, the amplified input data signal is further transmitted to a common mode adjusting circuit, the common mode adjusting circuit adjusts the common mode voltage of the amplified input data signal to a potential matched with an amplitude voltage threshold value, an amplitude differential comparison circuit compares the input data signal bit by bit, and finally the comparison result is subjected to low-pass filtering by an integrating circuit and then transmitted to a logic judgment integrating circuit to be judged; compared with the technical scheme based on envelope detection, the link fault monitoring technology has higher detection speed and has outstanding advantages in the aspects of reliability, judgment speed and application universality.

Description

Data transmission link fault monitoring technology based on alternating current coupling LVDS standard
Technical Field
The invention relates to a link fault monitoring technology, in particular to a data transmission link fault monitoring technology based on an alternating current coupling Low Voltage Differential Signaling (LVDS) standard, and belongs to the technical field of high-speed data transmission based on a Low Voltage Differential Signaling (LVDS) standard.
Background
With the increasing data transmission rate, high-speed data transmission using Low Voltage Differential Signaling (LVDS) technology is increasingly used in consumer electronics, high-speed computer peripherals, telecommunications/networks, automotive electronics, and other systems. The LVDS standard is a small-swing differential signal technology and has the advantages of high speed, low power consumption, low noise, small EMI (electro-magnetic interference), low cost and the like, so that the bottleneck problems of speed performance, performance and the like of high-speed data transmission are solved in a very wide application field; in the development of the technical industry, two LVDS standard specifications [1, 2] are currently formed: one is the ANSI/TIA/EIA-644 standard for TIA/EIA (telecommunication industry alliance/electronic industry alliance) as predominantly introduced by National semiconductor corporation of America (National semiconductor Corp.); the other is the IEEE1596.3 standard.
In a typical data transmission system based on the LVDS (Low Voltage Differential Signal) standard, the LVDS standard specification defines a fault detection mechanism to ensure the stability and reliability of the system operation. These fault mechanisms are based essentially on the dc characteristics of the signal, such as open, floating or short circuit. To avoid noise signals, the LVDS standard also defines the amplitude threshold of the LVDS signals to be ± 100 mV. Meanwhile, based on the LVDS standard, various application interface technologies, such as a mini-LVDS interface, an MIPI interface, and the like in the display module, are developed. Aiming at the application requirements of a new system, the development of a signal link fault monitoring circuit of the LVDS data transmission system with high reliability is of great significance. In particular, it is necessary to deeply study how to quickly and accurately monitor a link failure and remove a failure caused by deterioration of signal quality of a system for a data transmission rate up to Gbps.
In a data transmission system based on the LVDS standard, in order to ensure reliability and stability of the data transmission system, an LVDS receiver needs an internal or external fault detection circuit to monitor whether the system is in some special link condition or link fault state. Once the fault detection circuit monitors the abnormal link state, the receiver generates a fault state control signal to directly control the output signal of the LVDS receiving circuit, so as to ensure that the data output by the system is in a controllable logic state, usually a logic high level, and avoid the erroneous operation of the system.
The standards of the LVDS standard specification define the following three link failure states: input open, input float, input short. For the above faulty link states, in the past application process, three types of fault protection circuits have emerged: external bias circuits, in-path circuits, and parallel circuits.
The external bias fail safe circuit consists of three resistors externally connected to the receiver input pins, and in this design, a positive bias voltage is set between the two input pins to place the receiver output in a logic high state when the line is not being driven. The fault protection circuit has a simple structure and is widely used in early LVDS receivers. However, this method has many disadvantages, such as complicated resistance value design selection, increased number of system components, increased reception Bit Error Rate (BER), higher sensitivity requirement of the receiver, and ineffectiveness for input short-circuit failure.
The fail safe design in the signal path is similar to the external bias fail safe approach, but here R1 and R2 are integrated into the LVDS receiver, so the bias on the VID is now a built-in voltage source. The circuit is widely applied to some LVDS receivers; using the in-path circuit design, the resistance values of R1 and R2 are selected to have internal VID bias voltage values between 30mV and 50 mV. A positive VID bias is inserted even when the input is shorted, which causes the outputs to all be at a high level. This in-path design overcomes some of the disadvantages of external biasing methods such as the elimination of external resistors, operation when the input is shorted, etc. However, the method for protecting the fault in the path has the following limitations:
1. the flexibility of setting bias voltage is not provided in a wider working voltage range;
2. resulting in an unbalanced receiver threshold, degrading duty cycle performance, and increasing jitter;
3. lower "in path" noise margin;
4. due to poor matching between the external short-circuit resistor and the on-chip resistor, yield of the receiver during mass production is reduced.
The parallel fault protection circuit is applied to LVDS products of Maxim (Maxim) company, overcomes the main defects of the two fault protection circuits, but the parallel fault protection method also has the following limitations:
1. for point-to-point application of multi-point or Gbps data rate, the common mode load capacitance of the transmitter can be increased, and the fault protection function is added to increase the activation delay;
2. due to the influence of factors such as manufacturing process, temperature, power supply voltage range, power supply noise and the like, the comparative reference voltage of VCC-0.3V is difficult to accurately generate;
3. in order to realize noise suppression of the input signal, a hysteresis circuit is also required to be added in the receiving comparison circuit; the hysteresis circuit increases Inter-symbol interference (ISI) in the signal path, thereby increasing the receiver bit error rate.
Disclosure of Invention
The invention provides a data transmission link fault monitoring technology based on an alternating current coupling LVDS standard, and solves the problems in the prior art.
In order to solve the technical problems, the invention provides the following technical scheme:
the invention provides a data transmission link fault monitoring technology based on an alternating current coupling LVDS standard, which comprises an input signal bias voltage establishing circuit, a signal amplitude amplifying circuit, a reference generating circuit, a common mode adjusting circuit, an amplitude differential comparison circuit and a logic judgment integrating circuit, wherein the input signal bias voltage establishing circuit establishes proper direct current bias working voltage for an alternating current coupling input data signal, then transmits the input data signal to the signal amplitude amplifying circuit to be amplified by rated voltage gain, the signal amplitude amplifying circuit further transmits the amplified input data signal to the common mode adjusting circuit, the common mode adjusting circuit adjusts the common mode voltage of the amplified input data signal to a potential matched with an amplitude voltage threshold value, and the amplitude differential comparison circuit compares the input data signal bit by bit, and finally, integrating and low-pass filtering the comparison result and transmitting the result to a logic decision integrating circuit, wherein the logic decision integrating circuit decides according to the potential after integral filtering to generate high and low level signals.
As a preferred technical solution of the present invention, the reference generation circuit inputs an amplitude threshold to the signal amplitude amplification circuit, the reference generation circuit inputs an amplitude voltage threshold to the common mode adjustment circuit, and the reference generation circuit further inputs a comparison voltage threshold to the amplitude differential comparison circuit.
As a preferred technical solution of the present invention, in the amplitude differential comparison circuit, when the amplitude of the input data signal is greater than a reference amplitude voltage threshold, the comparison result of the amplitude differential comparison circuit is a square wave following the data polarity; the square wave pulse turns on a current source to charge a capacitor with the initial voltage set to zero potential; after the voltage on the capacitor reaches the set jump voltage of the rear-stage logic judgment integrating circuit after being charged by a plurality of pulses, the logic judgment integrating circuit outputs high level which represents that the amplitude of an input data signal is greater than a reference amplitude voltage threshold value; otherwise, the output of the logic decision integrating circuit keeps low level, which represents that the reference amplitude of the input data signal is smaller than the amplitude voltage threshold value, and the comparison result is low-pass filtered.
As a preferred technical solution of the present invention, in the signal amplitude amplifying circuit, a load of the amplifying circuit is composed of MP5A/R1A and MP5B/R1B, and an equivalent load thereof is:
Figure GDA0003528363490000041
the amplification gain is:
Figure GDA0003528363490000042
as a preferable aspect of the present invention, in the common mode adjusting circuit and the reference generating circuit, the signal V amplified by the preceding stageOP1/VON1Common mode regulation is realized by an amplification stage consisting of an MN7A/MN7B differential pair; a feedback loop consisting of the AMP-OP3, the MN10B and the R2A/R2B realizes the function of adjusting the output common-mode voltage of the amplifier AMP 2; R2A/R2B by comparing output voltage VOP2/VON2Summing to obtain the common-mode voltage value VCMFB(ii) a AMP2 output voltage is:
Vop2＝VCMREF+VA*α (3)
wherein, VAIs the amplitude of the LVDS input signal, and α is the output node V from the input stage to AMP2OP2The magnification factor of (2);
at the same time, for V generated by band-gap reference sourceBGA second-order feedback loop is formed by MN14, MN13A/MN13B, MP9A/MP9B, MP10 and R4\ R5\ R6, so that V isCMREFIs equal to VBG；
Signal amplitude reference voltage VSWTHThe resistance voltage-dividing network formed by R4 and R5 is that:
Figure GDA0003528363490000051
in a preferred embodiment of the present invention, the non-inverting input of the differential comparator circuit is the non-inverting output voltage V of AMP2OP2The input of the reverse end of the differential comparison circuit is a signal amplitude reference voltage VSWTHThe amplitude difference comparison circuit is composed of MN15A/MN15B, MN16A/MN16B, MN17, MP122A/MP11B and MP12A/MP12B, and the comparison result is as follows:
Figure GDA0003528363490000052
the invention has the following beneficial effects: compared with the prior art, the data transmission link fault monitoring technology based on the alternating current coupling LVDS standard has the following beneficial effects:
1. the link fault monitoring technology for VDS technology data transmission has smaller influence by factors such as manufacturing process deviation, temperature change, power supply voltage fluctuation and LVDS input signal common-mode voltage change, has high reliability, has higher detection speed compared with the technical scheme based on envelope detection, can complete monitoring judgment within more than ten times of UI (Unit interval), and is particularly suitable for systems needing quick response; therefore, the invention has outstanding advantages in reliability, decision speed and application universality.
2. The circuit provided by the link fault monitoring technology for VDS technology data transmission can realize accurate comparison of signal amplitude, and the comparison result is used for controlling a current source consisting of MP20A/MP20B and MP21B to charge a capacitor C, so that a low-pass filtering function is realized, and the comparison result is more reliable. Meanwhile, a Schmidt inverter with hysteresis voltage is adopted to avoid judgment noise, and the influence of power supply noise and a judgment device with process deviation on judgment voltage can be prevented.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a functional structure diagram of a data transmission link fault monitoring technique based on the ac-coupled LVDS standard according to the present invention;
fig. 2 is a schematic diagram of a signal amplitude amplifying circuit structure of rail-to-rail constant transconductance of a data transmission link fault monitoring technology based on the ac-coupled LVDS standard according to the present invention;
fig. 3 is a schematic diagram of a common mode adjustment circuit and an accurate signal amplitude reference voltage generation circuit of a data transmission link fault monitoring technology based on the ac-coupled LVDS standard according to the present invention;
FIG. 4 is a schematic diagram of an amplitude difference comparison circuit and a logic decision integrating circuit analysis circuit of a data transmission link fault monitoring technique based on an AC-coupled LVDS standard according to the present invention;
fig. 5 is a circuit functional sequence flow chart of a data transmission link fault monitoring technique based on the ac-coupled LVDS standard according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Example 1
As shown in fig. 1 and 5, the present invention provides a data transmission link fault monitoring technique based on the ac-coupled LVDS standard, which includes an Input Bias voltage Setting circuit (Input Bias Setting Circuits), a signal amplitude amplifying circuit (HS AMP Regulator), a Reference generating circuit (Reference Generator), a common mode adjusting circuit (HS CM Conditioner), an amplitude difference comparing circuit (Diff Comparator), and a logic decision integrating circuit (Slicer), wherein the Input Bias voltage Setting circuit sets up a suitable dc Bias operating voltage for an ac-coupled Input data signal, and then transmits the Input data signal to the signal amplitude amplifying circuit for amplification with a rated voltage gain, the signal amplitude amplifying circuit further transmits the amplified Input data signal to the common mode adjusting circuit, the common mode adjusting circuit adjusts the common mode voltage of the amplified Input data signal to a level matching an amplitude voltage threshold, the amplitude difference comparison circuit compares input data signals bit by bit, and finally, the comparison result is integrated, low-pass filtered and transmitted to the logic judgment integration circuit, and the logic judgment integration circuit judges according to the potential after the integration filtering to generate high and low level signals.
In the amplitude difference comparison circuit, when the amplitude of the input data signal is greater than a reference amplitude voltage threshold, the comparison result of the amplitude difference comparison circuit is a square wave following the data polarity; the square wave pulse turns on a current source to charge a capacitor with the initial voltage set to zero potential; after the voltage on the capacitor reaches the set jump voltage of the rear-stage logic judgment integrating circuit after being charged by a plurality of pulses, the logic judgment integrating circuit outputs high level which represents that the amplitude of the input data signal is greater than the reference amplitude voltage threshold; otherwise, the output of the logic decision integrating circuit keeps low level, which represents that the reference amplitude of the input data signal is smaller than the amplitude voltage threshold value, and the comparison result is low-pass filtered.
The reference generating circuit inputs an amplitude threshold value to the signal amplitude amplifying circuit, inputs an amplitude voltage threshold value to the common mode adjusting circuit, and inputs a comparison voltage threshold value to the amplitude differential comparison circuit.
Example 2
In order to realize the above scheme, three key indexes are ensured during circuit design: firstly, the gain consistency of input signals; secondly, the common mode matching of input signals at two ends of the comparator is realized; thirdly, the accuracy of the signal amplitude threshold voltage; as described in more detail in the following circuit architecture analysis and performance index design;
in the LVDS standard, the common mode range of the input signal is defined to be 0.05V-2.4V; in order to avoid the influence of the change of the input common-mode voltage on the gain, the invention adopts a rail-to-rail constant transconductance amplifier structure, the circuit schematic diagram is shown in figure 2, VIP/VINIs an LVDS differential input signal, VOP1/VON1Is the amplifier differential output signal; composed of MN1A/MN1B and MP1A/MP1B forms a complementary amplification stage, and is combined with a common-mode voltage following current automatic switching circuit formed by MN2, MN4A/MN4B, MP2 and MP4A/MP4B, so that the circuit has constant transconductance in the whole input common-mode voltage range; in order to reduce the influence of the process parameters on the amplification factor, the load of the amplifying circuit consists of MP5A/R1A and MP5B/R1B, and the equivalent load is as follows:
Figure GDA0003528363490000071
the amplification gain is:
Figure GDA0003528363490000081
as can be seen from equation (2), VBGIs a parameter that is weakly correlated with PTV, the deviation of the resistor R1 becomes weakly correlated with the cancellation of the transconductance and the load.
In order to realize that the input signals at two ends of the amplitude differential comparison circuit have good common-mode voltage matching, the circuit structure shown in fig. 3 is adopted; the circuit not only realizes the adjustment of the common-mode voltage of the input data signal and the smart matching with the signal amplitude voltage threshold, but also realizes the accurate generation function of the signal amplitude voltage threshold.
Signal V amplified by preceding stageOP1/VON1Common mode regulation is realized by an amplification stage consisting of an MN7A/MN7B differential pair; a feedback loop consisting of the AMP-OP3, the MN10B and the R2A/R2B realizes the function of adjusting the output common-mode voltage of the amplifier AMP 2; R2A/R2B by comparing output voltage VOP2/VON2Summing to obtain the common-mode voltage value VCMFB(ii) a The voltage and a common mode reference voltage VCMREFComparing if the common mode voltage V is outputCMFBReference voltage V of common modeCMREFHigh, AMP-OP3 output voltage VO3Will be controlled by raising the gate voltage V of MN8CGSCausing the tail current of AMP2 to increase, thereby reducing the AMP2 output voltage VOP2/VON2A common mode voltage of; vice versa, AMP2 outputs a voltage of:
Vop2＝VCMREF+VA*α (3)
wherein, VAIs the amplitude of the LVDS input signal, and α is the output node V from the input stage to AMP2OP2The magnification factor of (2);
at the same time, for V generated by band-gap reference sourceBGA second-order feedback loop is formed by MN14, MN13A/MN13B, MP9A/MP9B, MP10 and R4\ R5\ R6, so that V isCMREFIs equal to VBG；
Signal amplitude reference voltage VSWTHThe resistance voltage-dividing network formed by R4 and R5 is that:
Figure GDA0003528363490000082
from equation (4), it can be seen that the signal amplitude is referenced to the voltage VSWTHThe influence of PTV and other factors is small, the accuracy is high, and the accuracy can reach the order of magnitude of 100 ppm.
A schematic diagram of an amplitude difference Comparator circuit (Diff Comparator) and a logic decision integrator circuit (Slicer) is shown in FIG. 4. the non-inverting input of the difference Comparator circuit is the non-inverting output voltage V of AMP2OP2The input of the reverse end of the differential comparison circuit is a signal amplitude reference voltage VSWTHThe amplitude difference comparison circuit is composed of MN15A/MN15B, MN16A/MN16B, MN17, MP122A/MP11B and MP12A/MP12B, and the comparison result is as follows:
Figure GDA0003528363490000091
in equation (5), the gain α of the amplifier is small as seen from equation (2) with the variation in PTV; meanwhile, the ratio of the resistors in the integrated circuit can achieve high precision, and the precision can reach 0.1%, so that the second term in the equation (5) can also be achieved with high precision and is influenced very little by the PTV.
The circuit provided by the link fault monitoring technology for VDS technology data transmission can realize accurate comparison of signal amplitude, and the comparison result is used for controlling a current source consisting of MP20A/MP20B and MP21B to charge a capacitor C, so that a low-pass filtering function is realized, and the comparison result is more reliable; meanwhile, a Schmidt inverter with hysteresis voltage is adopted to avoid judgment noise and prevent the influence of power supply noise and a judgment device with process deviation on judgment voltage; the method has the advantages that the method is less influenced by factors such as manufacturing process deviation, temperature change, power voltage fluctuation and LVDS input signal common-mode voltage change, has high reliability, has higher detection speed compared with the technical scheme based on envelope detection, can finish monitoring and judgment within more than ten times of UI (Unit interval), and is particularly suitable for systems needing quick response; therefore, the invention has outstanding advantages in reliability, decision speed and application universality.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (6)

1. A data transmission link fault monitoring technology based on an alternating current coupling LVDS standard comprises an input signal bias voltage establishing circuit, a signal amplitude amplifying circuit, a reference generating circuit, a common mode adjusting circuit, an amplitude differential comparison circuit and a logic judgment integrating circuit, and is characterized in that the input signal bias voltage establishing circuit establishes proper direct current bias working voltage for an alternating current coupling input data signal, then the input data signal is transmitted to the signal amplitude amplifying circuit to be amplified by rated voltage gain, the signal amplitude amplifying circuit further transmits the amplified input data signal to the common mode adjusting circuit, the common mode adjusting circuit adjusts the common mode voltage of the amplified input data signal to a potential matched with an amplitude voltage threshold value, and the amplitude differential comparison circuit compares the input data signal bit by bit, and finally, integrating and low-pass filtering the comparison result and transmitting the result to a logic decision integrating circuit, wherein the logic decision integrating circuit decides according to the potential after integral filtering to generate high and low level signals.
2. The technology for monitoring the fault of the data transmission link based on the alternating-current coupled LVDS standard according to claim 1, wherein the reference generation circuit inputs an amplitude threshold to the signal amplitude amplification circuit, the reference generation circuit inputs an amplitude voltage threshold to the common mode adjustment circuit, and the reference generation circuit further inputs a comparison voltage threshold to the amplitude differential comparison circuit.
3. The technology for monitoring the fault of the data transmission link based on the alternating-current coupled LVDS standard according to claim 1, wherein in the amplitude differential comparison circuit, when the amplitude of the input data signal is larger than a reference amplitude voltage threshold, the comparison result of the amplitude differential comparison circuit is a square wave following the polarity of the data; the square wave pulse turns on a current source to charge a capacitor with the initial voltage set to zero potential; after the voltage on the capacitor reaches the set jump voltage of the rear-stage logic judgment integrating circuit after being charged by a plurality of pulses, the logic judgment integrating circuit outputs high level which represents that the amplitude of an input data signal is greater than a reference amplitude voltage threshold value; otherwise, the output of the logic decision integrating circuit keeps low level, which represents that the reference amplitude of the input data signal is smaller than the amplitude voltage threshold value, and the comparison result is low-pass filtered.
4. The technology for monitoring the fault of the data transmission link based on the alternating-current coupled LVDS standard as claimed in claim 1, wherein in the signal amplitude amplifying circuit, the load of the amplifying circuit is composed of MP5A/R1A and MP5B/R1B, and the equivalent loads are:
Figure FDA0003528363480000021
the amplification gain is:
Figure FDA0003528363480000022
。
5. the technique according to claim 1, wherein the pre-amplified signals V in the common mode adjusting circuit and the reference generating circuit are amplified by the pre-amplifier stageOP1/VON1Common mode regulation is realized by an amplification stage consisting of an MN7A/MN7B differential pair; a feedback loop consisting of the AMP-OP3, the MN10B and the R2A/R2B realizes the function of adjusting the output common-mode voltage of the amplifier AMP 2; R2A/R2B by comparing output voltage VOP2/VON2Summing to obtain the common-mode voltage value VCMFB(ii) a AMP2 output voltage is:
Vop2＝VCMREF+VA*α (3)
wherein, VAIs the amplitude of the LVDS input signal, and α is the output node V from the input stage to AMP2OP2The magnification factor of (2);
at the same time, for V generated by band-gap reference sourceBGA second-order feedback loop is formed by MN14, MN13A/MN13B, MP9A/MP9B, MP10 and R4\ R5\ R6, so that V isCMREFIs equal to VBG；
Signal amplitude reference voltage VSWTHThe resistance voltage-dividing network formed by R4 and R5 is that:
Figure FDA0003528363480000023
。
6. the technology for monitoring the fault of the data transmission link based on the AC-coupled LVDS standard as claimed in claim 1, wherein the non-inverting input of the differential comparison circuit is the non-inverting output voltage V of AMP2OP2Inverting terminal of differential comparison circuitInput is signal amplitude reference voltage VSWTHThe amplitude difference comparison circuit is composed of MN15A/MN15B, MN16A/MN16B, MN17, MP122A/MP11B and MP12A/MP12B, and the comparison result is as follows:
Figure FDA0003528363480000024
。
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