CN111193875A - High-definition digital image transmission system receiving end of traversing machine - Google Patents
High-definition digital image transmission system receiving end of traversing machine Download PDFInfo
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- CN111193875A CN111193875A CN201811360351.8A CN201811360351A CN111193875A CN 111193875 A CN111193875 A CN 111193875A CN 201811360351 A CN201811360351 A CN 201811360351A CN 111193875 A CN111193875 A CN 111193875A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
- H04N7/181—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast for receiving images from a plurality of remote sources
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
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Abstract
The invention discloses a high-definition digital image transmission system receiving end of a traversing machine, which comprises a wireless module, a mainboard unit, a wireless forwarding module and a mobile end, wherein the wireless module comprises a power amplifier PA unit, an impedance matching circuit, a radio frequency demodulation module, an RJ45 interface A and a power interface A, and the mainboard unit comprises an RJ45 interface B, a data unpacking module, a data decoding module, an HDMI interface circuit, a main power input module, a power interface B, a power interface C and a USB interface A. The high-definition digital image transmission system receiving end of the traversing machine provided by the invention has the following advantages: as many as 15 playing devices can run simultaneously, the transmission distance is increased, and the first-person visual angle in the true sense can be recorded; the social platform is convenient to publish the game video, the real first-person visual angle can be simply published through mobile devices such as a mobile phone, the cost is reduced, the controllability is improved, the real picture can be quickly transmitted to the player, and valuable decision-making time is provided for the player.
Description
Technical Field
The invention relates to the technical field of image transmission systems, in particular to a high-definition digital image transmission system receiving end of a traversing machine.
Background
The image transmission technology is widely applied to activities such as large-scale exhibition and competition, but has the following defects:
1. poor image quality: the image is an analog signal, the pixel is equivalent to 320P image quality, the picture seen by the players is fuzzy, each information is too little, and the snowflake pattern is often seen, which affects the game.
2. Picture series circuit: the phenomenon that pictures of two devices are mutually connected in the same field when more than 2 devices are transmitted by the simulation picture can affect the match. Or the match can only be played by players in turn, and the players cannot compete on the same game.
3. The distance is short: too short a transmission distance results in the inability to arrange complex and large game content.
4. The true first perspective cannot be stored: for storage, a sports camera with a high outlook price is required for recording, but it is not the first perspective of the real player. The picture quality, the visual angle and the like are different from the visual angle of the player; the cost is high, the video is inconsistent with the first visual angle, the video is complicated to release, and the controllability of players is influenced.
5. Video publishing on the social platform is cumbersome: high-cost moving cameras need to be erected, and cameras need to be dismantled, copied to a computer, edited and uploaded and the like in video release. In addition, the motion camera may affect the weight of the aircraft and thus the performance of the contestants.
6. Low time delay: the delay is the same as the transmission delay of the simulation diagram, but the simulation diagram transmission has the problem of the point 5; the transmission delay of the existing digital image is too high, and the existing digital image cannot be applied to a traversing machine.
Based on the defects, a high-definition digital image transmission system receiving end of the traversing machine is provided.
Disclosure of Invention
In order to solve the problems in the prior art, the invention aims to provide a high-definition digital image transmission system receiving end of a traversing machine, wherein up to 15 playing devices can run simultaneously, the transmission distance is increased, a first-person visual angle in a real sense can be recorded, a social platform can conveniently release a match video, the real first-person visual angle can be simply released through mobile devices such as mobile phones, the cost is reduced, the controllability is increased, a real picture can be quickly transmitted to players, precious decision time is provided for the players, and the problems that the picture quality is poor, the picture series is short, the transmission distance is short, the real first visual angle cannot be stored, the video release of the social platform is complicated and the time delay is high in the background technology are solved.
In order to achieve the purpose, the invention provides the following technical scheme: a receiving end of a high-definition digital image transmission system of a traversing machine comprises a wireless module, a mainboard unit, a wireless forwarding module and a mobile end, wherein the wireless module comprises a power amplifier PA unit, an impedance matching circuit, a radio frequency demodulation module, an RJ45 interface A and a power interface A, the mainboard unit comprises an RJ45 interface B, a data unpacking module, a data decoding module, an HDMI interface circuit, a main power input module, a power interface B, a power interface C and a USB interface A, the wireless forwarding module comprises a power interface D and a USB interface B, the power amplifier PA unit, the impedance matching circuit, the radio frequency demodulation module and the RJ45 interface A are electrically connected in sequence, the wireless module and the mainboard unit are connected through the RJ45 interface A and the RJ45 interface B, the RJ45 interface B, the data unpacking module, the data decoding module and the HDMI interface circuit are electrically connected in sequence, the power interface B and the power interface C, the power supply interface C is connected with the power supply interface A to supply power for the wireless module, the power supply interface B is connected with the power supply interface D to supply power for the wireless forwarding module, and the mainboard unit and the wireless forwarding module are connected through the USB interface A and the USB interface B to transmit data.
Preferably, a wireless module power supply circuit is arranged in the power interface a, the wireless module power supply circuit comprises a chip U30 and a chip U32, a pin 2 of the chip U30 is connected in series with a capacitor C212 and grounded, an input end of the capacitor C212 is connected with a VCC _ SYS output terminal of the chip U29, a pin 5 of the chip U30 is sequentially connected in series with a resistor R192, a capacitor C208, an inductor L10 and a capacitor C211 and grounded, an input end of the capacitor C211 is connected in series with a voltage regulator D6 and connected with a VCC _5V power output end, and a pin 3 of the chip U30 is connected with an output end of the capacitor C; pin 2 of the chip U32 is serially connected with a capacitor C227 to be grounded, the input end of the capacitor C227 is connected with a VCC _ SYS output terminal of the chip U29, pin 5 of the chip U32 is serially connected with a resistor R206, a capacitor C219, an inductor L11 and a capacitor C222 to be grounded, and the input end of the capacitor C222 is connected with a VCC _3V3 power output end.
Preferably, the HDMI interface circuit includes a chip U1O and a chip J2, pins 1 to 4 of the chip J2 are sequentially connected to a pin AG22, a pin AG21, a pin AH22 and a pin AH21 of the chip U1O, pin 7 of the chip J2 is connected to a pin AG20 of the chip U1O, pin 9 of the chip J2 is connected to a pin AH20 of the chip U1O, pin 10 of the chip J2 is connected to a pin AG19 of the chip U1O, pin 12 of the chip J2 is connected to a pin AH19 of the chip U1O, pin 15 of the chip J2 is connected to pin 3 of Q1, pin 2 of the thyristor Q1 is connected to an I2C5_ SCL terminal, pin 1 of the thyristor Q1 is connected to pin R130 2, and the input end of the resistor R130 is connected to a VCC _ IO port; pin 16 of the chip J2 is connected with pin 3 of the thyristor Q2, pin 2 of the thyristor Q2 is connected with the I2C5_ SDA terminal, pin 1 of the thyristor Q2 is connected with pin 2 of the resistor R132, and the input end of the resistor R132 is connected with the VCC _ IO port.
Preferably, the HDMI interface circuit is externally connected with a CPU end EMMC interface circuit, an EMMC chip peripheral interface circuit, a DDR related circuit, and a CPU ethernet interface, the CPU end EMMC interface circuit includes a main chip CPU, interfaces FLASH _ D0-FLASH _ D7 of the main chip CPU are data reading buses, an EMMC _ PWREN interface of the main chip CPU is an EMMC module power-on enable control line, an EMMC _ CLK0 interface is an EMMC communication clock line, and an EMMC _ CMD interface is a command neutral line for controlling the EMMC; the peripheral interface of the EMMC chip comprises a chip U12, pins (DATA 0-DATA 7) of the chip U12 are respectively connected with interfaces FLASH _ D0-FLASH _ D7 of a main chip CPU, a pin CMD of the chip U12 is connected with an EMMC _ CMD interface of the main chip CPU, a pin RST _ N of the chip U12 is connected with an EMMC _ PWREN interface of the main chip CPU, and a pin CLK of the chip U12 is connected with a main chip CPMMC UECLK 0 interface; the DDR related circuit comprises a chip U1K and a chip U1L, a pin H14 of the chip U1K is connected with a VCC _ DDR terminal, the VCC _ DDR terminal is connected with a capacitor C247 in series and is grounded, and two ends of the capacitor C247 are sequentially connected with a capacitor C248 and a capacitor C249 in parallel; a pin H12 of a chip U1K is connected with a VREF-DDR0 terminal, a VREF-DDR0 terminal is connected with a capacitor C255 in series and grounded, two ends of the capacitor C255 are connected with a resistor R238 in parallel, an input end of the resistor R238 is connected with a resistor R236 and a VCC-DDR terminal, a pin H11 of the chip U1K is connected with a VREFAO-DDR0 terminal, a VREFAO-DDR0 terminal is connected with a capacitor C260 in series and grounded, two ends of the capacitor C260 are sequentially connected with a capacitor C259 and a resistor R242 in parallel, an input end of the resistor R242 is connected with a resistor R240 and a VCC-DDR terminal, and two ends of the resistor; the CPU Ethernet interface comprises a chip U1Q, a chip U18 and a chip U18, a pin AD 18 of the chip U1 18 is connected with a resistor R18 in series to be connected with a pin 23 of the chip U18, a pin AB 18 of the chip U1 18 is connected with a resistor R18 in series to be connected with a pin 24 of the chip U18, a pin Y18 of the chip U1 18 is connected with a pin 25 of the chip U18 in series to be connected with a resistor R18 in series to be connected with a pin 26 of the chip U18, a pin AA 18 of the chip U1 18 is connected with a resistor R18 in series to be connected with a pin 27 of the chip U18, a pin V18 of the chip U1 18 in series to be connected with a pin 16 of the chip U18, a pin AA 18 of the chip U1 18 in series to be connected with a resistor R18 in series to be connected with a pin 14 of the chip U18, a pin AA 18 of the chip U1 18 in series to be connected with a pin 72, a pin AA 18 of the chip U18, a pin AA 18 of the chip U1 and a pin 18 to be connected with a resistor R365, a pin 365 of the chip U6, a pin 18 and a pin 18 to be connected with a pin 365, a pin 365 of the chip U6, a pin 18 to be connected with a pin 365 and a pin 368 to, pin 1 and pin 2 of chip U19 are connected to pin 11 and pin 12 of chip U18, respectively.
Preferably, the front power supply circuit is built in the main power supply input module, the front power supply circuit includes a chip U29, pin 2 of the chip U29 is connected in series with a capacitor C206 and grounded, the input end of the capacitor C206 is connected with a VCC _ SYSIN power supply terminal, pin 7 of the chip U29 is connected in series with a capacitor C207 and grounded, pin 1 of the chip U29 is connected with the input end of a series resistor R185 and grounded, pin 5 of the chip U29 is connected in series with a resistor R182, a capacitor C202 and an inductor L9 in sequence and connected with a VCC _ SYS output terminal, pin 3 of the chip U29 is connected with the output end of the capacitor C202, pin 8 of the chip U29 is connected in series with a resistor R186 and a capacitor C203 and connected with the output end of an inductor L9, the output end of the inductor L9 is connected with a resistor R184 and a.
Preferably, the power interface B is internally provided with a power controller control circuit, the power controller control circuit includes a chip U1D, a pin M27 of the chip U1D is connected in series with a capacitor C28 and grounded, a pin P25 of the chip U1D is connected in series with a capacitor C29 and grounded, a pin P28 of the chip U1D is connected with a VDD _10 terminal, and a pin M25 of the chip U1D is connected with an I2C0_ SDA _ PMIC terminal; the chip U29 is connected with a clock circuit, the clock circuit comprises a clock chip Y1, a pin 1 series resistor R2 of a clock chip Y1 is connected with a pin N28 of the chip U29, a pin 4 series resistor R3 of the clock chip Y1 is grounded, an input end of a resistor R3 is connected with an input end of a resistor R2 in series with a capacitor C31, a pin 3 of the clock chip Y1 is connected with a pin N27 of the chip U29, and a pin 2 series capacitor C30 of the clock chip Y1 is connected with a pin N27 of the chip U29 in series with the capacitor C30.
Preferably, the power interface C is internally provided with a main board CPU main power circuit, the main board CPU main power circuit includes a chip U1 and a chip U1, pins (U-U) and (V-V) of the chip U1 are connected to a VDD _ CPU terminal, the VDD _ CPU terminal is connected in series to a capacitor C, two ends of the capacitor C are sequentially connected in parallel to a capacitor C, a capacitor C and a capacitor C, pins (L-L), pins (M-M) and (N-N) of the chip U1 are connected to a VDD _ GPU terminal, the VDD _ GPU terminal is connected in series to a capacitor C ground, two ends of the capacitor C are sequentially connected in parallel to a capacitor C, a capacitor C and a capacitor C, a pin V of the chip U1 is connected to a VCC _ LCD terminal, the VCC _ LCD terminal is connected in series to a capacitor C ground, a pin T of the chip U1 is connected to a VDD _ LOG terminal, the VDD _ LOG terminal is.
Preferably, the power interface D is internally provided with a power main chip PMU working circuit, which includes a chip U6, a chip U7 and a chip U8, a pin 13, a pin 14, a pin 18, a pin 25, a pin 30, a pin 41, a pin 47 and a pin 48 of the chip U6 are all connected to a VCC _ SYS output terminal of the chip U29, a pin 28 of the chip U6 is connected in series to an inductor L1 to be connected to a VCC-DDR terminal, a pin 26 of the chip U6 is connected in series to an inductor L4 to be connected to a VCC-20 terminal, a pin 11 of the chip U6 is connected in series to an inductor L2 to be connected to a VCC-IO terminal, a pin 1 of the chip U6 is connected in series to an inductor L5 to be connected to a VCC-LOG terminal, a pin 40 of the chip U6 is connected in series to a capacitor C106 to be grounded, an input terminal of the capacitor C106 is connected to a VCC10_ LCD terminal, a pin 7 of the chip; a pin D1 of the chip U7 is connected with a capacitor C94 in series and grounded, the input end of the capacitor C94 is connected with a VCC _ SYS output terminal of the chip U29, a terminal D3 of the chip U7 is connected with an inductor L3 and a capacitor C96 in series and grounded, the input end of the capacitor C96 is connected with a VDD _ CPU terminal, a terminal A2 of the chip U7 is connected with a capacitor C99 in series and grounded, and the input end of the capacitor C99 is connected with a VCC _ DDR terminal; the pin D1 of the chip U8 is connected in series with a capacitor C112 and grounded, the input end of the capacitor C112 is connected with a VCC _ SYS output terminal of the chip U29, the pin D3 of the chip U8 is connected in series with an inductor L6 and a capacitor C114 and grounded, the input end of the capacitor C114 is connected with a VDD _ GPU terminal, the terminal A2 of the chip U8 is connected in series with a capacitor C119 and grounded, and the input end of the capacitor C119 is connected with a VCC _ DDR terminal.
Preferably, the USB interface circuit built in the USB interface B includes a pin J25, a pin 1 of the pin J25 is connected in series with a magnetic bead LB18 to connect to a 5V0_ WL terminal, an input terminal of the magnetic bead LB18 is connected to ground via a capacitor C434, a pin 2 of the magnetic bead LB18 is connected to a USB _ DM terminal, and a pin 3 of the magnetic bead LB18 is connected to a USB _ DP terminal.
Preferably, the mobile terminal adopts a mobile phone or a tablet personal computer, corresponding APP software is installed, the video data can be obtained through the mobile phone forwarding module, the first-person video of the player can be watched in real time after the video data is obtained, and meanwhile, the video can be selectively recorded to the mobile phone.
Compared with the prior art, the invention has the beneficial effects that: the high-definition digital image transmission system receiving end of the traversing machine provided by the invention has the following advantages: 1. by adopting digital signal transmission, high-definition digital images can be provided; 2. the device can realize simultaneous operation of up to 15 devices in the same site, thereby avoiding image series in multiple devices in the same site; 3. the distance is increased from 150 meters to 450 meters, so that more complex and huge game contents can be held conveniently; 4. on the premise of not increasing the user cost, video storage is realized, and the first-person visual angle in the real sense is recorded; 5. the social platform is convenient to publish the game video, so that the real first-person view angle can be published simply through mobile equipment such as a mobile phone; 6. the cost is reduced, and an additional motion camera which is added for video storage and social contact is omitted; 7. the controllability is improved, the weight of an additional motion camera is saved, the weight of the airplane is reduced, and the controllability of players is improved; 8. the high-definition low-delay time reduces the delay time for high-definition image transmission, so that the plane is really a picture which can be transmitted to players more quickly, and valuable decision time is provided for the players.
Drawings
FIG. 1 is a functional block diagram of the present invention;
FIG. 2 is a power supply circuit diagram of the wireless module of the present invention;
FIG. 3 is a schematic diagram of an HDMI interface circuit according to the present invention;
FIG. 4 is a circuit diagram of the level shift circuit of the present invention;
FIG. 5 is a circuit diagram of the CPU EMMC interface of the present invention;
FIG. 6 is a circuit diagram of the peripheral interface of the EMMC chip of the present invention;
FIG. 7 is a diagram of a DDR related circuit of the invention;
FIG. 8 is a circuit diagram of a CPU Ethernet interface of the present invention;
FIG. 9 is a circuit diagram of a front stage power supply of the present invention;
FIG. 10 is a control circuit diagram of the power supply controller of the present invention;
FIG. 11 is a main power circuit diagram of the main board CPU of the present invention;
FIG. 12 is a diagram of the power main chip PMU operating circuit of the present invention;
FIG. 13 is a circuit diagram of a USB interface according to the present invention;
fig. 14 is a schematic diagram of the operation of the wireless module of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-14, a receiving end of a high-definition digital image transmission system of a pass-through machine comprises a wireless module, a main board unit, a wireless forwarding module and a mobile end, wherein the wireless module comprises a power amplifier PA unit, an impedance matching circuit, a radio frequency demodulation module, an RJ45 interface a and a power interface a, the main board unit comprises an RJ45 interface B, a data unpacking module, a data decoding module, an HDMI interface circuit, a main power input module, a power interface B, a power interface C and a USB interface a, the wireless forwarding module comprises a power interface D and a USB interface B, the power amplifier PA unit, the impedance matching circuit, the radio frequency demodulation module and the RJ45 interface a are electrically connected in sequence, the wireless module and the main board unit are connected through the RJ45 interface a and the RJ45 interface B, the RJ45 interface B, the data unpacking module, the data decoding module and the HDMI interface circuit are electrically connected in sequence, the power interface, the power supply interface C is connected with the power supply interface A to supply power for the wireless module, the power supply interface B is connected with the power supply interface D to supply power for the wireless forwarding module, and the mainboard unit and the wireless forwarding module are connected through the USB interface A and the USB interface B to transmit data.
A wireless module power supply circuit is arranged in the power interface A and comprises a chip U30 and a chip U32, a pin 2 of the chip U30 is connected in series with a capacitor C212 to be grounded, the input end of the capacitor C212 is connected with a VCC _ SYS output terminal of the chip U29, a pin 5 of the chip U30 is sequentially connected in series with a resistor R192, a capacitor C208, an inductor L10 and a capacitor C211 to be grounded, the input end of the capacitor C211 is connected in series with a voltage regulator tube D6 to be connected with a VCC _5V power output end, and a pin 3 of the chip U30 is connected with the output end of the capacitor C; pin 2 of the chip U32 is serially connected with a capacitor C227 to be grounded, the input end of the capacitor C227 is connected with a VCC _ SYS output terminal of the chip U29, pin 5 of the chip U32 is serially connected with a resistor R206, a capacitor C219, an inductor L11 and a capacitor C222 to be grounded, and the input end of the capacitor C222 is connected with a VCC _3V3 power output end; the wireless module power supply circuit is divided into two parts of circuits, wherein a circuit where the chip U30 is located converts an input power supply into VCC _5V output, a circuit where the chip U32 is located converts the input power supply into VCC _3V3 output, the two parts of power supplies are both supplied by the radio frequency demodulation module, and because the requirement on power supply capacity is high, two independent power supplies are adopted for supplying power; at the working end, the impedance matching circuit is used for matching the radio frequency demodulation module and the power amplifier PA unit, because the output power of the radio frequency demodulation module is a bit higher for the power amplifier PA unit, the radio frequency demodulation module needs to be subjected to signal attenuation, the radio frequency signal is subjected to signal attenuation through the resistance-capacitance resistor, and simultaneously, in order to achieve good signal amplification, impedance matching is carried out on the radio frequency signal in the attenuation process, impedance matching and filtering are carried out on double-transmitting and double-receiving circuits, so that the impedance matching in the attenuation process is realized by adopting a pi-type circuit, and impedance matching and filtering are carried out on the double-transmitting and double-receiving circuits; a power amplifier PA unit: the digital radio frequency signal processed by the impedance matching circuit is amplified, so that the power of the original radio frequency unit is increased from 25mw to 800mw, the receiving capacity is enhanced to increase the transmission distance, the transmission distance is increased from 150 meters to 450 meters, and more complex and huge game contents can be conveniently held; during receiving, radio frequency signals are obtained through the antenna, the radio frequency signals pass through the power amplifier PA unit and the impedance matching circuit and then reach the adjusting unit, the digital signals are demodulated through the demodulator to obtain video data, and the video data are transmitted to the main board unit through the RJ45 interface A and the RJ45 interface B.
The HDMI interface circuit comprises a chip U1O and a chip J2, wherein pins 1 to 4 of the chip J2 are sequentially connected with a pin AG22, a pin AG21, a pin AH22 and a pin AH21 of the chip U1O, a pin 7 of the chip J2 is connected with a pin AG20 of the chip U1O, a pin 9 of the chip J2 is connected with a pin AH20 of the chip U1O, a pin 10 of the chip J2 is connected with a pin AG19 of the chip U1O, a pin 12 of the chip J2 is connected with a pin AH19 of the chip U1O, a pin 15 of the chip J2 is connected with a pin 3 of a thyristor Q1, a pin 2 of the thyristor Q1 is connected with an I2C5_ SCL terminal, a pin 1 of the thyristor Q1 is connected with a pin R130, and the input end of the resistor R130 is connected with an; a pin 16 of the chip J2 is connected with a pin 3 of a thyristor Q2, a pin 2 of a thyristor Q2 is connected with an I2C5_ SDA terminal, a pin 1 of the thyristor Q2 is connected with a pin 2 of a resistor R132, and the input end of the resistor R132 is connected with a VCC _ IO port; the interface of the chip J2 is used for driving an external display device, the interface is defined by a TYPE-A interface, the HDMI interface acquires information such as the resolution of the display device by handshaking with the display device through a CPU, the function is completed by an I2C interface, and a level conversion circuit composed of a thyristor Q1 and a thyristor Q2 is used for carrying out level conversion on an I2C signal.
The HDMI interface circuit is externally connected with a CPU end EMMC interface circuit, an EMMC chip peripheral interface circuit, a DDR related circuit and a CPU Ethernet interface, the CPU end EMMC interface circuit comprises a main chip CPU, interfaces FLASH _ D0-FLASH _ D7 of the main chip CPU are data reading buses, an EMMC _ PWREN interface of the main chip CPU is an EMMC module power-on enabling control line, an EMMC _ CLK0 interface is an EMMC communication clock line, and an EMMC _ CMD interface is a command central line and is used for controlling the EMMC; the peripheral interface of the EMMC chip comprises a chip U12, pins (DATA 0-DATA 7) of the chip U12 are respectively connected with interfaces FLASH _ D0-FLASH _ D7 of a main chip CPU, a pin CMD of the chip U12 is connected with an EMMC _ CMD interface of the main chip CPU, a pin RST _ N of the chip U12 is connected with an EMMC _ PWREN interface of the main chip CPU, and a pin CLK of the chip U12 is connected with a main chip CPMMC UECLK 0 interface; the peripheral interface of the EMMC chip is powered by a VCC _ IO terminal, the chip U12 is an external fixed memory, the memory is not lost when power is down and can be used for storing firmware, a main chip CPU is powered on and then reads the firmware into a DDR through a chip U12, then the firmware is run in the DDR, interfaces FLASH _ D0-FLASH _ D7 are data reading buses, an EMMC _ PWREN interface of the main chip CPU is a power-on enabling control line of an EMMC module, an EMMC _ CLK0 interface is an EMMC communication clock line, and an EMMC _ CMD interface is a command center line and is used for controlling the EMMC; the DDR related circuit comprises a chip U1K and a chip U1L, a pin H14 of the chip U1K is connected with a VCC _ DDR terminal, the VCC _ DDR terminal is connected with a capacitor C247 in series and is grounded, and two ends of the capacitor C247 are sequentially connected with a capacitor C248 and a capacitor C249 in parallel; a pin H12 of a chip U1K is connected with a VREF-DDR0 terminal, a VREF-DDR0 terminal is connected with a capacitor C255 in series and grounded, two ends of the capacitor C255 are connected with a resistor R238 in parallel, an input end of the resistor R238 is connected with a resistor R236 and a VCC-DDR terminal, a pin H11 of the chip U1K is connected with a VREFAO-DDR0 terminal, a VREFAO-DDR0 terminal is connected with a capacitor C260 in series and grounded, two ends of the capacitor C260 are sequentially connected with a capacitor C259 and a resistor R242 in parallel, an input end of the resistor R242 is connected with a resistor R240 and a VCC-DDR terminal, and two ends of the resistor; the operation speed of the chip U1K is high, in order to improve the operation efficiency of a system, a system program in the chip U12 is copied into the chip U1K to operate after the system is started, so as to improve the operation efficiency of the system, wherein a pin H14 of the chip U1K is connected with a VCC _ DDR terminal to serve as an accessed power supply, a VREF-DDR0 terminal accessed by a pin H12 of the chip U1K and a VREFAO-DDR0 terminal accessed by a pin H11 of the chip U1K serve as a reference power supply, VCC _ DDR is obtained by a PMU module, and the VREF-DDR0 terminal and the VREFAO-DDR0 terminal filter and divide voltage of DDR _ through a resistance-capacitance circuit; due to the fact that the chip U1K is high in running speed and low in delay time, delay time is reduced for high-definition image transmission, real images of the airplane can be transmitted to players more quickly, precious decision-making time is provided for the players, cost is reduced, extra motion cameras are omitted for video storage and social contact, burden brought by the extra motion cameras is omitted while the extra motion cameras are omitted, airplane weight is reduced, and player controllability is improved; the CPU Ethernet interface comprises a chip U1Q, a chip U18 and a chip U18, a pin AD 18 of the chip U1 18 is connected with a resistor R18 in series to be connected with a pin 23 of the chip U18, a pin AB 18 of the chip U1 18 is connected with a resistor R18 in series to be connected with a pin 24 of the chip U18, a pin Y18 of the chip U1 18 is connected with a pin 25 of the chip U18 in series to be connected with a resistor R18 in series to be connected with a pin 26 of the chip U18, a pin AA 18 of the chip U1 18 is connected with a resistor R18 in series to be connected with a pin 27 of the chip U18, a pin V18 of the chip U1 18 in series to be connected with a pin 16 of the chip U18, a pin AA 18 of the chip U1 18 in series to be connected with a resistor R18 in series to be connected with a pin 14 of the chip U18, a pin AA 18 of the chip U1 18 in series to be connected with a pin 72, a pin AA 18 of the chip U18, a pin AA 18 of the chip U1 and a pin 18 to be connected with a resistor R365, a pin 365 of the chip U6, a pin 18 and a pin 18 to be connected with a pin 365, a pin 365 of the chip U6, a pin 18 to be connected with a pin 365 and a pin 368 to, pin 1 and pin 2 of chip U19 are connected to pin 11 and pin 12 of chip U18, respectively; the main board unit and the wireless communication module are communicated through a 100M Ethernet port, U1Q is an Ethernet interface part of a CPU, U19 is an Ethernet chip, impedance matching and isolation are performed between the CPU interface and the network chip through resistance connection, U18 is a network transformer, the wireless communication module and the main board unit are connected through U18, and U18 can play a role in isolation protection at the same time.
A front power supply circuit is arranged in the main power supply input module, the front power supply circuit comprises a chip U29, a pin 2 of the chip U29 is connected with a capacitor C206 in series and grounded, the input end of the capacitor C206 is connected with a VCC _ SYSIN power supply terminal, a pin 7 of the chip U29 is connected with a capacitor C207 in series and grounded, a pin 1 of the chip U29 is connected with a series resistor R185 and the input end of the capacitor C207, a pin 5 of the chip U29 is sequentially connected with a resistor R182, a capacitor C202 and an inductor L9 in series and connected with a VCC _ SYS output terminal, a pin 3 of the chip U29 is connected with the output end of the capacitor C202, a pin 8 of the chip U29 is connected with a resistor R186 and a capacitor C203 and the output end of an inductor L9, the output end of the inductor L9 is connected; the front-stage power supply circuit is connected with an external power supply for supplying power, converts the external power supply into a stable system input power supply and supplies power for the power supply main chip PMU unit and the wireless module power supply circuit.
A power supply controller control circuit is arranged in the power supply interface B and comprises a chip U1D, a pin M27 of the chip U1D is connected with a capacitor C28 in series and is grounded, a pin P25 of the chip U1D is connected with a capacitor C29 in series and is grounded, a pin P28 of the chip U1D is connected with a VDD _10 terminal, and a pin M25 of the chip U1D is connected with an I2C0_ SDA _ PMIC terminal; a clock circuit is connected to the chip U1D and comprises a clock chip Y1, a pin 1 serial resistor R2 of the clock chip Y1 is connected with a pin N28 of the chip U1D, a pin 4 of the clock chip Y1 is connected with a pin R3 in series and grounded, an input end of the resistor R3 is connected with an input end of a capacitor C31 in series and connected with an input end of the resistor R2, a pin 3 of the clock chip Y1 is connected with a pin N27 of the chip U1D, and a pin 2 of the clock chip Y1 is connected with a pin N27 of the chip U1D in series and connected with a capacitor C30 in; the power supply controller control circuit does not depend on the power supply state of the peripheral equipment, is controlled by the CPU, is called preferentially after power supply is started, is configured and controlled for the PMU (power supply main chip) through the I2C0 after being called, and configures module voltage and controls the power supply time sequence of each voltage according to instructions after the PMU receives commands.
A power interface C is internally provided with a mainboard CPU main power circuit, the mainboard CPU main power circuit comprises a chip U1 and a chip U1, pins (U-U) and pins (V-V) of the chip U1 are connected with a VDD _ CPU terminal, the VDD _ CPU terminal is connected with a capacitor C in series, two ends of the capacitor C are sequentially connected with a capacitor C, a capacitor C and a capacitor C in parallel, pins (L-L) and pins (M-M) and pins (N-N) of the chip U1 are connected with a VDD _ GPU terminal, the VDD _ GPU terminal is connected with a capacitor C in series and grounded, two ends of the capacitor C are sequentially connected with a capacitor C, a capacitor C and a capacitor C in parallel, a pin V of the chip U1 is connected with a VCC _ LCD terminal, the VCC _ LCD terminal is connected with a capacitor C in series and grounded, a pin T of the chip U1 is connected with a VDD _ LOG terminal; the peripheral units of the CPU can be selectively turned off or enabled, in order to reduce power consumption as much as possible, only the peripheral units used in the system are powered, for example, the CPU supplies power for the CPU main part through VDD _ CPU of the power module, and the VDD _ GPU supplies power for the GPU of the CPU, because the video display part needs to use the LCDC controller part, the module needs to be powered through VCC _ LCD, VDD _ LOG supplies power for the CPU logic processing unit, and ceramic capacitors are connected in parallel near each power access pin as much as possible to filter the input power, so that the peripheral units of the system work stably.
A power interface D is internally provided with a power main chip PMU working circuit, the power main chip PMU working circuit comprises a chip U6, a chip U7 and a chip U8, a pin 13, a pin 14, a pin 18, a pin 25, a pin 30, a pin 41, a pin 47 and a pin 48 of the chip U6 are all connected with a VCC _ SYS output terminal of the chip U29, a pin 28 of the chip U6 is connected with a series inductor L1 and a VCC-DDR terminal in series, a pin 26 of the chip U6 is connected with a series inductor L4 and a VCC-20 terminal in series, a pin 11 of the chip U6 is connected with a series inductor L2 and a VCC-IO terminal in series, a pin 1 of the chip U6 is connected with a series inductor L5 and a VCC-LOG terminal in series, a pin 40 of the chip U6 is connected with a capacitor C106 and grounded in series, an input VCC10_ LCD terminal of the capacitor C117 and a pin 7 of the chip U6 is; a pin D1 of a chip U7 is connected with a capacitor C94 in series and grounded, the input end of the capacitor C94 is connected with a VCC _ SYS output terminal of the chip U29, a terminal D3 of the chip U7 is connected with an inductor L3 and a capacitor C96 in series and grounded, the input end of a capacitor C96 is connected with a VDD _ CPU terminal, a terminal A2 of the chip U7 is connected with a capacitor C99 in series and grounded, and the input end of a capacitor C99 is connected with a VCC _ DDR terminal; a pin D1 of the chip U8 is connected with a capacitor C112 in series and grounded, the input end of the capacitor C112 is connected with a VCC _ SYS output terminal of the chip U29, a pin D3 of the chip U8 is connected with an inductor L6 and a capacitor C114 in series and grounded, the input end of the capacitor C114 is connected with a VDD _ GPU terminal, a pin A2 of the chip U8 is connected with a capacitor C119 in series and grounded, and the input end of the capacitor C119 is connected with a VCC _ DDR terminal; the power supply main chip PMU unit provides power for the work of the clock circuit, and because the module has higher requirement on power supply capacity, two independent power supplies are adopted for supplying power, the VCC _ SYSIN power supply terminal of the preceding stage power supply circuit is respectively connected with the pin 2 of the chip U30 and the chip U32, and respectively outputs a VCC _5V power supply and a VCC _3V3 power supply after voltage processing, thereby meeting the power supply requirement of the module.
A USB interface circuit is arranged in the USB interface B and comprises a pin J25, a pin 1 of the pin J25 is connected with a magnetic bead LB18 in series and connected with a 5V0_ WL terminal, the input end of the magnetic bead LB18 is connected with a capacitor C434 in a ground connection mode, a pin 2 of the magnetic bead LB18 is connected with a USB _ DM terminal, and a pin 3 of the magnetic bead LB18 is connected with a USB _ DP terminal; c434 is a power supply filter capacitor of the USB device, LB18 is a magnetic bead, and the power supply is subjected to high-frequency filtering by the circuit to eliminate high-frequency interference; the USB _ DM terminal and the USB _ DP terminal are USB data communication lines and are used for communicating with a wireless communication module of the USB interface.
The mobile terminal adopts a mobile phone or a tablet personal computer, and by installing corresponding APP software, video data can be acquired through a mobile phone forwarding module, and a first-person video of a player can be watched in real time after the video data is acquired, meanwhile, the video can be selectively recorded in the mobile phone, if necessary, the video can be conveniently and simply edited and uploaded through social platform software at the mobile phone end, the mobile end watches the first-person video in real time by adopting the mobile phone or a tablet personal computer, the data can be transmitted to a plurality of playing devices through a wireless network, up to 15 playing devices can simultaneously operate in the same place, the signal transmission form of wireless network transmission is adopted, the image series connection of a plurality of devices in the same place is avoided, meanwhile, the social platform such as a mobile phone and a tablet personal computer is convenient to use to publish the game video, so that the real first-person visual angle can be simply published through mobile equipment such as the mobile phone.
The power supply process of the high-definition digital image transmission system receiving end of the traversing machine is as follows: the front stage power circuit in the main power input module is connected with an external power supply for supplying power, the external power supply is converted into a stable system input power supply to supply power for a power controller control circuit arranged in a power interface B and a main board CPU main power circuit arranged in a power interface C, a wireless module power supply circuit arranged in the power interface A is connected with the main board CPU main power circuit for supplying power for the work of a wireless module, and the main board CPU main power circuit arranged in the power interface C supplies power for a power main chip PMU working circuit arranged in a power interface D; the working process is as follows: obtain radio frequency signal through the antenna, enter into radio frequency demodulation module behind power amplifier PA unit and impedance matching circuit, demodulate digital signal through the demodulator and obtain video data, video data exports for the mainboard unit through RJ45 interface A and RJ45 interface B, the RJ45 interface B of mainboard unit obtains the video data that the transmitting terminal sent, carry out data decoding again after the data unwrapping, parse data, convert data into the display data again, then drive HDMI interface circuit and outwards look the screen display, send this data to mobile terminal through wireless forwarding module through USB interface A and USB interface B simultaneously, play by mobile terminal's cell-phone and panel computer, release etc.
The whole has the following advantages:
1. by adopting digital signal transmission, high-definition digital images can be provided.
2. The same site can realize the simultaneous operation of up to 15 devices, thereby avoiding the occurrence of image series in multiple devices in the same site.
3. The distance is increased from 150 meters to 450 meters, so that more complex and huge game contents can be held conveniently.
4. On the premise of not increasing the user cost, the video storage is realized, and the first-person visual angle in the real sense is recorded.
5. The social platform is convenient to publish the game video, so that the real first-person view angle can be published simply through mobile devices such as a mobile phone.
6. The cost is reduced, and an additional motion camera added for video storage and social contact is omitted.
7. The controllability is improved, the weight of an additional motion camera is saved, the weight of the airplane is reduced, and the controllability of players is improved.
8. The high-definition low-delay time reduces the delay time for high-definition image transmission, so that the plane is really a picture which can be transmitted to players more quickly, and valuable decision time is provided for the players.
In summary, the high-definition digital image transmission system receiving end of the traversing device provided by the invention has the following advantages: 1. by adopting digital signal transmission, high-definition digital images can be provided; 2. the device can realize simultaneous operation of up to 15 devices in the same site, thereby avoiding image series in multiple devices in the same site; 3. the distance is increased from 150 meters to 450 meters, so that more complex and huge game contents can be held conveniently; 4. on the premise of not increasing the user cost, video storage is realized, and the first-person visual angle in the real sense is recorded; 5. the social platform is convenient to publish the game video, so that the real first-person view angle can be published simply through mobile equipment such as a mobile phone; 6. the cost is reduced, and an additional motion camera which is added for video storage and social contact is omitted; 7. the controllability is improved, the weight of an additional motion camera is saved, the weight of the airplane is reduced, and the controllability of players is improved; 8. the high-definition low-delay time reduces the delay time for high-definition image transmission, so that the plane is really a picture which can be transmitted to players more quickly, and valuable decision time is provided for the players.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (10)
1. A receiving end of a high-definition digital image transmission system of a traversing machine is characterized by comprising a wireless module, a mainboard unit, a wireless forwarding module and a mobile end, wherein the wireless module comprises a power amplifier PA unit, an impedance matching circuit, a radio frequency demodulation module, an RJ45 interface A and a power interface A, the mainboard unit comprises an RJ45 interface B, a data unpacking module, a data decoding module, an HDMI interface circuit, a main power input module, a power interface B, a power interface C and a USB interface A, the wireless forwarding module comprises a power interface D and a USB interface B, the power amplifier PA unit, the impedance matching circuit, the radio frequency demodulation module and the RJ45 interface A are electrically connected in sequence, the wireless module and the mainboard unit are connected through the RJ45 interface A and the RJ45 interface B, the RJ45 interface B, the data unpacking module, the data decoding module and the HDMI interface circuit are electrically connected in sequence, the power interface B and the power interface C are, the power supply interface C is connected with the power supply interface A to supply power for the wireless module, the power supply interface B is connected with the power supply interface D to supply power for the wireless forwarding module, and the mainboard unit and the wireless forwarding module are connected through the USB interface A and the USB interface B to transmit data.
2. The receiving end of a high-definition digital image transmission system of a traversing machine according to claim 1, wherein: a wireless module power supply circuit is arranged in the power interface A and comprises a chip U30 and a chip U32, a pin 2 of the chip U30 is connected in series with a capacitor C212 to be grounded, the input end of the capacitor C212 is connected with a VCC _ SYS output terminal of the chip U29, a pin 5 of the chip U30 is sequentially connected in series with a resistor R192, a capacitor C208, an inductor L10 and a capacitor C211 to be grounded, the input end of the capacitor C211 is connected in series with a voltage regulator tube D6 to be connected with a VCC _5V power output end, and a pin 3 of the chip U30 is connected with the output end of the capacitor C208; pin 2 of the chip U32 is serially connected with a capacitor C227 to be grounded, the input end of the capacitor C227 is connected with a VCC _ SYS output terminal of the chip U29, pin 5 of the chip U32 is serially connected with a resistor R206, a capacitor C219, an inductor L11 and a capacitor C222 to be grounded, and the input end of the capacitor C222 is connected with a VCC _3V3 power output end.
3. The receiving end of a high-definition digital image transmission system of a traversing machine according to claim 1, wherein: the HDMI interface circuit comprises a chip U1O and a chip J2, wherein pins 1-4 of a chip J2 are sequentially connected with a pin AG22, a pin AG21, a pin AH22 and a pin AH21 of the chip U1O, a pin 7 of the chip J2 is connected with a pin AG20 of a chip U1O, a pin 9 of the chip J2 is connected with a pin AH20 of the chip U1O, a pin 10 of the chip J2 is connected with a pin AG19 of the chip U1O, a pin 12 of the chip J2 is connected with a pin AH19 of the chip U1O, a pin 15 of a chip J2 is connected with a pin 3 of a thyristor Q1, a pin 2 of the thyristor Q1 is connected with an I2C5_ SCL terminal, a pin 1 of the thyristor Q1 is connected with a pin R130 2, and the input end of the resistor R130 is connected with a; pin 16 of the chip J2 is connected with pin 3 of the thyristor Q2, pin 2 of the thyristor Q2 is connected with the I2C5_ SDA terminal, pin 1 of the thyristor Q2 is connected with pin 2 of the resistor R132, and the input end of the resistor R132 is connected with the VCC _ IO port.
4. The receiving end of the over-the-air high definition digital image transmission system according to claim 1, wherein: the HDMI interface circuit is externally connected with a CPU end EMMC interface circuit, an EMMC chip peripheral interface circuit, a DDR related circuit and a CPU Ethernet interface, the CPU end EMMC interface circuit comprises a main chip CPU, interfaces FLASH _ D0-FLASH _ D7 of the main chip CPU are data reading buses, an EMMC _ PWREN interface of the main chip CPU is an EMMC module power-on enabling control line, an EMMC _ CLK0 interface is an EMMC communication clock line, and an EMMC _ CMD interface is a command central line and is used for controlling the EMMC; the peripheral interface of the EMMC chip comprises a chip U12, pins (DATA 0-DATA 7) of the chip U12 are respectively connected with interfaces FLASH _ D0-FLASH _ D7 of a main chip CPU, a pin CMD of the chip U12 is connected with an EMMC _ CMD interface of the main chip CPU, a pin RST _ N of the chip U12 is connected with an EMMC _ PWREN interface of the main chip CPU, and a pin CLK of the chip U12 is connected with a main chip CPMMC UECLK 0 interface; the DDR related circuit comprises a chip U1K and a chip U1L, a pin H14 of the chip U1K is connected with a VCC _ DDR terminal, the VCC _ DDR terminal is connected with a capacitor C247 in series and is grounded, and two ends of the capacitor C247 are sequentially connected with a capacitor C248 and a capacitor C249 in parallel; a pin H12 of a chip U1K is connected with a VREF-DDR0 terminal, a VREF-DDR0 terminal is connected with a capacitor C255 in series and grounded, two ends of the capacitor C255 are connected with a resistor R238 in parallel, an input end of the resistor R238 is connected with a resistor R236 and a VCC-DDR terminal, a pin H11 of the chip U1K is connected with a VREFAO-DDR0 terminal, a VREFAO-DDR0 terminal is connected with a capacitor C260 in series and grounded, two ends of the capacitor C260 are sequentially connected with a capacitor C259 and a resistor R242 in parallel, an input end of the resistor R242 is connected with a resistor R240 and a VCC-DDR terminal, and two ends of the resistor; the CPU Ethernet interface comprises a chip U1Q, a chip U18 and a chip U18, a pin AD 18 of the chip U1 18 is connected with a resistor R18 in series to be connected with a pin 23 of the chip U18, a pin AB 18 of the chip U1 18 is connected with a resistor R18 in series to be connected with a pin 24 of the chip U18, a pin Y18 of the chip U1 18 is connected with a pin 25 of the chip U18 in series to be connected with a resistor R18 in series to be connected with a pin 26 of the chip U18, a pin AA 18 of the chip U1 18 is connected with a resistor R18 in series to be connected with a pin 27 of the chip U18, a pin V18 of the chip U1 18 in series to be connected with a pin 16 of the chip U18, a pin AA 18 of the chip U1 18 in series to be connected with a resistor R18 in series to be connected with a pin 14 of the chip U18, a pin AA 18 of the chip U1 18 in series to be connected with a pin 72, a pin AA 18 of the chip U18, a pin AA 18 of the chip U1 and a pin 18 to be connected with a resistor R365, a pin 365 of the chip U6, a pin 18 and a pin 18 to be connected with a pin 365, a pin 365 of the chip U6, a pin 18 to be connected with a pin 365 and a pin 368 to, pin 1 and pin 2 of chip U19 are connected to pin 11 and pin 12 of chip U18, respectively.
5. The receiving end of a high-definition digital image transmission system of a traversing machine according to claim 1, wherein: a front-stage power supply circuit is arranged in the main power supply input module and comprises a chip U29, a pin 2 of a chip U29 is connected with a capacitor C206 in series and is grounded, the input end of the capacitor C206 is connected with a VCC _ SYSIN power supply terminal, a pin 7 of a chip U29 is connected with a capacitor C207 in series and is grounded, a pin 1 of a chip U29 is connected with an input end of a series resistor R185 connected with a capacitor C207 in series, a pin 5 of a chip U29 is sequentially connected with a resistor R182 in series, a capacitor C202 and an inductor L9 in series and is connected with a VCC _ SYS output terminal, a pin 3 of a chip U29 is connected with an output end of the capacitor C202, a pin 8 of a chip U29 is connected with a resistor R186 and a capacitor C203 and is connected with an output end of an inductor L9, an output end of.
6. The receiving end of a high-definition digital image transmission system of a traversing machine according to claim 1, wherein: the power interface B is internally provided with a power controller control circuit, the power controller control circuit comprises a chip U1D, the pin M27 of the chip U1D is connected with a capacitor C28 in series and is grounded, the pin P25 of the chip U1D is connected with a capacitor C29 in series and is grounded, the pin P28 of the chip U1D is connected with a VDD _10 terminal, and the pin M25 of the chip U1D is connected with an I2C0_ SDA _ PMIC terminal; the chip U29 is connected with a clock circuit, the clock circuit comprises a clock chip Y1, a pin 1 series resistor R2 of a clock chip Y1 is connected with a pin N28 of the chip U29, a pin 4 series resistor R3 of the clock chip Y1 is grounded, an input end of a resistor R3 is connected with an input end of a resistor R2 in series with a capacitor C31, a pin 3 of the clock chip Y1 is connected with a pin N27 of the chip U29, and a pin 2 series capacitor C30 of the clock chip Y1 is connected with a pin N27 of the chip U29 in series with the capacitor C30.
7. The receiving end of a high-definition digital image transmission system of a traversing machine according to claim 1, wherein: the power interface C is internally provided with a mainboard CPU main power circuit, the mainboard CPU main power circuit comprises a chip U1 and a chip U1, pins (U-U) and pins (V-V) of the chip U1 are connected with a VDD _ CPU terminal, the VDD _ CPU terminal is connected with a capacitor C in series, two ends of the capacitor C are sequentially connected with the capacitor C, the capacitor C and the capacitor C in parallel, pins (L-L) and pins (M-M) and pins (N-N) of the chip U1 are connected with a VDD _ GPU terminal, the VDD _ GPU terminal is connected with the capacitor C in series and grounded, two ends of the capacitor C are sequentially connected with the capacitor C, the capacitor C and the capacitor C in parallel, a pin V of the chip U1 is connected with a VCC _ LCD terminal, the VCC _ LCD terminal is connected with the capacitor C in series and grounded, a pin T of the chip U1 is connected with a VDD _ LOG terminal, the.
8. The receiving end of a high-definition digital image transmission system of a traversing machine according to claim 1, wherein: a power supply main chip PMU working circuit is arranged in the power supply interface D, the power supply main chip PMU working circuit comprises a chip U6, a chip U7 and a chip U8, a pin 13, a pin 14, a pin 18, a pin 25, a pin 30, a pin 41, a pin 47 and a pin 48 of the chip U6 are all connected with a VCC _ SYS output terminal of the chip U29, a pin 28 of the chip U6 is connected with an inductor L1 in series to be connected with a VCC-DDR terminal, a pin 26 of the chip U6 is connected with an inductor L4 in series to be connected with a VCC-20 terminal, a pin 11 of the chip U6 is connected with an inductor L2 in series to be connected with a VCC-IO terminal, a pin 1 of the chip U6 is connected with an inductor L5 in series to be connected with a VCC-LOG terminal, a pin 40 of the chip U6 is connected with a capacitor C106 in series to be grounded, an input terminal of the capacitor C106 is connected with a VCC 36; a pin D1 of the chip U7 is connected with a capacitor C94 in series and grounded, the input end of the capacitor C94 is connected with a VCC _ SYS output terminal of the chip U29, a terminal D3 of the chip U7 is connected with an inductor L3 and a capacitor C96 in series and grounded, the input end of the capacitor C96 is connected with a VDD _ CPU terminal, a terminal A2 of the chip U7 is connected with a capacitor C99 in series and grounded, and the input end of the capacitor C99 is connected with a VCC _ DDR terminal; the pin D1 of the chip U8 is connected in series with a capacitor C112 and grounded, the input end of the capacitor C112 is connected with a VCC _ SYS output terminal of the chip U29, the pin D3 of the chip U8 is connected in series with an inductor L6 and a capacitor C114 and grounded, the input end of the capacitor C114 is connected with a VDD _ GPU terminal, the terminal A2 of the chip U8 is connected in series with a capacitor C119 and grounded, and the input end of the capacitor C119 is connected with a VCC _ DDR terminal.
9. The receiving end of a high-definition digital image transmission system of a traversing machine according to claim 1, wherein: the USB interface circuit of the USB interface B built-in USB interface circuit comprises a pin bank J25, a pin 1 of the pin bank J25 is connected with a magnetic bead LB18 in series to be connected with a 5V0_ WL terminal, an input end of the magnetic bead LB18 is connected with a capacitor C434 in a ground mode, a pin 2 of the magnetic bead LB18 is connected with a USB _ DM terminal, and a pin 3 of the magnetic bead LB18 is connected with a USB _ DP terminal.
10. The receiving end of a high-definition digital image transmission system of a traversing machine according to claim 1, wherein: the mobile terminal adopts a mobile phone or a tablet personal computer, corresponding APP software is installed, the video data can be acquired through the mobile phone forwarding module, the first-person video of the player can be watched in real time after the video data is acquired, and meanwhile, the video can be selectively recorded to the mobile phone.
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Application publication date: 20200522 |