CN111193818A

CN111193818A - Method, system, equipment and medium for obtaining IP address

Info

Publication number: CN111193818A
Application number: CN201911413817.0A
Authority: CN
Inventors: 梁盛楠
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2020-05-22

Abstract

The invention discloses a method, a system, equipment and a storage medium for acquiring an IP address, wherein the method comprises the following steps: circularly acquiring the states of the first LED indicating pin and the second LED indicating pin, and storing the states into a register; acquiring states from the register at preset time intervals, and judging whether network interruption exists or not based on the states; in response to the presence of a network disruption, shortening the predetermined time and repeating the previous step until there is no network disruption; and invoking a restart network service command to obtain the new IP address. The method, the system, the equipment and the medium for acquiring the IP address indicate the speed and the communication state of the network port through the first LED indication pin and the second LED indication pin, and acquire the IP address when the network is communicated again.

Description

Method, system, equipment and medium for obtaining IP address

Technical Field

The present invention relates to the field of networks, and in particular, to a method, a system, a computer device, and a readable medium for acquiring an IP address.

Background

The white box switch is a novel switch construction system with software and hardware separated. A complete switch system can be formed by purchasing the bare hardware of the switch of the ODM (original design manufacturer) and matching with some optional open source operating systems. The trend in future data centers is to gradually replace existing legacy switches with white box switches.

The BMC (Baseboard Management Controller) is a control chip on a motherboard of a white box switch, which can remotely operate a CPU, is a system independent of the CPU end of the switch, and can remotely monitor some performance indexes on the switch system, and perform a series of operations such as on/off operation, system upgrade, and device check on the switch. When a DHCP (Dynamic Host Configuration Protocol) service in the BMC system is abnormal or an underlying network driver is abnormal, it may happen that an IP address cannot be automatically acquired through the DHCP service, and at this time, a remedial measure is required to replace the DHCP function.

Disclosure of Invention

In view of this, an objective of the embodiments of the present invention is to provide a method, a system, a computer device, and a computer readable storage medium for acquiring an IP address, where a first LED indication pin and a second LED indication pin are used to indicate a rate and a communication state of a network port, so that a network problem can be found in time, and the IP address can be acquired when the network is connected again.

Based on the above object, an aspect of the embodiments of the present invention provides a method for acquiring an IP address, including the following steps: circularly acquiring the states of the first LED indicating pin and the second LED indicating pin, and storing the states into a register; acquiring the state from the register at preset time intervals, and judging whether network interruption exists or not based on the state; in response to the presence of a network outage, shortening the predetermined time and repeating the previous step until there is no network outage; and invoking a restart network service command to obtain the new IP address.

In some embodiments, storing the states each in a register comprises: and converting the combination of the states of the first LED indication pin and the second LED indication pin into a numerical value to be stored in a register.

In some embodiments, said obtaining said status from said register at predetermined time intervals and determining if there is a network interrupt based on said status comprises: and acquiring a numerical value from the register at preset time intervals, and judging whether the acquired numerical value is a preset numerical value or not.

In some embodiments, further comprising: and responding to the absence of network interruption, and indicating the transmission rate of the network through the acquired numerical value.

In some embodiments, further comprising: the predetermined time is initialized in response to the end of the network outage.

In another aspect of the embodiments of the present invention, a system for accelerating reading of information of a field replaceable unit is further provided, including: the state acquisition module is configured for circularly acquiring the states of the first LED indication pin and the second LED indication pin and storing the states into the register; the first judging module is configured to acquire the state from the register at preset time intervals and judge whether network interruption exists or not based on the state; a second judgment module configured to shorten the predetermined time and repeat the previous step in response to the presence of the network interruption until the network interruption is absent; and a control module configured to invoke a restart network service command to obtain a new IP address.

In some embodiments, the status acquisition module is further configured to: and converting the combination of the states of the first LED indication pin and the second LED indication pin into a numerical value to be stored in a register.

In some embodiments, the first determining module is further configured to: and acquiring a numerical value from the register at preset time intervals, and judging whether the acquired numerical value is a preset numerical value or not.

In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.

In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.

The invention has the following beneficial technical effects: the speed and the communication state of the network port are indicated through the first LED indication pin and the second LED indication pin, so that the network problem can be found in time, the IP address can be obtained when the network is communicated again, and the function of automatically obtaining the IP address can be normally used when the DHCP service of the system per se fails.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

Fig. 1 is a schematic diagram of an embodiment of a method for acquiring an IP address provided in the present invention;

fig. 2 is a schematic diagram of a hardware structure of an embodiment of the method for acquiring an IP address provided by the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

In view of the above object, a first aspect of the embodiments of the present invention provides an embodiment of a method for acquiring an IP address. Fig. 1 is a schematic diagram illustrating an embodiment of a method for acquiring an IP address provided by the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:

s1, circularly acquiring the states of the first LED indicating pin and the second LED indicating pin, and storing the states into a register;

s2, acquiring states from the register at preset time intervals, and judging whether network interruption exists or not based on the states;

s3, responding to the network interruption, shortening the preset time and repeating the previous step until no network interruption exists; and

and S4, calling a restart network service command to acquire a new IP address.

In the embodiment of the present invention, an RJ-45 socket of the BMC management network port is connected to a PHY (physical layer) chip BCM54210S, and two LED pins of the BCM54210S are respectively connected to two GPIOs (General-purpose input-output interfaces) of a CPLD (Complex Programmable Logic Device). The first LED indication pin can use a LINKSPD [1] mode, the second LED indication pin can use a LINKSPD [2] mode, and the states of the first LED indication pin and the second LED indication pin respectively have two states of high level and low level.

And respectively and cyclically acquiring the states of the first LED indicating pin and the second LED indicating pin, and storing the states into a register. And the CPLD acquires a first LED indication pin and a second LED indication pin of the PHY chip, acquires the current state of the network card and stores the state into a register of the CPLD. In some embodiments, storing the states each in a register comprises: and converting the combination of the states of the first LED indication pin and the second LED indication pin into a numerical value to be stored in a register. For example, a high level may correspond to a digital 0, a low level may correspond to a digital 1, a state value 00 represents that both the first LED indication pin and the second LED indication pin are at a high level, and the state value 00 may be converted into a 0 to be written into the register.

The status is obtained from the register at predetermined intervals and it is determined whether there is a network interruption based on the status. The states of the first LED indication pin and the second LED indication pin may be preset when the network is interrupted, for example, the network may be interrupted when the first LED indication pin and the second LED indication pin are both at a low level. The BMC accesses the CPLD register content through the I2C bus at regular time, and judges whether the states of the first LED indication pin and the second LED indication pin are the same as the preset state during network interruption. In some embodiments, said obtaining said status from said register at predetermined time intervals and determining if there is a network interrupt based on said status comprises: and acquiring a numerical value from the register at preset time intervals, and judging whether the acquired numerical value is a preset numerical value or not. For example, a network interrupt value of 3, i.e. a status value of 11, is preset, and if the value obtained from the register is 3, it indicates that there is a network interrupt.

In response to the presence of the network interruption, the predetermined time is shortened and the previous step, i.e., step S2, is repeated until there is no network interruption. For example, the predetermined time is 20 seconds, the state is obtained from the register every 20 seconds and it is determined whether there is a network interrupt, if there is, the predetermined time may be shortened to 10 seconds, and then the state is obtained from the register every 10 seconds and it is determined whether there is a network interrupt, and the process is circulated until the network interrupt is recovered. In some embodiments, further comprising: and responding to the absence of network interruption, and indicating the transmission rate of the network through the acquired numerical value. A value 0 (corresponding to a state value 00) may be preset to indicate a rate of 1000, a value 1 (corresponding to a state value 01) to indicate a rate of 100, and a value 2 (corresponding to a state value 10) to indicate a rate of 10, so that the obtained values may indicate a transmission rate of the network.

In some embodiments, further comprising: the predetermined time is initialized in response to the end of the network outage. And initializing the shortened preset time to reduce the pressure of data reading and writing.

A restart web services command is invoked to obtain a new IP address. When the network is interrupted and recovered, a network restart service command can be called to restart the network and obtain a new IP address again. Therefore, the IP address can be automatically acquired after the network is recovered.

It should be particularly noted that, the steps in the embodiments of the method for acquiring an IP address described above may be mutually intersected, replaced, added, or deleted, and therefore, these methods for acquiring an IP address that are reasonably transformed by permutation and combination should also belong to the scope of the present invention, and should not limit the scope of the present invention to the embodiments.

In view of the above, a second aspect of the embodiments of the present invention provides a system for data backup based on a private cloud, including: the state acquisition module is configured for circularly acquiring the states of the first LED indication pin and the second LED indication pin and storing the states into the register; the first judging module is configured to acquire the state from the register at preset time intervals and judge whether network interruption exists or not based on the state; a second judgment module configured to shorten the predetermined time and repeat the previous step in response to the presence of the network interruption until the network interruption is absent; and a control module configured to invoke a restart network service command to obtain a new IP address.

In some embodiments, the second determining module is further configured to: and responding to the absence of network interruption, and indicating the transmission rate of the network through the acquired numerical value.

In some embodiments, the method further comprises initializing a predetermined time in response to the network outage ending.

In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, respectively acquiring the states of the first LED indicating pin and the second LED indicating pin, and storing the states into a register; s2, acquiring states from the register at preset time intervals, and judging whether network interruption exists or not based on the states; s3, responding to the existence of network interruption, shortening preset time, acquiring the state from the register every preset time again, and judging whether the network interruption exists or not until the network interruption does not exist; and S4, invoking a restart network service command to obtain a new IP address.

Fig. 2 is a schematic diagram of a hardware structure of an embodiment of the method for acquiring an IP address according to the present invention.

Taking the apparatus shown in fig. 2 as an example, the apparatus includes a processor 301 and a memory 302, and may further include: an input device 303 and an output device 304.

The processor 301, the memory 302, the input device 303 and the output device 304 may be connected by a bus or other means, and fig. 2 illustrates the connection by a bus as an example.

The memory 302 is a non-volatile computer-readable storage medium, and can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the method for acquiring an IP address in the embodiment of the present application. The processor 301 executes various functional applications of the server and data processing by running the nonvolatile software programs, instructions and modules stored in the memory 302, that is, implements the method of acquiring an IP address of the above-described method embodiment.

The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the method of acquiring an IP address, and the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The input device 303 may receive information such as a user name and a password that are input. The output means 304 may comprise a display device such as a display screen.

Program instructions/modules corresponding to one or more methods of acquiring an IP address are stored in the memory 302 and, when executed by the processor 301, perform the method of acquiring an IP address in any of the above-described method embodiments.

Any embodiment of the computer device executing the method for acquiring the IP address can achieve the same or similar effects as any corresponding embodiment of the method.

The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.

Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes in the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for acquiring an IP address can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.

Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.

Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.

Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A method for obtaining an IP address, comprising the steps of:

circularly acquiring the states of the first LED indicating pin and the second LED indicating pin, and storing the states into a register;

acquiring the state from the register at preset time intervals, and judging whether network interruption exists or not based on the state;

in response to the presence of a network outage, shortening the predetermined time and repeating the previous step until there is no network outage; and

a restart web services command is invoked to obtain a new IP address.

2. The method of claim 1, wherein storing the states each in a register comprises:

and converting the combination of the states of the first LED indication pin and the second LED indication pin into a numerical value to be stored in a register.

3. The method of claim 2, wherein the obtaining the status from the register at predetermined time intervals and determining whether there is a network disruption based on the status comprises:

and acquiring a numerical value from the register at preset time intervals, and judging whether the acquired numerical value is a preset numerical value or not.

4. The method of claim 3, further comprising:

and responding to the absence of network interruption, and indicating the transmission rate of the network through the acquired numerical value.

5. The method of claim 1, further comprising:

the predetermined time is initialized in response to the end of the network outage.

6. A system for obtaining an IP address, comprising:

the state acquisition module is configured for circularly acquiring the states of the first LED indication pin and the second LED indication pin and storing the states into the register;

the first judging module is configured to acquire the state from the register at preset time intervals and judge whether network interruption exists or not based on the state;

a second judgment module configured to shorten the predetermined time and repeat the previous step in response to the presence of the network interruption until the network interruption is absent; and

and the control module is configured to invoke a restart network service command to acquire a new IP address.

7. The system of claim 6, wherein the status acquisition module is further configured to:

8. The system of claim 7, wherein the first determining module is further configured to:

9. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 5.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.