CN111193391B - Staggered parallel totem-pole bridgeless PFC phase control method - Google Patents
Staggered parallel totem-pole bridgeless PFC phase control method Download PDFInfo
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- CN111193391B CN111193391B CN201911338840.8A CN201911338840A CN111193391B CN 111193391 B CN111193391 B CN 111193391B CN 201911338840 A CN201911338840 A CN 201911338840A CN 111193391 B CN111193391 B CN 111193391B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a method for controlling a bridge-free PFC phase of staggered parallel totem poles, which comprises the following steps: the switching-on of the switching tubes on the master phase and the slave phase which are connected in parallel in a staggered mode is controlled through an inductive current zero-crossing detection signal; setting a period value of the PWM module, wherein the period value of the PWM module is higher than a period value corresponding to the lowest switching frequency of the switching tube; capturing a PWM count value when a main phase triggers an inductive current zero-crossing detection signal in a main phase and a slave phase through a DSP (digital signal processor), and recording the PWM count value as a first count value; capturing a PWM count value when a slave phase triggers an inductive current zero-crossing detection signal in a master-slave phase through a DSP (digital signal processor), and recording the PWM count value as a second count value; and adjusting the conduction time of the switching tubes on the master-slave phase through the first counting value and the second counting value. The invention realizes the frequency conversion control of the master phase and the slave phase which are connected in parallel in a two-phase or multi-phase staggered way, realizes zero current switching on of each phase, greatly reduces the system input current ripple waves by phase control, and improves the efficiency of the whole machine.
Description
Technical Field
The invention relates to the field of power factor correction, in particular to a phase control method for a bridge-free PFC (power factor correction) of staggered parallel totem poles.
Background
In order to improve Power Factor and reduce the harmonic content of input current, Power Factor Correction (PFC) circuits are widely used in Power electronic devices. The traditional PFC interleaving parallel technology is that two or more paths of input and output of PFC circuits with the same structure are connected in parallel, the working signal frequencies of all PFC units are consistent, and the control phase angles of the switching tubes are staggered by a fixed angle, such as 180 degrees, so that input current ripples are partially or completely offset, and the ripples of input current are greatly reduced. Conventional pfc circuits typically employ fixed frequency PWM control and operate the circuit in Continuous Conduction Mode (CCM). Under the same power, the frequency is fixed in the CCM mode, the inductive current ripple is small, the pre-filter is small and convenient to design, and the CCM mode power factor correction circuit is simple to control and is widely applied to most power factor correction circuits. However, since zero current turn-on and turn-off cannot be achieved, the switching loss is large, and it is difficult for the CCM mode circuit to operate at high efficiency. The traditional active PFC circuit controlled by analog chips such as UC3854, L4981 and the like has the defects of inflexible control method, aging of components and the like.
Compared with the traditional PFC circuit, the totem-pole bridgeless PFC circuit is simple in structure and higher in efficiency, can reduce conduction loss, and improves power density. However, in the Critical-continuous Mode (CRM), the inductor current drops to zero every switching period, the inductor current peak is large, the current ripple is large, and a large pre-filter is required. In this mode, the design of the filter is also more difficult due to the frequency conversion operation. In addition, since the current peak is large, there is a large stress on the device, which limits the choice of the device. Due to the above features in CRM mode, the circuit power level in this mode is generally small. Zero voltage switching-on or current valley bottom switching-on of the switch tube can be realized under the CRM mode, and the loss of the switch tube is very small. However, in the CRM mode, the difficulty of realizing staggered parallel connection is higher than that in the fixed frequency operation. The traditional interleaving and parallel connection is fixed switching frequency, and only when the PWM signals are configured, the master PWM signal and the slave PWM signal have a phase relation of a fixed angle, for example, two phases are separated by 180 degrees. However, under the condition of the interleaved parallel-connection variable frequency operation, the implementation of the interleaved 180 degrees is relatively complex compared with the fixed frequency operation because the switching frequencies at different moments in a mains power frequency period are actually different, and because of the difference of the devices of the circuits, the Current Zero-crossing moments of the interleaved parallel-connection power devices are not completely the same, if only the switching-on moment of the main phase is controlled, the phase relation of the slave phase is fixed at the PWM fixed interval, and the slave phase is not triggered and controlled by the self inductive Current Zero-crossing Detection (ZCD) signal, so that the switching-on moment of the slave phase switching tube is possibly not Zero-voltage switching-on or valley bottom switching-on, and the low switching loss cannot be ensured.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a phase control method for staggered parallel totem-pole bridgeless PFC.
The technical scheme of the invention is as follows:
a phase control method for staggered parallel totem-pole bridgeless PFC (power factor correction), is characterized by comprising the following steps:
the switching-on of switching tubes on the master phase and the slave phase which are connected in parallel in a staggered mode is controlled through an inductive current zero-crossing detection signal, and the switching-on of the switching tubes of each phase is controlled through the inductive current zero-crossing detection signal;
setting a period value of a PWM module, wherein the period value of the PWM module is higher than a period value corresponding to the lowest switching frequency of the switching tube;
capturing a PWM count value when the main phase in the main phase and the slave phase triggers the inductive current zero-crossing detection signal through a DSP (digital signal processor), and recording the PWM count value as a first count value;
capturing a PWM count value when the slave phase in the master-slave phase triggers the inductive current zero-crossing detection signal through the DSP, and recording the PWM count value as a second count value;
and adjusting the conduction time of the switching tubes on the master phase and the slave phase according to the first counting value and the second counting value.
According to the invention of the above scheme, when the switching frequency of the switching tube is higher than the frequency corresponding to the period value of the PWM module, the inductor current zero crossing detection signal controls the switching tube to be turned on; and when the switching frequency of the switching tube is lower than the frequency corresponding to the period value of the PWM module, the period value of the PWM module controls the switching-on of the switching tube.
The invention according to the above scheme is characterized in that when the master phase and the slave phase are in closed-loop control, the master phase and the slave phase control the turn-on of the corresponding switching tubes according to the detected zero-crossing detection signals of the inductive current, and the turn-off of the switching tubes is controlled according to the turn-on time obtained by voltage loop feedback.
The present invention according to the above-mentioned scheme is characterized in that, when the inductive current zero-crossing detection signal of the main phase is triggered, the value of the time-base counter of the main phase is cleared, a next cycle is started, and at the same time, the value of the time-base counter of the main phase is captured by the DSP processor and loaded into the capture control register of the main phase.
Further, when the inductive current zero-crossing detection signal of the slave phase is triggered, the value of the time-base counter of the slave phase is cleared, and the next cycle is started.
The present invention according to the above aspect is characterized in that when the main phase triggers the inductor current zero crossing detection signal, the DSP processor captures and records a first PWM count value of a capture control register of the main phase and a second PWM count value of a time base counter;
capturing and recording a third PWM count value of a time-base counter of the slave phase through the DSP processor when the slave phase triggers the inductive current zero-crossing detection signal;
and adjusting the conduction time of the switching tubes on the master phase and the slave phase through the first PWM count value, the second PWM count value and the third PWM count value.
Further, when the switching frequency of the master phase is lower than that of the slave phase, obtaining a first adjustment step length according to the first PWM count value, the second PWM count value, the third PWM count value and an empirical adjustment value of the mains voltage;
and in the next period, on the basis that the voltage loop calculates a first duty ratio of the main phase and a second duty ratio of the slave phase, the first duty ratio is added with the first adjusting step length, and the second duty ratio is subtracted with the first adjusting step length.
Further, when the switching frequency of the master phase is higher than that of the slave phase, obtaining a second adjustment step length according to the first PWM count value, the second PWM count value, the third PWM count value and an empirical adjustment value of the mains voltage;
and in the next period, on the basis that the voltage loop calculates a first duty ratio of the main phase and a second duty ratio of the slave phase, the first duty ratio is added with the second adjusting step length, and the second duty ratio is subtracted with the second adjusting step length.
Further, when the switching frequency of the master phase is equal to the switching frequency of the slave phase, obtaining an adjustment angle according to the first PWM count value, the second PWM count value and the third PWM count value;
at the next cycle, the phase of the master phase is added to the adjustment angle and the phase of the slave phase is subtracted from the adjustment angle.
The invention according to the above aspect is characterized in that the counter of the PWM module is in an up mode.
The invention has the beneficial effects that:
according to the invention, the input current ripple of the PFC circuit is reduced by a two-phase or multi-phase interleaving parallel technology, the size of a pre-stage filter is reduced, and the power density is improved; the switching loss of the power device is reduced in a critical continuous mode, zero current switching-on is realized, and the switching loss is small; the two phases or the multiple phases are in staggered parallel connection, the master phase and the slave phase are controlled by frequency conversion, each phase is conducted by an inductive current zero-crossing detection signal independent of each phase to control a switching tube, zero current switching-on of each phase is realized, and meanwhile, phase control enables system input current ripples to be greatly reduced, so that the efficiency of the whole machine is improved; the frequency conversion control switch tube of the independent inductive current zero-crossing detection signal of each phase is still realized under the condition that the main phase frequency is the same as or different from the auxiliary phase frequency.
Drawings
FIG. 1 is a flow chart of an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a phase difference between a master phase and a slave phase being 180 degrees according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a master phase switching frequency lower than a slave phase switching frequency and a slave phase advancing according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating the switching frequency of the master phase being lower than the switching frequency of the slave phase and the phase lag of the slave phase according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating that the switching frequency of the master phase is higher than that of the slave phase according to an embodiment of the present invention.
Detailed Description
The invention is further described with reference to the following figures and embodiments:
as shown in fig. 1, an embodiment of the invention provides a method for controlling phases of a cross-parallel totem-pole bridgeless PFC, which includes the following steps:
step S1: the switching-on of the switching tubes on the master phase and the slave phase which are connected in parallel in a staggered mode is controlled through the inductive current zero-crossing detection signal, and the switching-on of the switching tubes of each phase is controlled through the inductive current zero-crossing detection signal of each phase.
Step S2: and setting a period value of the PWM module, wherein the period value of the PWM module is higher than a period value corresponding to the lowest switching frequency of the switching tube. The period value of the PWM module is generally much higher than the period value of the lowest switching frequency of the switching tube. When the switching frequency of the switching tube is higher than the frequency corresponding to the period value of the PWM module, the inductive current zero-crossing detection signal controls the switching-on of the switching tube; and when the switching frequency of the switching tube is lower than the frequency corresponding to the period value of the PWM module, the period value of the PWM module controls the switching-on of the switching tube.
Step S3: and capturing a PWM count value when the main phase in the main phase and the slave phase triggers the inductive current zero-crossing detection signal through the DSP processor, and recording the PWM count value as a first count value. Specifically, the PWM count value is captured by a Capture Control Logic (Capture Control Logic) function of the DSP processor. When the inductive current zero-crossing detection signal triggers TZ, a DCAEVT or DCBEVT signal is generated, the function is triggered by the rising edge of the filtered DCEVTFLT signal from low to high, and the value of the current time base counter tbtr is recorded in the capture control register DCCAP. The capture value of the capture control register DCCAP will remain unchanged from the value of the first trigger until the PWM count reaches the cycle point or zero.
Step S4: and capturing a PWM count value when the slave phase triggers the inductive current zero-crossing detection signal in the master-slave phase through the DSP, and recording the PWM count value as a second count value.
Step S5: and adjusting the conduction time of the switching tubes on the master-slave phase through the first counting value and the second counting value. The first count value represents the switching frequency of the switching tube on the master phase, the second count value represents the switching frequency of the switching tube on the slave phase, and the conducting time of the switching tube on the master phase and the conducting time of the switching tube on the slave phase are adjusted according to the magnitude relation between the two values and the theoretical phase angle under the switching frequency at the moment, so that the phase difference between the master phase and the slave phase is adjusted to be the theoretically calculated angle, as shown in fig. 2, the two phases are separated by 180 degrees.
In this embodiment, when the master phase and the slave phase are in closed-loop control, the master phase and the slave phase control the turn-on of the corresponding switching tubes according to the detected zero-crossing detection signals of the inductive current, and the turn-off of the switching tubes is controlled according to the turn-on time obtained by the feedback of the voltage loop.
In this embodiment, when the zero-crossing detection signal of the inductor current of the main phase is triggered, the value of the time-base counter of the main phase is cleared to start the next cycle, and the value of the time-base counter of the main phase is captured by the capture control logic function of the DSP processor and loaded into the capture control register of the main phase, where the value also represents the current switching frequency.
And when the inductive current zero-crossing detection signal of the slave phase is triggered, clearing the value of the time base counter of the slave phase to start the next period.
In the embodiment, when the main phase triggers the inductor current zero-crossing detection signal, the capture control logic function of the DSP processor captures and records the first PWM count value of the capture control register of the main phase and the second PWM count value of the time-base counter. And when the slave phase triggers the inductive current zero-crossing detection signal, capturing and recording a third PWM count value of a time-base counter of the slave phase through a capture control logic function of the DSP processor. And adjusting the conduction time of the switching tubes on the master phase and the slave phase through the first PWM count value, the second PWM count value and the third PWM count value.
As shown in fig. 3 and 4, when the switching frequency of the master phase is lower than or equal to that of the slave phase, there are two cases where the phase leads and lags the master phase. When the main phase triggers the inductive current zero-crossing detection signal, the value of a capture control register DCCAP of the main phase is recorded as ePWM1_ DCCAP, and the value of a time base counter TBCTR of the main phase is recorded as ePWM1_ TBCTR. When the slave phase triggers the inductive current zero-crossing detection signal, the value of a time base counter TBCTR of the slave phase is recorded as ePWM2_ TBCTR.
When the switching frequency of the main phase is equal to or close to that of the slave phase, the adjustment angle of the master-slave phase is obtained according to ePWM1_ DCCAP, ePWM1_ TBTR and ePWM2_ TBTR,
in the next cycle, the phase of the main phase is added to the adjustment angle and the adjustment angle is subtracted from the phase of the phases so that the phases of the two phases are 180 degrees apart.
When the switching frequency of the main phase is lower than that of the slave phase, a first adjusting step size is obtained according to ePWM1_ DCCAP, ePWM1_ TBCTR, ePWM2_ TBCTR and the experience adjusting value K1 of the mains voltage,
in the next period, on the basis that the voltage ring calculates the first duty ratio of the main phase and the second duty ratio of the slave phase, the first duty ratio is added with a first adjusting step length, the second duty ratio is subtracted with the first adjusting step length, the duty ratio of the main phase is adjusted according to the positive and negative of the step length, the PWM of the main phase is turned off in advance or in a delayed mode, the turn-off time is delayed or advanced from the corresponding adjusting duty ratio, the phase of the master phase and the slave phase is controlled in a closed loop mode, and the phase relation of 180 degrees is quickly achieved.
As shown in fig. 5, the switching frequency of the master phase is higher than that of the slave phase. When the main phase triggers the inductive current zero-crossing detection signal, the value of a capture control register DCCAP of the main phase is recorded as ePWM1_ DCCAP, and the value of a time base counter TBCTR of the main phase is recorded as ePWM1_ TBCTR. When the slave phase triggers the inductive current zero-crossing detection signal, the value of a time base counter TBCTR of the slave phase is recorded as ePWM2_ TBCTR.
When the switching frequency of the main phase approaches the switching frequency of the slave phase, the adjustment angle of the main phase and the slave phase is obtained according to ePWM1_ DCCAP, ePWM1_ TBTR and ePWM2_ TBTR,
in the next cycle, the phase of the main phase is added to the adjustment angle and the adjustment angle is subtracted from the phase of the phases so that the phases of the two phases are 180 degrees apart.
When the switching frequency of the main phase is higher than that of the slave phase, a second adjusting step length is obtained according to ePWM1_ DCCAP, ePWM1_ TBCTR, ePWM2_ TBCTR and the experience adjusting value K2 of the mains voltage,
in the next period, on the basis that the voltage ring calculates the first duty ratio of the main phase and the second duty ratio of the slave phase, the first duty ratio is added with a second adjusting step length, the second duty ratio is subtracted with the second adjusting step length, the duty ratio of the main phase is adjusted according to the positive and negative of the step length, the PWM of the main phase is turned off in advance or in a delayed mode, the turn-off time is delayed or advanced from the corresponding adjusting duty ratio, the phase of the master phase and the slave phase is controlled in a closed loop mode, and the phase relation of 180 degrees is quickly achieved.
And in a mains power frequency period, setting an empirical regulation value K of mains voltage according to the capture control register DCCAP value of the main phase, the time base counter TBCTR value of the main phase and the time base counter TBCTR value of the slave phase, and accelerating the speed of regulating phase tracking.
In this embodiment, the counter of the PWM module is in the up mode.
In this embodiment, the DSP processor is a TMS320F28035 chip.
The invention has the beneficial effects that:
according to the invention, the input current ripple of the PFC circuit is reduced by a two-phase or multi-phase interleaving parallel technology, the size of a pre-stage filter is reduced, and the power density is improved; the switching loss of the power device is reduced in a critical continuous mode, zero current switching-on is realized, and the switching loss is small; the two phases or the multiple phases are in staggered parallel connection, the master phase and the slave phase are controlled by frequency conversion, each phase is conducted by an inductive current zero-crossing detection signal independent of each phase to control a switching tube, zero current switching-on of each phase is realized, and meanwhile, phase control enables system input current ripples to be greatly reduced, so that the efficiency of the whole machine is improved; the frequency conversion control switch tube of the independent inductive current zero-crossing detection signal of each phase is still realized under the condition that the main phase frequency is the same as or different from the auxiliary phase frequency.
It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.
The invention is described above with reference to the accompanying drawings, which are illustrative, and it is obvious that the implementation of the invention is not limited in the above manner, and it is within the scope of the invention to adopt various modifications of the inventive method concept and technical solution, or to apply the inventive concept and technical solution to other fields without modification.
Claims (8)
1. A phase control method for staggered parallel totem-pole bridgeless PFC (power factor correction), is characterized by comprising the following steps:
the switching-on of switching tubes on the master phase and the slave phase which are connected in parallel in a staggered mode is controlled through an inductive current zero-crossing detection signal, and the switching-on of the switching tubes of each phase is controlled through the inductive current zero-crossing detection signal;
setting a period value of a PWM module, wherein the period value of the PWM module is higher than a period value corresponding to the lowest switching frequency of the switching tube;
capturing a PWM count value when the main phase in the main phase and the slave phase triggers the inductive current zero-crossing detection signal through a DSP (digital signal processor), and recording the PWM count value as a first count value;
capturing a PWM count value when the slave phase in the master-slave phase triggers the inductive current zero-crossing detection signal through the DSP, and recording the PWM count value as a second count value;
adjusting the conduction time of the switching tubes on the master phase and the slave phase according to the first counting value and the second counting value;
when the main phase triggers the inductive current zero-crossing detection signal, capturing and recording a first PWM count value of a capture control register of the main phase and a second PWM count value of a time-base counter through the DSP processor;
capturing and recording a third PWM count value of the time-based counter of the slave phase by the DSP processor when the slave phase triggers the inductive current zero-crossing detection signal;
adjusting the conduction time of the switching tubes on the master phase and the slave phase according to the first PWM count value, the second PWM count value and the third PWM count value;
when the switching frequency of the main phase is lower than that of the slave phase, obtaining a first adjusting step length according to the first PWM count value, the second PWM count value, the third PWM count value and an empirical adjusting value of mains voltage,
the first PWM count value is ePWM1_ DCCAP, the second PWM count value is ePWM1_ TBCTR, the third PWM count value is ePWM2_ TBCTR, and the experience adjustment value of the mains voltage is K1;
and in the next period, on the basis that the voltage loop calculates a first duty ratio of the main phase and a second duty ratio of the slave phase, the first duty ratio is added with the first adjusting step length, and the second duty ratio is subtracted with the first adjusting step length.
2. The phase control method for the bridge-less PFC of the claim 1, wherein when the switching frequency of the switching tube is higher than the frequency corresponding to the period value of the PWM module, the zero-crossing detection signal of the inductive current controls the switching tube to be turned on; and when the switching frequency of the switching tube is lower than the frequency corresponding to the period value of the PWM module, the period value of the PWM module controls the switching-on of the switching tube.
3. The phase control method according to claim 1, wherein when the master phase and the slave phase are in closed-loop control, the master phase and the slave phase control the switching on of the corresponding switching tubes according to the detected zero-crossing detection signal of the inductive current, and the switching off of the switching tubes is controlled according to the on-time obtained by voltage loop feedback.
4. The method according to claim 1, wherein when the zero-crossing detection signal of the inductor current of the main phase triggers, the value of the time-based counter of the main phase is cleared to start the next cycle, and the value of the time-based counter of the main phase is captured by the DSP processor and loaded into the capture control register of the main phase.
5. The method according to claim 4, wherein the value of the time-base counter of the slave phase is cleared to start the next cycle when the inductor current zero-crossing detection signal of the slave phase triggers.
6. The method according to claim 1, wherein when the switching frequency of the master phase is higher than the switching frequency of the slave phase, a second adjustment step is obtained according to the first PWM count value, the second PWM count value, the third PWM count value, and an empirical regulation value of the mains voltage,
the empirical regulation value of the mains voltage is K2;
and in the next period, on the basis that the voltage loop calculates a first duty ratio of the main phase and a second duty ratio of the slave phase, the first duty ratio is added with the second adjusting step length, and the second duty ratio is subtracted with the second adjusting step length.
7. The method according to claim 1, wherein when the switching frequency of the master phase is equal to the switching frequency of the slave phase, an adjustment angle is obtained according to the first PWM count value, the second PWM count value, and the third PWM count value,
at the next cycle, the phase of the master phase is added to the adjustment angle and the phase of the slave phase is subtracted from the adjustment angle.
8. The method of claim 1, wherein the counter of the PWM module is in an up mode.
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| CN113206657B (en) * | 2021-03-24 | 2022-09-16 | 珠海泰为电子有限公司 | PWM signal generation method and device of PFC circuit, storage medium and electronic equipment |
| CN114915159B (en) * | 2022-07-18 | 2022-10-25 | 浙江大学杭州国际科创中心 | Power factor correction rectifier |
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