CN111192904A

CN111192904A - OLED display panel

Info

Publication number: CN111192904A
Application number: CN202010011451.0A
Authority: CN
Inventors: 闫宇
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2020-01-06
Filing date: 2020-01-06
Publication date: 2020-05-22

Abstract

The application provides an OLED display panel, which comprises a driving circuit layer, a pixel defining layer, a first common layer, a light emitting material layer, a second common layer and a blocking part, wherein the pixel defining layer is formed on one side of the driving circuit layer and comprises a plurality of sub-pixel defining parts, and a sub-pixel area is formed between every two adjacent sub-pixel defining parts; the first common layer is formed in the sub-pixel area and extends to cover the sub-pixel definition part; the light-emitting material layer is formed on one side, far away from the driving circuit layer, of the first common layer and is positioned in the sub-pixel area; the second common layer is formed on one side of the luminescent material layer far away from the drive circuit layer and extends to cover the sub-pixel defining part; the blocking portion is disposed on the at least one sub-pixel defining portion and in at least one of the first common layer and the second common layer. By arranging the blocking part on at least one sub-pixel defining part, the transmission channel of carriers between adjacent sub-pixels is blocked, so that the phenomenon of crosstalk between the adjacent sub-pixels is relieved.

Description

OLED display panel

Technical Field

The application relates to the technical field of display, in particular to an OLED display panel.

Background

The OLED device utilizes electrons and holes to be compounded in a light-emitting functional layer to emit light, other functional layers except light-emitting material layers of three colors in the light-emitting functional layer of each pixel are all common layers at present, and when only a single sub-pixel emits light, current carriers can be diffused into adjacent sub-pixels which do not need to emit light, so that the sub-pixels emit light. Carrier diffusion to non-emitting sub-pixels affects device efficiency, and adjacent sub-pixel crosstalk affects color accuracy, thereby affecting product quality.

Therefore, the conventional OLED display panel has a technical problem that crosstalk occurs between adjacent sub-pixels, and needs to be improved.

Disclosure of Invention

The application provides an OLED display panel to alleviate the technical problem that adjacent sub-pixels in the existing OLED display panel generate crosstalk.

In order to solve the above problems, the technical solution provided by the present application is as follows:

the application provides an OLED display panel, includes:

a driving circuit layer;

the pixel definition layer is formed on one side of the driving circuit layer and comprises a plurality of sub-pixel definition parts, and a sub-pixel area is formed between every two adjacent sub-pixel definition parts;

a first common layer formed in the sub-pixel region and extending to cover the sub-pixel defining part;

the light-emitting material layer is formed on one side, far away from the driving circuit layer, of the first common layer and is positioned in the sub-pixel area;

the second common layer is formed on one side, far away from the driving circuit layer, of the light-emitting material layer and extends to cover the sub-pixel defining part;

and a blocking part disposed on at least one of the sub-pixel defining parts and located in at least one of the first and second common layers.

In the OLED display panel of the present application, the blocking portion is a notch.

In the OLED display panel of the present application, the blocking part is an insulating member.

In the OLED display panel, the height of the blocking part is larger than or equal to the thickness of the film layer where the blocking part is located.

In the OLED display panel of the present application, the width of the blocking part is less than or equal to the width of the sub-pixel defining part.

In the OLED display panel of the present application, the length of the blocking portion is greater than or equal to the length of the sub-pixel region.

In the OLED display panel, the OLED display panel comprises a plurality of pixels distributed in an array, each pixel comprises at least three sub-pixels, and the barrier part is arranged between at least two adjacent sub-pixels in the pixels.

In the OLED display panel of this application, OLED display panel includes a plurality of pixels that the array distributes, and every pixel includes at least three sub-pixel, the pixel includes that the sub-pixel interval is provided with the first pixel of separation portion and does not set up the second pixel of separation portion, wherein be provided with between at least two adjacent sub-pixels in the first pixel the separation portion.

In the OLED display panel of the present application, the first pixels and the second pixels are alternately arranged in a first direction in the OLED display panel.

In the OLED display panel, the barrier part is arranged between at least two adjacent pixels.

The beneficial effect of this application does: the application provides an OLED display panel, which comprises a driving circuit layer, a pixel defining layer, a first common layer, a light emitting material layer, a second common layer and a blocking part, wherein the pixel defining layer is formed on one side of the driving circuit layer and comprises a plurality of sub-pixel defining parts, and a sub-pixel area is formed between every two adjacent sub-pixel defining parts; the first common layer is formed in the sub-pixel area and extends to cover the sub-pixel definition part; the light-emitting material layer is formed on one side, far away from the driving circuit layer, of the first common layer and is positioned in the sub-pixel area; the second common layer is formed on one side of the light-emitting material layer, which is far away from the driving circuit layer, and extends to cover the sub-pixel defining part; the blocking portion is disposed on at least one of the sub-pixel defining portions and in at least one of the first and second common layers. According to the OLED display panel, the blocking part is arranged on the at least one sub-pixel defining part, so that the common layers of the adjacent sub-pixels are separated, the transmission channel of carriers between the adjacent sub-pixels is blocked when the OLED display panel is electrified subsequently, when one sub-pixel emits light, the sub-pixel adjacent to the sub-pixel cannot be influenced by the carriers and also emits light, and therefore the phenomenon of crosstalk between the adjacent sub-pixels is relieved.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of an OLED display panel in the prior art.

Fig. 2 is a schematic view of a first structure of an OLED display panel according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of a second OLED display panel according to an embodiment of the present disclosure.

Fig. 4 is a schematic top view of an OLED display panel according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

The application provides an OLED display panel and a display device to alleviate the technical problem that crosstalk occurs in adjacent sub-pixels in the existing OLED display panel.

Fig. 2 is a schematic view of a first structure of an OLED display panel according to an embodiment of the present disclosure. The OLED display panel includes a driving circuit layer, a pixel defining layer, a first common layer 114, a light emitting material layer 115, a second common layer 116, and a barrier portion 119. The pixel defining layer is formed at one side of the driving circuit layer and includes a plurality of sub-pixel defining parts 113, and a sub-pixel region is formed between adjacent sub-pixel defining parts 113. The first common layer 114 is formed in the sub-pixel region and extends to cover the sub-pixel defining portion 113. The light emitting material layer 115 is formed on a side of the first common layer 114 away from the driving circuit layer and is located in the sub-pixel region. The second common layer 116 is formed on the side of the light emitting material layer 115 away from the driving circuit layer, and extends to cover the sub-pixel defining portion 113. The barrier portion 119 is disposed on at least one of the sub-pixel defining portions 113, and is located in at least one of the first and second

common layers

114 and 116.

The driving circuit layer includes a substrate 101 and a plurality of thin film transistors, for example, a bottom gate thin film transistor, the thin film transistor includes an active layer 102, a first gate insulating layer 103, a first metal layer 104, a second gate insulating layer 105, a second metal layer 106, an interlayer dielectric layer 107, a planarization layer 108, a source drain layer, and a passivation layer 111, which are stacked on the substrate 101.

When the OLED display panel is a rigid panel, the substrate 101 is a rigid substrate, such as glass, transparent resin, or the like; when the OLED display panel is a flexible panel, the substrate 101 is a flexible substrate, such as polyimide, polycarbonate, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, polyarylate, or glass fiber reinforced plastic, and is formed on a glass substrate by coating, and after the preparation of the display panel is completed, the glass substrate is peeled off, and the peeling method may be laser peeling.

A buffer layer (not shown) is typically formed on the substrate 101, and the material of the buffer layer may be inorganic material such as silicon oxide, silicon nitride, etc.

The active layer 102 is formed on the buffer layer, and the material of the active layer 102 is a metal oxide, such as Indium Gallium Zinc Oxide (IGZO), but not limited thereto, and may also be one or more of Aluminum Zinc Oxide (AZO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), boron-doped zinc oxide (BZO), and magnesium-doped zinc oxide (MZO). Furthermore, the active layer 102 may also be a polysilicon material or other materials.

The first gate insulating layer 103 is formed on the active layer, and the material of the first gate insulating layer 103 may be an inorganic material such as silicon oxide or silicon nitride.

The first metal layer 104 is formed on the first gate insulating layer 103, and the material of the first metal layer 104 may be, but not limited to, molybdenum, aluminum, copper, chromium, tungsten, titanium, tantalum, and alloys containing the same, and the material thereof is not particularly limited herein. The first metal layer 104 is patterned by an etching process to form a gate electrode of each thin film transistor and a first plate of the storage capacitor.

The second gate insulating layer 105 is formed on the first metal layer 104, and the material of the second gate insulating layer 105 may be an inorganic material such as silicon oxide, silicon nitride, or the like.

The second metal layer 106 is formed on the second gate insulating layer 105, and the material of the second metal layer 106 may be, but not limited to, molybdenum, aluminum, copper, chromium, tungsten, titanium, tantalum, and alloys containing the same, and the material thereof is not particularly limited herein. The second metal layer 106 is patterned to form a second plate of the storage capacitor.

An interlayer dielectric layer 107 is formed on the second metal layer 106, and the material of the interlayer dielectric layer 107 may be an inorganic material such as silicon oxide or silicon nitride.

A passivation layer 108 is formed on the interlayer dielectric layer 107, and a material of the passivation layer 111 may be at least one of silicon oxide and silicon nitride.

The source and drain layers are formed on the passivation layer 108, the source and drain layers may be made of, but not limited to, mo, al, cu, cr, w, ti, ta, and alloys containing these, and the source and drain layers are patterned by an etching process to form the source 108 and the drain 109 of each tft. The source electrode 108 and the drain electrode 109 are connected to the active layer 102 through a first via hole.

The planarization layer 111 is formed on the source drain layer, and the material of the planarization layer 111 may be photoresist, and is formed on the source drain layer by coating.

The structure of each layer in the driving circuit layer is described by taking a bottom gate thin film transistor as an example, but of course, the structure of the driving circuit layer is not limited thereto, and a top gate thin film transistor may be included.

First electrodes 112 are formed on the driving circuit layer, the first electrodes 112 are distributed on the planarization layer 111 in an array manner, an opening area is formed between adjacent first electrodes 112, and the first electrodes 112 are connected with the drain electrode of the thin film transistor through second through holes. In the present embodiment, the first electrode 112 is an anode.

The pixel defining layer is formed on the driving circuit layer and includes a plurality of sub-pixel defining parts 113, each sub-pixel defining part 113 is located in an opening area between adjacent first electrodes 112, a sub-pixel area is formed between adjacent sub-pixel defining parts 113, and the sub-pixel area exposes the underlying first electrode 112.

The first common layer 114, the light emitting material layer 115, and the second common layer 116 collectively constitute a light emitting functional layer, in which an organic light emitting material is disposed in the light emitting material layer 115. In the sub-pixels of different colors, the organic light emitting material in the light emitting material layer 115 is different in kind.

The second electrode 117 is formed on the second common layer 116, covering the sub-pixel region and the sub-pixel defining part 113. In the present embodiment, the second electrode 117 is a cathode.

A retaining wall 118 is usually disposed on the second electrode 117, and when the subsequent OLED display panel is packaged, the retaining wall 118 and the packaging layer cooperate to block water and oxygen from entering.

In the embodiment, the first common layer 114 is a hole transport layer, the second common layer 116 is an electron transport layer, and under the action of an external electric field, holes injected from the anode and electrons injected from the cathode both pass through the electron transport layer and the hole transport layer as carriers to reach the light emitting material layer 115, and excitons are formed in the light emitting material layer 115 in a coincidental manner, and energy is released in the form of light energy.

The OLED display panel generally includes a plurality of pixels arranged in an array, each pixel includes at least three sub-pixels, the first electrode 112, the first common layer 114, the light emitting material layer 115, the second common layer 116 and the second electrode 117 in each sub-pixel region form one sub-pixel, and the sub-pixels emit light under the driving of the thin film transistors in the driving circuit layer.

In this embodiment, each pixel includes three sub-pixels, the pixel structure is RGB, and fig. 2 shows a structure of three sub-pixels in one pixel, where the red sub-pixel, the green sub-pixel, and the blue sub-pixel are sequentially arranged from left to right. However, the present application is not limited thereto, and each pixel may further include more sub-pixels, such as RGBW structure.

The barrier portion 119 may be provided in at least one of the first common layer 114 and the second common layer 116, that is, may be provided only in the first common layer 114, may be provided only in the second common layer 116, or may be provided in both the first common layer 114 and the second common layer 116. The blocking portion 119 is disposed on at least one of the sub-pixel defining portions 113, i.e., between at least two adjacent sub-pixels.

Fig. 1 is a schematic structural diagram of an OLED display panel in the prior art. In the prior art, the first common layer 114 and the second common layer 116 of the OLED display panel both cover the sub-pixel region and the sub-pixel defining portion 113, that is, the first common layer 114 and the second common layer 116 between adjacent sub-pixels are connected.

When the OLED display panel displays, each sub-pixel is controlled to emit light independently, when a certain sub-pixel needs to emit light, the sub-pixel receives a driving signal to emit light, and other sub-pixels which do not need to emit light do not receive the driving signal, so that the sub-pixels do not emit light, and the sub-pixels are controlled independently. However, since a Common Metal Mask (CMM) is usually used in the OLED display panel manufacturing process, the first Common layer 114 and the second Common layer 116 between adjacent sub-pixels are connected to each other. At this time, when a certain sub-pixel emits light, the transmission of carriers occurs in the first common layer 114 and the second common layer 116 corresponding to the sub-pixel, and when a part of the carriers are transmitted to the adjacent sub-pixel along the first common layer 114 or the second common layer 116, the adjacent sub-pixel also emits light, so that the crosstalk of the adjacent sub-pixel affects the color calibration, thereby affecting the quality of the final product.

In fig. 2, in this embodiment, the blocking portion 119 is disposed in at least one of the first common layer 114 and the second common layer 116, the film layer where the blocking portion 119 is located is divided into two portions, namely, a left portion and a right portion, by the blocking portion 119, and the two portions are blocked by the blocking portion 119, so that a transmission channel of carriers is blocked, and the carriers do not flow into adjacent sub-pixels along the channel to cause the adjacent sub-pixels to emit light, thereby alleviating a crosstalk phenomenon between the adjacent sub-pixels and improving the quality of the OLED display panel.

The blocking portion 119 may be formed in various ways. In one embodiment, the blocking portion 119 is a notch. As shown in fig. 2, the barrier portion 119 is provided in the first common layer 114, and in fig. 2, a red sub-pixel, a green sub-pixel, and a blue sub-pixel are provided in this order from left to right, and the first common layer 114 between the red sub-pixel and the green sub-pixel is formed with a notch, and can be formed by using a Fine Metal Mask (FMM) having a low aperture ratio. Through setting up the breach, obstructed the carrier transmission passageway between red subpixel and the green subpixel, consequently do not influence green subpixel and blue subpixel when red subpixel is luminous, realized that red subpixel is luminous alone.

In another embodiment, the barrier 119 is an insulating member. When the carriers of the red sub-pixel are transmitted to the green sub-pixel, the carriers are blocked by the insulating component and cannot be transmitted continuously, so that the independent light emission of the red sub-pixel is realized.

In one embodiment, the height of the blocking portion 119 is greater than or equal to the thickness of the film layer where the blocking portion 119 is located, and the film layer where the blocking portion 119 is located is divided into two portions on two sides of the blocking portion 119, and the film layer is not located above the blocking portion 119, so that the film layer where the blocking portion 119 is located is cut off, and carriers do not diffuse from the location where the blocking portion 119 is located. When the blocking portion 119 is a notch, the height of the blocking portion 119 is equal to the height of the first common layer 114, and when the blocking portion 119 is an insulating member, the height of the blocking portion 119 is greater than or equal to the height of the first common layer 114.

Fig. 4 is a schematic top view of an OLED display panel according to an embodiment of the present disclosure. The OLED display panel includes a plurality of pixels distributed in an array, each pixel includes at least three sub-pixels, which are a red sub-pixel 11, a green sub-pixel 12, and a blue sub-pixel 13 in this embodiment.

In one embodiment, the width of the blocking portion 119 is less than or equal to the width of the sub-pixel defining portion. Taking the first row of the first pixel in fig. 4 as an example, the barrier 119 is disposed between the red sub-pixel 11 and the green sub-pixel 12, and the width W1 of the barrier 119 is smaller than or equal to the width W2 between the red sub-pixel 11 and the green sub-pixel 12.

The portions of the first and second

common layers

114 and 116 corresponding to the respective sub-pixel regions need to perform the function of carrier transfer into the light-emitting material layer 115 corresponding to each sub-pixel, and therefore the width W1 of the barrier section 119 cannot exceed the width W2 between the red and

green sub-pixels

11 and 12 so as not to affect the light-emitting effect of the respective sub-pixels themselves.

In one embodiment, the length of the barrier 119 is greater than or equal to the length of the sub-pixel region. The length L2 of each sub-pixel region is equal to the length of each sub-pixel in fig. 4, when the length L1 of the blocking portion 119 is greater than or equal to the length L2 of the sub-pixel region, the carrier channel between adjacent sub-pixels is completely blocked, and in the lateral direction in fig. 4, the carriers in the sub-pixel region of the red sub-pixel 11 do not diffuse into the sub-pixel region of the green sub-pixel 12, achieving individual light emission of the red sub-pixel 11.

When the height of the blocking portion 119 is greater than or equal to the thickness of the film layer where the blocking portion 119 is located, the width of the blocking portion 119 is less than or equal to the width of the sub-pixel defining portion, and the length of the blocking portion 119 is greater than or equal to the length of the sub-pixel region, the blocking effect is optimal.

There are various ways of disposing the blocking portion 119 in the entire OLED display panel. In one embodiment, the OLED display panel includes a plurality of pixels distributed in an array, each pixel includes at least three sub-pixels, and the barriers 119 are disposed between at least two adjacent sub-pixels in the pixel, that is, the barriers 119 are disposed in all pixels in the entire OLED display panel.

As shown in fig. 4, each pixel includes three sub-pixels, and barriers 119 may be disposed at two places between the three sub-pixels, i.e., on the sub-pixel defining section 113 between the red sub-pixel 11 and the green sub-pixel 12, and on the sub-pixel defining section 113 between the green sub-pixel 12 and the blue sub-pixel 13. The barrier 119 may be disposed only between the red sub-pixel 11 and the green sub-pixel 12, so as to realize the independent light emission of the red sub-pixel 11, and the specific structure is shown in fig. 2; the barrier portion 119 may be provided only between the green sub-pixel 12 and the blue sub-pixel 13 to realize the independent light emission of the blue sub-pixel 13; it is also possible to provide the barriers 119 between the red sub-pixel 11 and the green sub-pixel 12 and between the green sub-pixel 12 and the blue sub-pixel 13 at the same time, so that the red sub-pixel 11, the green sub-pixel 12 and the blue sub-pixel 13 can emit light individually, as shown in fig. 3 and the second pixel in the first row in fig. 4.

Since the pixels are distributed in the OLED display panel in an array, when the blocking portions 119 are disposed in all the pixels, one blocking portion 119 may be disposed corresponding to the same column of sub-pixels, where the length L1 of the blocking portion 119 is greater than the sum of the lengths of all the sub-pixel regions in the column of sub-pixels, and carriers in the column of sub-pixels on the left side of the blocking portion 119 cannot diffuse into the column of sub-pixels on the right side of the blocking portion 119.

Further, since crosstalk due to carrier transfer also occurs between different pixels, a barrier portion 119 may be provided between at least two adjacent pixels, and as shown in fig. 4, a barrier portion 119 may be provided between horizontally adjacent pixels and between vertically adjacent pixels.

When all the sub-pixels in the whole OLED display panel need to emit light independently, the blocking portions 119 may be disposed between all the sub-pixels in each pixel, and the blocking portions 119 are disposed between every two adjacent pixels, at this time, the blocking portions 119 are in a form of cross arrangement of multiple rows and multiple columns, and the common layer of each sub-pixel is isolated from the common layers of the sub-pixels adjacent to the four sides thereof.

In another embodiment, the pixel includes a first pixel having a blocking portion 119 disposed between sub-pixel regions and a second pixel having no blocking portion 119 disposed between at least two adjacent sub-pixels in the first pixel 119, and only one blocking portion 119 may be disposed in the first pixel 119, or two blocking portions 119 may be disposed in the first pixel 119, and the specific structure is as shown in fig. 2 and fig. 3. At this time, the barrier portion 119 is provided in only some of the pixels.

There are various arrangements of the first pixels and the second pixels. In one embodiment, the first pixels and the second pixels are alternately arranged along a first direction, which is a direction of a long side or a short side of the OLED display panel. In fig. 4, the first direction may be the horizontal direction in fig. 4, where the first pixels are odd columns and the second pixels are even columns, or the first pixels are even columns and the second pixels are odd columns; the first direction may also be the vertical direction in fig. 4, in which case the first pixels are odd-numbered lines and the second pixels are even-numbered lines, or the first pixels are even-numbered lines and the second pixels are odd-numbered lines.

In another embodiment, the first pixels and the second pixels are arranged in a spaced array, that is, the second pixels are arranged around each first pixel, and the first pixels are arranged around each second pixel.

Similarly, crosstalk due to carrier transfer also occurs between different pixels, and therefore, the blocking portion 119 may be provided between at least two adjacent pixels, as shown in fig. 4, and the blocking portion 119 may be provided between horizontally adjacent pixels and between vertically adjacent pixels.

As can be seen from the above embodiments, the blocking portion 119 may be disposed between any two adjacent sub-pixels, and block a carrier transport channel between the two sub-pixels, thereby realizing individual light emission control for each sub-pixel. A designer skilled in the art can select a specific arrangement position of the blocking portion 119 as needed to realize accurate light emission control for each sub-pixel.

The application also provides a display device, which comprises an OLED display panel and an external drive chip bound with the OLED display panel, wherein the OLED display panel comprises a drive circuit layer, a pixel definition layer, a first common layer, a light-emitting material layer, a second common layer and a blocking part, the pixel definition layer is formed on one side of the drive circuit layer and comprises a plurality of sub-pixel definition parts, and a sub-pixel area is formed between every two adjacent sub-pixel definition parts; the first common layer is formed in the sub-pixel area and extends to cover the sub-pixel definition part; the light-emitting material layer is formed on one side, far away from the driving circuit layer, of the first common layer and is positioned in the sub-pixel area; the second common layer is formed on one side of the luminescent material layer far away from the drive circuit layer and extends to cover the sub-pixel defining part; the blocking portion is disposed on the at least one sub-pixel defining portion and in at least one of the first common layer and the second common layer.

In one embodiment, the blocking portion is a notch.

In one embodiment, the barrier is an insulating member.

In one embodiment, the height of the barrier is greater than or equal to the thickness of the film layer on which the barrier is located.

In one embodiment, the width of the blocking portion is less than or equal to the width of the sub-pixel defining portion.

In one embodiment, the length of the blocking portion is greater than or equal to the length of the sub-pixel region.

In one embodiment, the OLED display panel includes a plurality of pixels distributed in an array, each pixel includes at least three sub-pixels, and barriers are disposed between at least two adjacent sub-pixels in the pixel.

In one embodiment, the OLED display panel includes a plurality of pixels distributed in an array, each pixel includes at least three sub-pixels, the pixels include a first pixel having a blocking portion disposed between the sub-pixels and a second pixel having no blocking portion, and the blocking portion is disposed between at least two adjacent sub-pixels in the first pixel.

In one embodiment, in the OLED display panel, the first pixels and the second pixels are alternately arranged in the first direction.

In one embodiment, a barrier is disposed between at least two adjacent pixels.

The display device can be any product or component with a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer and the like. By arranging the blocking part in the OLED display panel in the display device, the common layers of the adjacent sub-pixels are separated, and when the OLED display panel is electrified subsequently, the transmission channel of carriers between the adjacent sub-pixels is blocked, when one sub-pixel emits light, the sub-pixel adjacent to the sub-pixel can not be influenced by the carriers and also emits light, so that the phenomenon of crosstalk between the adjacent sub-pixels is relieved.

According to the above embodiments:

the OLED display panel comprises a driving circuit layer, a pixel defining layer, a first common layer, a light emitting material layer, a second common layer and a blocking portion, wherein the pixel defining layer is formed on one side of the driving circuit layer and comprises a plurality of sub-pixel defining portions, and a sub-pixel area is formed between every two adjacent sub-pixel defining portions; the first common layer is formed in the sub-pixel area and extends to cover the sub-pixel definition part; the light-emitting material layer is formed on one side, far away from the driving circuit layer, of the first common layer and is positioned in the sub-pixel area; the second common layer is formed on one side of the luminescent material layer far away from the drive circuit layer and extends to cover the sub-pixel defining part; the blocking portion is disposed on the at least one sub-pixel defining portion and in at least one of the first common layer and the second common layer. According to the OLED display panel, the blocking part is arranged on the at least one sub-pixel defining part, so that the common layers of the adjacent sub-pixels are separated, the transmission channel of carriers between the adjacent sub-pixels is blocked when the OLED display panel is electrified subsequently, when one sub-pixel emits light, the sub-pixel adjacent to the sub-pixel cannot be influenced by the carriers and also emits light, and therefore the phenomenon of crosstalk between the adjacent sub-pixels is relieved.

In summary, although the present application has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be determined by the appended claims.

Claims

1. An OLED display panel, comprising:

a driving circuit layer;

2. The OLED display panel of claim 1, wherein the dam is a notch.

3. The OLED display panel of claim 1, wherein the barrier is an insulating member.

4. The OLED display panel of claim 1, wherein the height of the barriers is greater than or equal to the thickness of the film layer in which the barriers are located.

5. The OLED display panel of claim 1, wherein the barrier portion has a width less than or equal to a width of the sub-pixel defining portion.

6. The OLED display panel of claim 1, wherein the length of the blocking portion is greater than or equal to the length of the sub-pixel region.

7. The OLED display panel of claim 1, wherein the OLED display panel comprises a plurality of pixels distributed in an array, each pixel comprising at least three sub-pixels, at least two adjacent sub-pixels of the pixels having the barriers disposed therebetween.

8. The OLED display panel of claim 1, wherein the OLED display panel comprises a plurality of pixels distributed in an array, each pixel comprising at least three sub-pixels, the pixels comprising a first pixel having the blocking portion disposed therebetween and a second pixel having no blocking portion disposed therebetween, wherein the blocking portion is disposed between at least two adjacent sub-pixels of the first pixel.

9. The OLED display panel of claim 8, wherein the first pixels and the second pixels are alternately arranged in a first direction in the OLED display panel.

10. The OLED display panel according to any one of claims 7 or 8, wherein the barrier portion is disposed between at least two adjacent pixels.