CN111183748B - Error code resisting method based on cyclic redundancy check and erasure correction coding - Google Patents
Error code resisting method based on cyclic redundancy check and erasure correction coding Download PDFInfo
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- CN111183748B CN111183748B CN201318009100.7A CN201318009100A CN111183748B CN 111183748 B CN111183748 B CN 111183748B CN 201318009100 A CN201318009100 A CN 201318009100A CN 111183748 B CN111183748 B CN 111183748B
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Abstract
The invention discloses an error code resisting method based on cyclic redundancy check and erasure code, belonging to the technical field of wireless link digital measurement and control communication with random error codes or burst error codes, and the method comprises the following steps: adding a rapid cyclic redundancy check at a coding end according to a fixed code stream length, adding an error correction monitoring code to the cyclic redundancy check code, performing rapid Van der Monte erasure coding on bytes with a certain length according to columns, finally sending the coded data into a channel for transmission according to a row-first mode, and decoding and recovering the original data at a decoding end according to a corresponding mode. The method can be applied to the fields of high-compression-ratio video code streams which are particularly sensitive to channel error codes, important data protection transmitted in wireless channels with high error rates and the like. The invention enables the decoding end to quickly and timely find and correct the data generating the error code, and has the advantages of large coding gain, small delay, low algorithm complexity and the like; and real-time processing basis is provided for further reducing the influence of error codes on the quality of the video image.
Description
Technical Field
The invention belongs to the technical field of wireless link digital communication with random bit errors or burst bit errors, relates to an error code resisting method based on cyclic redundancy check and erasure coding, and is particularly suitable for important data protection which has higher requirements on time delay and is particularly sensitive to bit errors and transmitted in a wireless link.
Background
With the rapid development of communication technology and network technology, digital communication systems are being widely used. However, any communication network cannot guarantee a completely reliable transmission process, in particular a wireless network which has become widely used in recent years. Because the error rate of a communication link is high due to the influence of channel fading, interference, multipath transmission and the like, the transmitted data code stream is required to have high channel error resistance in data communication on a wireless channel with burst errors and random errors, and the transmitted data code stream has high error recovery capability after errors occur.
The current anti-error technology proposed for channel error code mainly includes Automatic Repeat Request (ARQ-Automatic Repeat Request); forward error correction (FEC-Forward error correction); and a hybrid Error Correction (HEC-Hybird Error Correction) mode and the like. The sending end of the automatic repeat request mode sends an error detection code with certain error detection capability, and once a receiving end detects an error in a received code word, the receiving end informs the sending end of retransmitting the code word through a feedback channel until the code word is correctly received. The advantage of ARQ is that the coding and decoding equipment is simple; under a certain redundancy code element, the error detection capability of the error detection code is much higher than the error correction capability of the error correction code, so that the error correction capability of the whole system is extremely strong, and an extremely low error rate can be obtained; the error detection capability of the error detection code is basically irrelevant to the change of channel interference, so the system has strong adaptability and is particularly suitable for the environment with high error rate. However, ARQ requires a feedback channel, is generally suitable for point-to-point communication, and requires that a source can control, and both ends of a system transceiver must cooperate and cooperate closely, so that a control circuit in this manner is complicated. The FEC mode does not need a feedback channel, can carry out simulcast communication from one user to a plurality of users, has better decoding real-time performance, and has simpler control circuit than ARQ. FEC has many kinds, such as BCH code and RS code, and they have excellent algebraic structure and properties, and have a fast decoding algorithm with small complexity, so that they are widely used. The mixed error correction mode has the characteristics of forward error correction and error detection retransmission, obviously needs a feedback channel and complex decoding equipment, but can better exert the error detection and error correction performance of error control coding, and can still obtain lower error rate even in the complex channel.
When the airborne measurement and control system performs compression transmission on data acquired by a load, higher technical requirements on anti-interference and anti-error performance are provided. Firstly, the technical requirements of a measurement and control system can be met under the condition that the link error rate is high; secondly, the requirement of the measurement and control system on delay time is high, so that the transmission delay of the whole coding and decoding is as low as possible, and the complexity and the calculation amount of the error code resisting algorithm cannot be too high; finally, the measurement and control system is single link transmission under most conditions when carrying out load data transmission, and no feedback channel participates, which requires that an error code resistant protection measure with an ARQ mechanism cannot participate.
Disclosure of Invention
The invention aims to solve the problems caused by random bit errors and burst bit errors in the channel. Aiming at the defects in the background technology, an error code resisting method based on cyclic redundancy check and erasure coding is provided, so that data with error codes can be quickly and efficiently found and recovered at a decoding end, the error code resisting performance of data transmitted in a channel is greatly improved, and a basis for implementing processing is provided for further reducing the influence of the error codes on important data. The method can be applied to high-compression-ratio video code streams which are particularly sensitive to channel error codes, important data protection transmitted in wireless channels with high error rates and the like.
The purpose of the invention is realized as follows: an error code resisting method based on cyclic redundancy check and erasure code is characterized by comprising the following steps:
and (3) a coding end:
(1) framing the transmitted data after the information source coding at a coding end;
(2) adding 3 erasure correcting coding frames after every 17 frames of data;
(3) adding 8-bit cyclic redundancy check codes at the tail end of each frame of data;
(4) adding 8 bit supervisory bits at the end of the 8 bit cyclic check code;
and a decoding end:
(5) carrying out 1-bit error correction judgment of cyclic redundancy check on the received data at a decoding end, and if no error exists, directly turning to the step (6); if the error exists, recovering the cyclic redundancy check code through 8-bit supervisory bits after the cyclic redundancy check code, and then turning to the step (6);
(6) judging each frame of data by using a cyclic redundancy check code; if the error exists, marking is carried out, and then the step (7) is carried out; if no error exists, directly switching to the step (8);
(7) recovering data frames with error codes in 17 frames of data by using any 2 frames without errors in 3 frames of erasure correcting coding frames; then, turning to the step (8);
(8) carrying out source decoding processing;
and completing error code resistance based on cyclic redundancy check and erasure coding.
The cyclic redundancy check coding and the erasure code are calculated in a lookup table mode.
Compared with the prior art, the invention has the beneficial effects that:
(1) the error code resisting method disclosed by the invention greatly improves the error code resisting capability of the transmission data in the wireless link;
(2) the invention has small encoding and decoding complexity and low time delay, and is very suitable for the technical requirements of an airborne measurement and control system.
(3) The invention can realize higher coding gain, has simple structure and low computation amount, and is very suitable for channel transmission with higher random bit errors and burst bit errors.
Drawings
FIG. 1 is a block diagram of the application of the present invention in a communication system;
FIG. 2 is a block diagram of the overall flow of an error resilient method;
FIG. 3 is a diagram of a (12, 4) cyclic redundancy coding 1-bit error correction pattern;
fig. 4 is a schematic diagram of a format of a data packet to be transmitted after being encoded.
Detailed Description
The present invention will be further described with reference to fig. 1 to 4.
An error code resisting method based on cyclic redundancy check and erasure code is characterized by comprising the following steps:
and (3) a coding end:
(1) framing the transmitted data after the information source coding at a coding end;
fig. 1 shows a wireless communication system to which the present invention is applied, and an algorithm according to the present invention performs erasure coding in a data frame structure, where each frame of data has a total of 250 bytes for processing. The whole algorithm structure flow is shown in fig. 2.
(2) Adding 3 erasure correcting coding frames after every 17 frames of data;
for data after framing, the erasure coding of the invention adopts a fast Van der Waals erasure coding technology.
To facilitate description of the related art in the encoding process, let the data matrix to be encoded be Dk×mK represents the number of packets, and m represents how many elements each packet contains.Then D isk×mThe matrix of (a) is represented by:
wherein the vector d11d12d13… d1mRepresenting a frame of data, Dk×mThe matrix after the van der waals matrix erasure coding is represented as En×mG is transformed into a unit matrix of K order when G is changed into GDn×mThe following steps are changed:
let ci，j＝ai，1×d1，j+ai，2×d2，j+ai，3×d3，j+…+ai，k×d1，kThen E isn×mCan be expressed as:
c denotes an erasure coded value.
In the actual encoding process, the size of each frame of encoded data is 250 bytes, and 3 encoding verification frames (which are provided for the decoding end and belong to the supervision frame) are added after each 17 encoded data frames. Since erasure coding is at GF (2)8) Operation over Galois field, encoding the resulting matrix E20×250The first 17 rows of data packets in the data packet are original data packets which can be directly copied to E during encoding20×250In the matrix, the key point in coding is to calculate ci，jAnd (4) elements. Due to ci，j＝ai，1×d1，j+ai，2×d2，j+ai，3×d3，j+…+ai，k×d1，kTo increase the speed, two code tables gf _ exp are provided]And gf _ log [ 2 ]]，gf_exp[i]is stored as alphaidecimal number corresponding to vector, e.g. α9The vector in GF (28) is expressed as (01011100), then GF _ exp[9]The corresponding decimal number is 92, i.e. gf _ exp [9 ]]＝92＝0x5c。gf_log[]The element stored in (1) is the power exponent number corresponding to decimal number, i.e. gf _ log [ gf _ exp [9 ]]]9. By constructing the two coding tables in advance, only the two coding tables need to be inquired during coding and decoding, so that the data calculation amount in the coding and decoding can be greatly reduced.
(3) Adding 8-bit cyclic redundancy check codes at the tail end of each frame of data;
to avoid calculating complex syndromes at the decoding end and finding the root of the wrong-position polynomial. At the encoding end, an 8-bit cyclic redundancy check is performed on each row of data, and a check value CC is placed after each row. How to quickly calculate the validation value CC and the erasure code value C is the key to reduce the amount of calculation of the algorithm. The algorithm here uses a table lookup for fast calculation. When 8-bit cyclic redundancy check is carried out on a binary number, the binary number is left shifted by 8 bits, then the polynomial is generated by dividing the binary number by the 8-bit cyclic redundancy check, and the obtained residue is the cyclic redundancy check code. The 8-bit cyclic redundancy generator polynomial is Gcrc8＝x8+x7+x4+x3+ x +1, a binary number can be represented in bytes as:
m(x)＝m n28n+m n-128(n-1)+mn-2×28(n-2)+…+m 128+m0(1)
and carrying out 8-bit cyclic redundancy coding on the binary number, firstly, moving the (1) left overall by 8 bits, and then dividing by a generator polynomial to obtain:
the residue equation is the cyclic redundancy check value, and in order to quickly calculate the cyclic redundancy check value, the following are set:
wherein QnIs an integer, rnIs an 8-bit binary remainder. Bringing (3) into (2) yields:
simplified to the above formula (4)
Then setting:
same as (3), Qn-1Is an integer, rn-1For 8-bit binary remainder, substituting (5) into (4), and so on to obtain:
r0that is, the final 8-bit cyclic redundancy check code is obtained, (5) is a recurrence formula of the whole calculation process, which shows that the calculation of the byte check code can be represented as the cyclic redundancy check code of the last byte remainder check code and the byte sum. Therefore, in the invention, all cyclic redundancy check codes of 8-bit binary number are calculated and stored in a fixed table, and the calculation amount is reduced and the operation speed is improved by a table query mode.
(4) Adding 8 bit supervisory bits at the end of the 8 bit cyclic check code;
in order to avoid the reduction of coding gain caused by the error of the cyclic redundancy check code, after the cyclic redundancy check code is finished, an 8-bit error correcting code is added, so that the error code resistance of the cyclic redundancy check code is improved. After receiving the check code at the receiving end, the generator polynomial Gcrc8 is used to perform modulo-2 division, and if the remainder is 0, the codeword is error-free. If one bit is in error, the remainder is not 0, and the rest numbers are different from each other. It can be proved from the mathematical principle that the corresponding relation between the remainder and the error bit is only related to the code system and the generator polynomial, but not to the codeword (information bit) to be tested, and fig. 3 shows a (12, 4) cyclic redundancy coding 1-bit error correction mode diagram, where the error mode G (x) is 10011, and the 16-bit validity bit is subjected to the 0-complementing processing by 4 bits.
After erasure correction coding and cyclic redundancy check codes are carried out in the mode, a corresponding frame header suitable for decoding at a decoding end is added, and channel transmission can be carried out. The per packet data format for the incoming channel transmission is shown in fig. 4.
And a decoding end:
(5) carrying out 1-bit error correction judgment of cyclic redundancy check on the received data at a decoding end, and if no error exists, directly turning to the step (6); if the error exists, recovering the cyclic redundancy check code through 8-bit supervisory bits after the cyclic redundancy check code, and then turning to the step (6);
(6) judging each frame of data by using a cyclic redundancy check code; if the error exists, marking is carried out, and then the step (7) is carried out; if no error exists, directly switching to the step (8);
(7) recovering data frames with error codes in 17 frames of data by using any 2 frames without errors in 3 frames of erasure correcting coding frames; then, turning to the step (8);
in step (7), the decoding end determines whether the received data enters a decoding stage by searching the data packet frame header. When decoding, firstly, 1-bit error correction is carried out to determine whether the received cyclic redundancy check code is correct. If the check code is correct, the code is used to determine whether the frame data is correct by performing a cycle check coding on 250 bytes of the frame again and comparing whether the currently calculated value is consistent with the value recovered from receiving. If not, it shows that the frame data has error code, and makes corresponding identification. If the data is consistent, the frame data is error-free, and the data is skipped and not processed. Since the encoding uses (20, 17) erasure correction, the number of erroneous data in a column can be only one, but multiple erroneous data in a frame are allowed. The data received by the terminal is set as
In
Indicating that the byte data is erroneous, the erroneous row is marked after the cyclic redundancy check. The decoding end utilizes a row a in the generating matrixi，jConstructing a new generator matrix, calculating the new generator matrix and the received data
Obtaining a new erasure code matrix
If it is not
In (1)
And ci，jThe values are different, indicating that the column is in error.
Now to correct the second row, the matrix G is used first1And D1To obtain E1，
Reuse of one row a of the generator matrixi+1，jConstructing a new generator matrix and calculating the matrix
Comparison
And ck+2，1Value, if the same, indicates the value d 'corresponding to the column'2，jI.e. corrected correctly. This allows all erroneous values in the second row to be corrected. Other row errors are also corrected in the same manner.
The above description of the principles shows that three sets of parity frames ensure that at least two of them are correct, otherwise they cannot be decoded correctly.
(8) Carrying out source decoding processing;
and completing error code resistance based on cyclic redundancy check and erasure coding.
By performing the anti-error protection of the data in the above manner, the channel data error rate can be controlled from 1 × 10-5Channel reduction to 1 x 10-8The method is very suitable for high-compression-ratio video code streams which are particularly sensitive to channel errors, important data protection transmitted in a wireless link with a high error rate and the like.
Claims (2)
1. An error code resisting method based on cyclic redundancy check and erasure code is characterized by comprising the following steps:
and (3) a coding end:
(1) framing the transmitted data after the information source coding at a coding end;
(2) adding 3 erasure correcting coding frames after every 17 frames of data;
(3) adding 8-bit cyclic redundancy check codes at the tail end of each frame of data;
(4) adding 8-bit supervision bits at the tail end of the 8-bit cyclic redundancy check code;
and a decoding end:
(5) carrying out 1-bit error correction judgment of cyclic redundancy check on the received data at a decoding end, and if no error exists, directly turning to the step (6); if the error exists, recovering the cyclic redundancy check code through 8-bit supervisory bits after the cyclic redundancy check code, and then turning to the step (6);
(6) judging each frame of data by using a cyclic redundancy check code; if the error exists, marking is carried out, and then the step (7) is carried out; if no error exists, directly switching to the step (8);
(7) recovering data frames with error codes in 17 frames of data by using any 2 frames without errors in 3 frames of erasure correcting coding frames; then, turning to the step (8);
(8) carrying out source decoding processing;
and completing error code resistance based on cyclic redundancy check and erasure coding.
2. The error resilient method based on crc and erasure coding according to claim 1, wherein: the cyclic redundancy check coding and the erasure coding are calculated in a lookup table manner.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111478885A (en) * | 2020-03-16 | 2020-07-31 | 湖南遥昇通信技术有限公司 | Asymmetric encryption and decryption method, equipment and storage medium |
| CN114285734A (en) * | 2021-12-29 | 2022-04-05 | 广西电网有限责任公司柳州供电局 | Communication monitoring system of transmission line based on optical cable splice closure |
| CN116028260A (en) * | 2023-01-09 | 2023-04-28 | 海光信息技术股份有限公司 | Data processing method, processing device and storage system |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111478885A (en) * | 2020-03-16 | 2020-07-31 | 湖南遥昇通信技术有限公司 | Asymmetric encryption and decryption method, equipment and storage medium |
| CN111478885B (en) * | 2020-03-16 | 2022-05-06 | 湖南遥昇通信技术有限公司 | Asymmetric encryption and decryption method, equipment and storage medium |
| CN114285734A (en) * | 2021-12-29 | 2022-04-05 | 广西电网有限责任公司柳州供电局 | Communication monitoring system of transmission line based on optical cable splice closure |
| CN114285734B (en) * | 2021-12-29 | 2024-02-20 | 广西电网有限责任公司柳州供电局 | Communication monitoring system of transmission line based on optical cable splice box |
| CN116028260A (en) * | 2023-01-09 | 2023-04-28 | 海光信息技术股份有限公司 | Data processing method, processing device and storage system |
| CN116028260B (en) * | 2023-01-09 | 2024-02-27 | 海光信息技术股份有限公司 | Data processing method, processing device and storage system |
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