CN111179988B - 2bit memory unit structure and operation method - Google Patents
2bit memory unit structure and operation method Download PDFInfo
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- CN111179988B CN111179988B CN201911231904.4A CN201911231904A CN111179988B CN 111179988 B CN111179988 B CN 111179988B CN 201911231904 A CN201911231904 A CN 201911231904A CN 111179988 B CN111179988 B CN 111179988B
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Abstract
The invention discloses a 2bit memory cell structure, each cell comprises 2 storage tubes A and a selection tube, the memory cell can store 2bit data, the grid of the selection tube leads out a first word line forming the memory cell, the source and drain regions of the selection tube are respectively connected with the source or drain of the storage tube at two sides of the selection tube, and the other rest drains or sources of the storage tubes respectively form a first bit line and a second bit line of the memory cell; and leading out the grid electrodes of 2 storage tubes in the memory unit to form a second word line and a third word line, wherein the second word line and the third word line are also connected together. When the memory unit is programmed, a source end carrier injection mode is adopted; when reading data, the source end voltage of the storage tube is used for shielding the influence of the state of the storage tube A on the storage tube A when reading the storage tube A; when reading data, the reading voltage of the selection tube is larger than the grid voltage of the storage tube so as to increase the reading current.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit device design, in particular to a 2bit memory unit structure.
Background
FIG. 1 is a schematic diagram of a 2-bit memory cell, the whole memory cell is composed of 3 tubes: the word line comprises 2 completely symmetrical storage tubes (A and A) positioned on the left side and the right side and a selection tube (B) positioned in the middle, wherein the grids of the 3 tubes are connected together to be led out to form a word line WL, the left and the right symmetrical storage tubes A and A are respectively led out to form bit lines BL and BL, and the other two ends are respectively connected with the source and the drain of the selection tube. Suppose that the storage tube is defined to be turned off to be 0 (the turning-off means that the channel of the storage tube is not conducted when no voltage is applied to the storage tube), and is turned on to be 1 (the turning-on means that the channel of the storage tube is conducted when no voltage is applied to the storage tube, and a larger current exists); in a conventional storage mode, 1 storage unit stores 2 bits, each of the storage tubes a and a may be "0" or "1", and since the storage tubes a and a are completely symmetrical in structure, the storage and reading of a and a may be achieved by interchanging the operating voltages of the storage tubes a and a.
Fig. 2 shows a structural implementation of this memory, as can be seen, the gates of 3 tubes can be connected together by salicide, and the gates of the storage tubes are created by means of self-aligned sidewalls, by which the size of the storage tubes can be made small (<50 nm).
Fig. 3 is a layout implementation of the memory, and it can be known that the storage tube a and the storage tube a surround the selection tube by one turn and are connected together because the storage tube adopts a self-aligned side wall manner.
Watch 1
The first table shows the operating conditions of the memory cell, VPP represents the high gate voltage for Program using Hot Carrier Injection (HCI), and ONO electron film thickness is greater than that of the first table
And then, the voltage is usually greater than 7V, the specific voltage increases along with the increase of the film thickness, Vd is the voltage of a drain terminal corresponding to the storage tube in Program, and the Vd is generally between 1.5 and 5V.
VNH represents the negative voltage of the grid electrode during Erase, VPE represents the positive high voltage of the drain end of the storage tube, and when the thickness of the ONO electronic film is larger than that of the ONO electronic film
The difference between VPE and VNH is typically greater than 10V.
Vgs is the gate voltage at the time of Read, and Vs represents the source terminal voltage of the storage tube at the time of Read. The voltage of Vgs is related to the 0 and 1 discrimination of the storage tube, Vgs must be in the middle of the 0 and 1 threshold voltage discrimination of the storage tube. The Vs voltage is used to mask the effect of the storage tube a on the state of a when the storage tube a is read.
Watch two
The second table shows the operating conditions of a specific memory cell, wherein the thickness of the ONO layer of the memory medium layer is
Under the condition, the grid voltage reaches 11V during programming, and the drain voltage of the storage tube is 2.5V.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a 2-bit memory unit, wherein the grids of a storage tube and a selection tube are independently connected, so that the reading current of the memory unit can be improved.
In order to solve the problems, each unit of the 2-bit memory unit structure comprises 3 transistors, wherein each unit comprises 2 storage tubes and a selection tube, the memory unit can store 2-bit data, and each storage tube can store '0' or '1'.
A first word line WL of the memory unit is led out from the grid electrode of the selection tube, a source electrode and a drain electrode of the selection tube are respectively connected with source electrodes or drain electrodes of storage tubes on two sides of the selection tube, and the other rest drain electrodes or source electrodes of the storage tubes respectively form a first bit line and a second bit line of the memory unit;
and the grid electrodes of the 2 storage tubes in the memory unit are led out to form a second word line and a third word line, and the second word line and the third word line are also connected together.
The further improvement is that the selection tube and the two storage tubes are all devices with completely symmetrical structures.
The further improvement is that the voltages of the 2 storage tubes are exchanged to realize the storage and the reading of the two storage tubes respectively.
In a further improvement, when the memory unit is programmed, the grid voltage of the selection tube is smaller than that of the storage tube; when reading data, the grid voltage of the selection tube is larger than that of the storage tube so as to increase the reading current.
The further improvement is that during programming, a source end carrier injection mode is adopted.
In order to solve the above problems, the present invention provides a 2bit memory unit structure, which comprises three MOS transistors on a semiconductor substrate, including a selection transistor in the middle and storage transistors at two sides of the selection transistor, wherein the selection transistor and the storage transistors at two sides of the selection transistor share a source drain region;
the silicon surface of the selection tube positioned in the middle of the surface of the semiconductor substrate is provided with a gate dielectric layer, a polysilicon gate of the selection tube is arranged above the gate dielectric layer, and two ends of the gate dielectric layer extend upwards to wrap the side surface of the polysilicon gate of the selection tube;
the storage tube is positioned at two sides of the selection tube, an ONO (oxide-nitride-oxide) dielectric layer of the storage tube is arranged on the silicon surface of the gate dielectric layer close to the selection tube and serves as a charge storage layer, and a polysilicon gate of the storage tube is arranged above the ONO layer;
the inner side of the polycrystalline silicon grid of the storage tube is a part of the selection tube, which extends upwards from the grid dielectric layer, and the outer side of the polycrystalline silicon grid of the storage tube is a side wall;
a source region or a drain region of the storage tube is arranged in the substrate below the outer side of the polysilicon gate of the storage tube, and metal silicide is arranged above the source region or the drain region of the storage tube;
the polysilicon grid of the selection tube is provided with a dielectric layer, the polysilicon grids of the storage tubes at two sides extend upwards, and the height of the dielectric layer exceeds that of the polysilicon grid of the selection tube and extends to the position near the surface of the dielectric layer above the polysilicon grid of the selection tube.
The further improvement is that the selection tube and the storage tube are transistors with completely symmetrical structures, and the operating voltages of the two storage tubes can be interchanged.
In a further improvement, the storage tube is a SONOS storage tube.
The storage tube is manufactured by selecting a self-aligning side wall of the tube.
In a further improvement, the gate width of the storage tube is less than 50 nm.
In a further improvement, the polysilicon gates of the select transistors are respectively led out to serve as a first word line of the memory cell, the polysilicon gates of the left and right storage transistors are respectively led out to serve as a second word line and a third word line of the memory cell, and the unshared source regions or drain regions of the storage transistors are respectively led out to serve as a first bit line and a second bit line of the memory cell.
In a further improvement, the memory unit adopts a source terminal carrier injection mode during programming.
In order to solve the above problems, the present invention provides a 2bit memory unit structure, which comprises three MOS transistors on a semiconductor substrate, including a selection transistor in the middle and storage transistors at two sides of the selection transistor, wherein the selection transistor and the storage transistors at two sides of the selection transistor share a source drain region;
the silicon surface of the selection tube positioned in the middle of the surface of the semiconductor substrate is provided with a gate dielectric layer, a polysilicon gate of the selection tube is arranged above the gate dielectric layer, and two ends of the gate dielectric layer extend upwards to wrap the side surface of the polysilicon gate of the selection tube;
the storage tube is positioned at two sides of the selection tube, an ONO (oxide-nitride-oxide) dielectric layer of the storage tube is arranged on the silicon surface of the gate dielectric layer close to the selection tube and serves as a charge storage layer, and a polysilicon gate of the storage tube is arranged above the ONO layer;
the inner side of the polycrystalline silicon grid of the storage tube is a part of the selection tube, which extends upwards from the grid dielectric layer, and the outer side of the polycrystalline silicon grid of the storage tube is a side wall;
a source region or a drain region of the storage tube is arranged in the substrate below the outer side of the polysilicon gate of the storage tube, and metal silicide is arranged above the source region or the drain region of the storage tube;
the polysilicon gate electrodes of the two storage tubes are connected with the polysilicon gate electrodes of the selection tube, and the polysilicon gate electrodes of the two storage tubes are connected with the side walls of the two storage tubes.
The further improvement is that the selection tube and the storage tube are transistors with completely symmetrical structures, and the operating voltages of the two storage tubes can be interchanged.
In a further improvement, the storage tube is a SONOS storage tube.
The storage tube is manufactured by selecting a self-aligning side wall of the tube.
In a further improvement, the gate width of the storage tube is less than 50 nm.
In a further improvement, the polysilicon gates of the select transistors are respectively led out to serve as a first word line of the memory cell, the polysilicon gates of the left and right storage transistors are respectively led out to serve as a second word line and a third word line of the memory cell, and the unshared source regions or drain regions of the storage transistors are respectively led out to serve as a first bit line and a second bit line of the memory cell.
The invention relates to an operation method of a 2bit memory unit, wherein the memory unit comprises a selection tube and two storage tubes A and A, the storage tubes are SONOS tubes and are positioned at two sides of the selection tube, the selection tube and the storage tubes A and A at the two sides of the selection tube share a source drain region, the storage tubes are of a completely symmetrical structure, a first word line of the memory unit is led out from a grid electrode of the selection tube, a second word line and a third word line of the memory unit are respectively led out from the grid electrodes of the storage tubes at the two sides, and a first bit line and a second bit line of the memory unit are respectively led out from a non-shared source region or a non-shared drain region of the storage tubes at the two sides;
when the memory unit is programmed, a source end carrier injection mode is adopted;
when the memory cell reads data, the source end voltage of the storage tube, namely the voltage of the first bit line is used for shielding the influence of the state of the storage tube A on the storage tube A when the storage tube A is read; when reading data, the reading voltage of the selection tube is larger than the grid voltage of the storage tube, namely the first word line voltage is larger than the second voltage or the third voltage, so that the reading current is increased.
Aiming at the storage tubes manufactured by the side wall process, the 2-bit memory unit structure changes the mode that the grids of the 2 storage tubes are led out independently and the grids of the tubes are connected independently, and provides a new voltage operation mode, thereby providing larger reading current.
Drawings
Fig. 1 is a circuit schematic of a conventional memory cell structure.
Fig. 2 is a device cross-sectional schematic diagram of a conventional memory cell structure.
Fig. 3 is a layout structure of a conventional memory cell.
FIG. 4 is a circuit diagram of a memory cell of the present invention.
Fig. 5 is a device cross-sectional schematic diagram of one embodiment of a memory cell of the present invention.
Fig. 6 is a device cross-sectional schematic of another embodiment of a memory cell of the present invention.
Detailed Description
In the structure of the 2-bit memory unit disclosed by the invention, as shown in fig. 4, each unit of the circuit comprises 3 transistors, wherein each transistor comprises 2 storage tubes A and a selection tube, the memory unit can store 2-bit data, and each storage tube can store '0' or '1'.
The grid electrode of the selection tube is led out to form a first word line WL of the memory unit, the source electrode and the drain electrode of the selection tube are respectively connected with the source electrode or the drain electrode of the storage tube on two sides of the selection tube, and the other rest drain electrode or the source electrode of the storage tube respectively form a first bit line BL and a second bit line BL of the memory unit.
The gate leads of 2 memory cells in the memory cell form a second word line wls and a third word line wls, which are also connected together.
The two storage tubes are devices with completely symmetrical structures, namely, the two storage tubes can be respectively stored and read by interchanging operation voltages.
The above is a schematic diagram of a circuit structure of a memory cell provided by the present invention, and based on the circuit structure, the present invention provides the following two embodiments on a specific device structure:
example one
The invention provides a 2bit memory unit structure, as shown in figure 5, three MOS tubes are arranged on a semiconductor substrate, including a selection tube positioned in the middle and storage tubes A and A positioned at two sides of the selection tube, the selection tube and the storage tubes at two sides of the selection tube share a source drain region, because the tubes are completely symmetrical, the source drain can be exchanged at will, and the operation voltage can be exchanged.
The silicon surface of the selection tube positioned in the middle of the surface of the semiconductor substrate is provided with a gate dielectric layer, a polysilicon gate of the selection tube is arranged above the gate dielectric layer, and two ends of the gate dielectric layer extend upwards to wrap the side surface of the polysilicon gate of the selection tube.
The storage tube is an SONOS storage tube and is positioned at two sides of the selection tube, the ONO medium layer of the storage tube is positioned on the silicon surface of the grid medium layer close to the selection tube and serves as a charge storage layer, and the polysilicon grid of the storage tube is arranged above the ONO layer;
the inner side of the polycrystalline silicon grid of the storage tube is a part of the selection tube, which extends upwards from the grid dielectric layer, and the outer side of the polycrystalline silicon grid of the storage tube is a side wall;
a source region or a drain region of the storage tube is arranged in the substrate below the outer side of the polysilicon gate of the storage tube, and metal silicide is arranged above the source region or the drain region of the storage tube;
a dielectric layer is also arranged above the polysilicon grid of the selection tube, and the dielectric layer is usually an oxide film layer. The polysilicon gates of the storage tubes at two sides extend upwards, and the height of the polysilicon gates of the storage tubes exceeds that of the polysilicon gates of the selection tubes and extends to be close to the surface of the dielectric layer above the polysilicon gates of the selection tubes.
The storage tube is manufactured in a mode of selecting the self-aligning side wall of the tube.
The gate width of the storage tube is less than 50 nm.
The polysilicon grid of the selection tube is led out to be used as a first word line of the memory unit, the polysilicon grids of the left and right storage tubes are respectively led out to be used as a second word line and a third word line of the memory unit, and the unshared source region or drain region of the storage tubes is respectively led out to be used as a first bit line and a second bit line of the memory unit.
The memory unit adopts a source end carrier injection mode during programming.
Example two
Based on a circuit principle diagram 4, the invention further provides a 2-bit memory cell structure, and compared with the first embodiment, the embodiment has the same general structure, and the difference is that the top of the polysilicon gate of the storage tube and the top of the polysilicon gate of the selection tube, and the top of the polysilicon gate of the storage tube of the embodiment is lower than the top of the polysilicon gate of the selection tube, that is, the three polysilicon gates of the embodiment have the morphology which is just opposite to that of the first embodiment, and have the morphology which is high in the middle and low in two sides, and the tops of the polysilicon gates of the left storage tube a and the right storage tube a and the top of the polysilicon gate of the selection tube in the middle are both provided with dielectric layers which are usually oxide film layers and are connected with two side walls at the outermost side to form a whole, and 3 polysilicon gates are wrapped in the dielectric layers.
Similarly, the selection tube and the storage tube are transistors with completely symmetrical structures, and the operating voltages of the two storage tubes can be interchanged. The storage tube is an SONOS storage tube and is manufactured in a mode of selecting a self-aligned side wall of the tube.
The grid width of the storage tube is less than 50 nm.
The polysilicon grid of the selection tube is led out to be used as a first word line WL of a memory unit, the polysilicon grids of the left and right storage tubes are respectively led out to be used as a second word line WLS and a third word line WLS of the memory unit, and the unshared source region or drain region of the storage tubes is respectively led out to be used as a first bit line BL and a second bit line BL of the memory unit.
In the 2bit memory unit with the two structures, the polysilicon gates of the storage tubes on the two sides can be connected together through the self-aligned gate top metal silicide, and in the layout shown in fig. 3, it can be seen that the storage tubes are formed in a self-aligned side wall mode, and the storage tubes a and a surround the selection tube for one circle and then are connected together.
Aiming at the two 2-bit memory units, the operation method of the 2-bit memory unit is characterized in that a source end carrier injection mode is adopted when the memory unit is programmed.
The parameters involved are seen in table three below:
watch III
VPP represents the voltage of a storage tube grid in programming, Vgp represents the voltage of a selection tube grid in programming, the programming adopts Source-end carrier Injection (SSI), and the thickness of ONO electronic film is larger than that of ONO electronic film
In general, VPP is greater than 7V, the specific voltage increases with increasing film thickness, and Vgp is generally less than 2V (slightly greater)And selecting the starting voltage of the transistor), and Vd is the drain terminal voltage corresponding to the storage transistor when the Program is used, and is generally 1.5-5V.
VNH represents the negative voltage of the grid electrode during Erase, VPE represents the positive high voltage of the drain end of the storage tube, and when the thickness of the ONO electronic film is larger than that of the ONO electronic film
The difference between VPE and VNH is typically greater than 10V.
Vgs is the gate voltage of the storage tube at the time of Read, and Vs represents the source terminal voltage of the storage tube at the time of Read. The voltage of Vgs is related to the "0" and "1" discrimination of the storage tube, Vgs must be in the middle of the "0" and "1" threshold voltage discrimination of the storage tube. The Vs voltage is used to mask the effect of the storage tube a on the state of a when the storage tube a is read. Vgr is the read voltage of the select tube, and the new operation mode can make Vgr larger than Vgs to increase the whole read current.
The operating voltage for a particular memory cell can be referenced as follows:
watch four
When the memory cell provided by the invention reads data, the source end voltage of the storage tube, namely the voltage of the first bit line is used for shielding the influence of the state of the storage tube A on the storage tube A when the storage tube A is read; when reading data, the reading voltage of the selection tube is larger than the grid voltage of the storage tube, namely the first word line voltage is larger than the second voltage or the third voltage, so that the reading current is increased.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. The utility model provides a 2bit memory cell structure, every unit contains 3 transistors, wherein contains 2 storage tubes and a selection pipe, the memory cell can save 2bit data, and every storage tube can save "0" or "1", its characterized in that: a first word line of the memory unit is led out from the grid electrode of the selection tube, a source electrode and a drain electrode of the selection tube are respectively connected with source electrodes or drain electrodes of storage tubes at two sides of the selection tube, and the other rest drain electrodes or source electrodes of the storage tubes respectively form a first bit line and a second bit line of the memory unit;
and the grid electrodes of the 2 storage tubes in the memory unit are led out to form a second word line and a third word line, and the second word line and the third word line are also connected together.
2. The 2-bit memory cell structure of claim 1, wherein: the selection tube and the two storage tubes are all devices with completely symmetrical structures.
3. The 2-bit memory cell structure of claim 2, wherein: the 2 storage tubes can realize the respective storage and reading of the two storage tubes by interchanging the operating voltages.
4. The 2-bit memory cell structure of claim 1, wherein: when the memory unit is programmed, the grid voltage of the selection tube is smaller than that of the storage tube; when reading data, the grid voltage of the selection tube is larger than that of the storage tube so as to increase the reading current.
5. The 2-bit memory cell structure of claim 4, wherein: and during programming, a source end carrier injection mode is adopted.
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| FR2630850B1 (en) * | 1988-04-27 | 1993-10-15 | Thomson Csf | ELECTRONIC TUBE FOR THE DETECTION, STORAGE, AND SELECTION OF LIGHT IMAGES |
| US6485991B1 (en) * | 2001-05-24 | 2002-11-26 | Advanced Micro Devices, Inc. | System and method for output track unit detection and safe storage tube removal |
| JP5001578B2 (en) * | 2005-06-30 | 2012-08-15 | ラピスセミコンダクタ株式会社 | Semiconductor memory device and manufacturing method of semiconductor memory device |
| CN101442076A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Device structure of SONOS memory tube and method for producing the same |
| CN102931196B (en) * | 2011-08-08 | 2015-04-08 | 上海华虹宏力半导体制造有限公司 | SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) device |
| CN103855163B (en) * | 2012-12-05 | 2016-12-21 | 上海华虹宏力半导体制造有限公司 | Two bit SONOS flash memories and manufacture methods thereof |
| CN104700893B (en) * | 2013-12-10 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | NOR-type memory circuitry and operating method |
| KR20150093019A (en) * | 2014-02-06 | 2015-08-17 | 에스케이하이닉스 주식회사 | Semiconductor memory device and operating method thereof |
| CN204045210U (en) * | 2014-09-04 | 2014-12-24 | 上海梅轩实业有限公司 | A kind of eeprom array |
| CN105118833B (en) * | 2015-07-30 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | The structure and manufacture method of 3D tunneling floating-gate memories |
| CN109166855B (en) * | 2018-08-28 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | Manufacturing process method of two-bit split-gate SONOS device |
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