CN111175594A - Method for monitoring residual life of direct current double-support capacitor of fully-controlled alternating current-direct current-alternating current system - Google Patents

Method for monitoring residual life of direct current double-support capacitor of fully-controlled alternating current-direct current-alternating current system Download PDF

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CN111175594A
CN111175594A CN201911050955.7A CN201911050955A CN111175594A CN 111175594 A CN111175594 A CN 111175594A CN 201911050955 A CN201911050955 A CN 201911050955A CN 111175594 A CN111175594 A CN 111175594A
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CN111175594B (en
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温建民
王开康
叶飞
何斌
陈杰
李庭
刘志刚
张钢
邱瑞昌
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Beijing Jiaotong University
China Railway Siyuan Survey and Design Group Co Ltd
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China Railway Siyuan Survey and Design Group Co Ltd
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    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/08—Measuring resistance by measuring both voltage and current
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
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Abstract

The invention provides a method for monitoring the residual life of a direct current double-support capacitor of a fully-controlled alternating current-direct current alternating current system, which is suitable for a direct current side double-support capacitor alternating current-direct current alternating current system, is convenient to realize on line, does not need to increase extra hardware equipment, does not need to change the state of the system, and monitors the residual life of the capacitor at any time in real time. The method can monitor the residual life of the two support capacitors on the direct current side at the same time, has strong anti-interference capability, and can realize the residual life prediction capability with enough precision.

Description

Method for monitoring residual life of direct current double-support capacitor of fully-controlled alternating current-direct current-alternating current system
Technical Field
The invention relates to a method for monitoring the residual life of a direct current double-support capacitor, in particular to a method for monitoring the residual life of a direct current double-support capacitor of a fully-controlled alternating current-direct current-alternating current system.
Background
The full-control rectification AC-DC-AC converter system has high efficiency and high reliability, and provides three-phase or single-phase AC power output with fully controllable amplitude and frequency, so that the full-control rectification AC-DC-AC converter system is widely applied to various occasions. With the development of power reliability, there are various schemes for online monitoring of the remaining life of the dc-side support capacitor. Due to the current modular design concept, existing ac-dc-ac converters are usually constructed with two sets of modules. Each set of modules comprises 6 IGBTs (Insulated gate bipolar Transistor) and 1 dc-side support capacitor. This makes two capacitors exist on the dc side of the ac-dc-ac converter topology, which makes it more difficult to implement the existing online capacitance remaining life monitoring scheme, which is not perfect. In addition, the conventional online support capacitor monitoring scheme usually requires an additional control strategy to make the system out of a normal working state or requires additional hardware equipment to increase the system cost.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a scheme for monitoring the residual life of a capacitor, which is suitable for a direct-current side double-support capacitor alternating-current-direct-current alternating-current system, is convenient to realize on line, does not need to add extra hardware equipment, does not need to change the state of the system and is carried out at any time in real time. The scheme can monitor the residual life of two supporting capacitors at the direct current side at the same time, has stronger anti-interference capability and can realize the residual life prediction capability with enough precision.
In order to achieve the above purposes, the technical scheme adopted by the invention is as follows:
the utility model provides a PWM converter direct current supports electric capacity remaining life on-line monitoring system, adopts DSP + FPGA framework, includes: the system comprises a core board, a bottom board, an AD7656 sampling module, a W5300 communication module and an upper computer; the core board comprises a DSP system and an FPGA minimum system; the DSP system comprises: a DSP minimum system and a plug-in storage unit; the plug-in storage unit includes: the device comprises a FLASH chip and a RAM chip, the AD7656 sampling module comprises 3 AD7656 chips and a low-pass filter, the W5300 communication module comprises a WIZnet W5300 chip and an Ethernet transformer,
a data address bus, a PWM output signal line, a BOOT guide signal line and a general input/output signal line of the DSP chip are all connected with the FPGA chip; the EM1CS2 pin of the DSP chip is connected with the FLASH chip and is used for selecting the FLASH chip; the EM1CS3 pin of the DSP chip is connected with the RAM chip and is used for chip selection of the RAM chip; the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the FLASH chip; the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the RAM chip; a 19-bit address bus and a 16-bit data bus of the DSP chip are respectively connected with an address pin and a data pin of the FLASH chip; a 19-bit address bus and a 16-bit data bus of the DSP chip are respectively connected with an address pin and a data pin of the RAM chip;
the EM1CS4 pin of the DSP chip is connected with the pin CS of the WIZnet W5300 chip, the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the WIZnet W5300 chip, the 8-bit address bus of the DSP chip is connected with the address line input pin of the WIZnet W5300 chip, and the 16-bit data bus of the DSP chip is connected with the data input pin of the WIZnet W5300 chip;
12 GPIO pins of the FPGA chip are respectively connected with a chip selection pin CS, a RESET signal pin RESET, a feedback signal pin BUSY and a start conversion signal pin CONVST of the 3 AD7656 chips, and data pins of the 3 AD7656 chips are all connected with a 16 data bus of the DSP chip; the 6-path sampling input pins of the AD7656 chip are connected with the output end of a low-pass filter, the input end of one low-pass filter is connected with a voltage sensor, and the input end of the other low-pass filter is connected with a current sensor;
the bottom plate is connected with the core board and provides a power supply for the control chip of the core board; the expansion interface of the core board comprises: the device comprises a multi-protocol serial communication interface, an ADC sampling input interface, a data address bus interface, a PWM output interface and a plurality of digital input and output interfaces.
On the basis of the scheme, the online monitoring system adopts an expandable connector design, and the expandable connector design allows a user to freely design the base plate aiming at the functions and the target functions of the core plate.
On the basis of the scheme, the DSP system adopts a window voltage detection chip to design an over-voltage and under-voltage protection circuit, and performs protection and reset operations on the DSP system; the DSP minimum system unit comprises a crystal oscillator circuit, a reset circuit, a power supply circuit, a boot mode setting circuit and a JTAG interface circuit; the model of the DSP chip is TMS320F28377 d; the DSP system also includes a plurality of data communication protocols including I2C, SCI, SPI, CAN, USB; the DSP system is provided with an ADC sampling module and is used for realizing 16-bit-precision differential input signal sampling and 12-bit-precision single-ended input signal sampling.
On the basis of the scheme, the FLASH chip adopts an SST39VF822 chip, and the RAM chip adopts an IS61LV25616AL-10TLI chip; the W5300 communication module is connected and communicated with an upper computer through an Ethernet transformer HR 911103A.
On the basis of the scheme, the communication interface of the upper computer comprises an oscilloscope part, a capacitor equivalent circuit, a capacitor service life and a capacitor state; the oscilloscope part comprises an oscilloscope control box, a waveform display frame and an oscilloscope setting part and is used for observing the waveform of the capacitor voltage and the capacitor current obtained by sampling; the capacitance equivalent circuit adopts a first-order series resistance-capacitance equivalent circuit, and different algorithms are selected to calculate the actual capacitance value.
On the basis of the scheme, the FPGA minimum system comprises a power supply circuit, a clock circuit, a JTAG circuit, a programming configuration circuit and an input/output circuit, wherein the power supply circuit is used for supplying power to an FPGA chip and an inner core and providing a reference level for the FPGA inner core; the clock circuit comprises a 50MHz clock signal input provided by an external active crystal oscillator circuit and a synchronous clock signal input output by the DSP chip; the JTAG circuit is used for burning programs and debugging chips on line; the programming configuration circuit adopts a four-way serial configuration chip EPCQ64, and the programming mode is selected to be an active serial mode and is used for solidifying a program circuit when the FPGA chip is electrified and started; the input-output circuit comprises digital input and output, and can be freely designed.
A full-control AC-DC-AC converter system DC double-support capacitor remaining life monitoring method is applied to the online monitoring system and comprises the following steps:
s1, initializing a DSP chip and an FPGA chip;
s2, initializing an AD7656 chip and a W5300 chip;
s3, setting the interrupt frequency of the DSP system to be 10kHz, triggering sampling once when the DSP system is interrupted, and setting the sampling frequency to be 10 kHz;
s4, starting the converter system after initialization: executing a three-phase current transformation program, outputting stable direct current voltage at a direct current side, and waiting for the voltage at the direct current side to be stable;
s5, executing a current injection program: increasing direct current bias in a current feedback loop at a rectification input side to enable voltage at the direct current side to generate 50Hz fluctuation with small amplitude;
s6, voltage sensors VT1, VT2 and VT acquire voltage analog signals, current sensors CT1, CT2 and CT acquire current analog signals, the acquired voltage and current analog signals are processed by a low-pass filter and then transmitted to an AD7656 chip, and the AD7656 chip converts the voltage and current analog signals into 16-bit-precision voltage and current digital signals;
s7, sampling: the DSP chip sends a sampling instruction to the FPGA chip, the FPGA chip controls the AD7656 chip to sample, the AD7656 chip transmits voltage and current digital signals to the FPGA chip, and the FPGA chip transmits the voltage and current digital signals to the DSP chip through a bus;
s8, after the DSP chip receives the voltage and current digital signals:
support capacitance C for inversion side2The algorithm is as follows:
selecting a fundamental wave frequency as 50Hz by adopting a discrete Fourier algorithm, solving the amplitude and the phase angle of a fundamental wave component in direct current voltage and direct current, solving an equivalent modulus value and an equivalent phase angle of a first-order equivalent resistance-capacitance circuit according to a formula (1), solving an equivalent capacitance value C and an equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit according to a formula (2), and transmitting the solved equivalent capacitance value and equivalent resistance value to an upper computer through a WIZnet W5300 chip and an Ethernet transformer;
or the direct current voltage and direct current digital signals are transmitted to an upper computer through a WIZnet W5300 chip and an Ethernet transformer, MATLAB software in the upper computer respectively carries out band-pass filtering on the voltage and current digital signals by adopting an equal ripple FIR band-pass filter, the band-pass frequency is set to be 50Hz, the band-pass width is 2Hz, the order is 395, and the filtering is carried out to obtain 50Hz capacitance voltage and current waveforms; calculating an equivalent modulus value and an equivalent phase angle of the first-order equivalent resistance-capacitance circuit according to the obtained 50Hz capacitor voltage and current waveforms, and then calculating an equivalent capacitance value C and an equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit according to a formula (2);
or the direct current voltage digital signals and the direct current digital signals are transmitted to an upper computer through a WIZnet W5300 chip and an Ethernet transformer, MATLAB software in the upper computer respectively carries out band-pass filtering on the voltage digital signals and the current digital signals by adopting a Butterworth IIR band-pass filter, the band-pass frequency is 49 Hz-51 Hz, the order is 4, and the filtering is carried out to obtain 50Hz capacitance voltage waveforms and current waveforms; calculating an equivalent modulus value and an equivalent phase angle of the first-order equivalent resistance-capacitance circuit according to the obtained 50Hz capacitor voltage and current waveforms, and then calculating an equivalent capacitance value C and an equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit according to a formula (2);
Figure BDA0002255318770000051
Figure BDA0002255318770000052
in the formula (1, | U50|、∠U50Respectively representing the amplitude and phase angle, | I, of the harmonic component of the 50Hz voltage50|、∠I50respectively representing the amplitude and phase angle of 50Hz current harmonic component, | Z | representing the equivalent module value of the first-order equivalent RC circuit, ∠ Z representing the equivalent phase angle of the first-order equivalent RC circuit, and for the support capacitor C on the rectification side1The algorithm is as follows:
according to the formula (3), reconstructing a 50Hz alternating current component on the output direct current side of the rectification side by using the collected current on the rectification side, the voltage on the rectification side and the voltage on the direct current side, wherein the 50Hz alternating current component on the output direct current side of the rectification side and the alternating current component flowing through the support capacitor C on the inversion side2Subtracting the 50Hz current component to calculate the current flowing through the supporting capacitor C of the rectifying side150Hz DC side voltage and the voltage flowing through the rectifying side support capacitor C1The 50Hz alternating current component is substituted into the formulas (1) and (2), and the supporting capacitor C at the rectifying side is calculated1The equivalent capacitance value C and the equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit;
Figure BDA0002255318770000061
in the formula (3)
Figure BDA0002255318770000062
50Hz voltage components of the A B C three-phase voltage respectively,
Figure BDA0002255318770000063
respectively are the direct current components of the AB C three-phase current,
Figure BDA0002255318770000064
and
Figure BDA0002255318770000065
respectively the 50Hz voltage and current components of the rectifying side output DC side,
Figure BDA0002255318770000066
and
Figure BDA0002255318770000067
voltage and current direct current components on the direct current side respectively;
and S9, judging the current capacitance state and the residual life according to the equivalent capacitance value and the equivalent resistance value of the first-order equivalent resistance-capacitance circuit and the initial capacitance value and the initial resistance value input by the user.
Drawings
The invention has the following drawings:
fig. 1 is a circuit topology diagram of an ac-dc-ac converter system.
FIG. 2 is a block diagram of an online monitoring system for the residual life of a DC support capacitor of a PWM converter.
Fig. 3 is a schematic diagram of a current injection method.
FIG. 4 is a software schematic diagram of the capacitor remaining life online monitoring system.
Detailed Description
The invention is described in further detail below with reference to figures 1-4.
The scheme for calculating the residual life of the capacitor on line is suitable for a circuit topology shown in figure 1:
the circuit topology has the following characteristics:
1. the input side is three-phase alternating current input;
2. the rectifying side is a three-phase half-bridge full-control rectifying topology;
3. the direct current side is provided with two supporting capacitors which are shown in the form of a first-order resistance-capacitance equivalent circuit, and the capacitors are the monitoring objects of the monitoring system;
4. the inverter side forms a three-phase alternating current system by six IGBTs of a three-bridge arm or forms a single-phase alternating current system by four IGBTs of a double-bridge arm;
5. the load is a three-phase symmetrical load or a single-phase load;
6. CT and VT are a direct current side current sensor and a voltage sensor, respectively, CT1 and CT2 are an alternating current side current sensor, respectively, and VT1 and VT2 are alternating current side current sensors, respectively. The solid line frame sensor is used for the monitoring system, and the dotted line frame sensor is not used for the monitoring system.
Based on the above circuit topology, there are the following theoretical facts:
(1) for a three-phase fully-controlled rectifying circuit, voltage pulsation with specified frequency can be generated on a direct-current side by a current injection method, so that current components with the same frequency exist in a capacitor on the direct-current side, and 50Hz current fluctuation is injected into the direct-current side;
(2) for a three-phase inverter circuit with six three-phase three-bridge-arm IGBTs, under the condition that three-phase loads are symmetrical and no input source exists, 50Hz alternating current components hardly exist in direct current side currents of an inverter; similarly, for a single-phase inverter circuit with single-phase double-bridge-arm four IGBTs, under the condition that a load is linear and passive, an alternating current component of 50Hz does not exist in direct-current side current;
(3) according to the two theoretical foundations, 50Hz alternating current components measured by the direct current side current sensor CT almost completely flow through the inverter side capacitor;
(4) therefore, the 50Hz AC voltage and current components measured by the voltage sensor and the current sensor installed on the DC side of the circuit can be approximated to the 50Hz voltage component across the capacitor and the 50Hz current component flowing through the capacitor.
Compared with the traditional current injection method, the current injection method is different from the traditional current injection method, the 50Hz voltage current fluctuation generated by the traditional current injection method on the DC side can cause DC bias and 100Hz harmonic component in the 50Hz AC side current, and the 100Hz harmonic component can distort the AC side current waveform, so that the current THD (total harmonic distortion) is increased, and the system stability is influenced. The current injection method provided by the invention can avoid the situation that the current THD is increased.
The current injection method of the present invention is shown in fig. 3, and the basic principle is as follows:
(1) the current injection method is based on the traditional voltage and current double closed-loop rectification control;
(2) the current injection method only needs to inject direct current bias into a current sampling signal of one phase of three phases;
(3) the current injection method will generate 50Hz voltage fluctuation on the DC side;
(4) the current injection method does not couple out 100Hz harmonic components on the alternating current side;
the scheme for online calculating the residual life of the capacitor provided by the invention adopts an online monitoring hardware system shown in FIG. 2. The hardware system consists of a DSP + FPGA double-digital processing chip, an Ethernet template based on a WIZnet W5300 chip and a sampling module based on an AD7656 chip are configured, and other expansion functions such as serial passing of the DSP chip are reserved. The hardware system takes a DSP chip as a main control chip, realizes parallel communication of data among different chips through the EMIF function of the DSP, and has the functions of high-precision sampling and high-speed communication.
Based on the hardware system, the method comprises the following operation steps:
1. installing a sensor at a designated position of the system; generally, in an ac-dc-ac converter system, a voltage sensor is installed on a dc side to detect voltage fluctuation on the dc side, and a current sensor is installed to calculate output power of an inverter system. Therefore, the voltage and current sensors required by an online monitoring system are usually included in the converter system, and step 1 can be omitted.
2. Configuring a DSP + FPGA hardware system: (1) initializing a DSP chip and an FPGA chip; (2) initializing AD7656 and W5300 chips; (3) the DSP system interrupt frequency is set to 10kHz and one sample is triggered in each interrupt routine so that the sample rate is also 10 kHz. In the sampling process, a DSP chip sends a sampling instruction to the FPGA, the FPGA controls the AD7656 to finish signal sampling once, and data are returned to the DSP system.
3. Based on the DSP + FPGA hardware system which is configured, the DSP is used as a main control chip, voltage and current analog signals are collected through a sensor, the voltage and current analog signals are converted into digital quantity in an AD7656 chip after passing through a low-pass filter and then are transmitted to an FPGA (field programmable gate array) chip, the FPGA transmits the data to a DSP (digital signal processing) chip through a bus, and the DSP obtains a voltage and current digital quantity signal with 16-bit precision;
4. after the DSP chip collects the voltage and current digital signals,
support capacitance C for inversion side2The algorithm is as follows:
selecting a fundamental wave frequency as 50Hz by adopting a discrete Fourier algorithm, solving the amplitude and the phase angle of a fundamental wave component in direct current voltage and direct current, solving an equivalent modulus value and an equivalent phase angle of a first-order equivalent resistance-capacitance circuit according to a formula (1), solving an equivalent capacitance value C and an equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit according to a formula (2), and transmitting the solved equivalent capacitance value and equivalent resistance value to an upper computer through a WIZnet W5300 chip and an Ethernet transformer;
or the direct current voltage and direct current digital signals are transmitted to an upper computer through a WIZnet W5300 chip and an Ethernet transformer, MATLAB software in the upper computer respectively carries out band-pass filtering on the voltage and current digital signals by adopting an equal ripple FIR band-pass filter, the band-pass frequency is set to be 50Hz, the band-pass width is 2Hz, the order is 395, and the filtering is carried out to obtain 50Hz capacitance voltage and current waveforms; calculating an equivalent modulus value and an equivalent phase angle of the first-order equivalent resistance-capacitance circuit according to the obtained 50Hz capacitor voltage and current waveforms, and then calculating an equivalent capacitance value C and an equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit according to a formula (2);
or the direct current voltage digital signals and the direct current digital signals are transmitted to an upper computer through a WIZnet W5300 chip and an Ethernet transformer, MATLAB software in the upper computer respectively carries out band-pass filtering on the voltage digital signals and the current digital signals by adopting a Butterworth IIR band-pass filter, the band-pass frequency is 49 Hz-51 Hz, the order is 4, and the filtering is carried out to obtain 50Hz capacitance voltage waveforms and current waveforms; calculating an equivalent modulus value and an equivalent phase angle of the first-order equivalent resistance-capacitance circuit according to the obtained 50Hz capacitor voltage and current waveforms, and then calculating an equivalent capacitance value C and an equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit according to a formula (2);
Figure BDA0002255318770000091
Figure BDA0002255318770000092
in the formula (1, | U50|、∠U50Respectively representing the amplitude and phase angle, | I, of the harmonic component of the 50Hz voltage50|、∠I50respectively representing the amplitude and phase angle of 50Hz current harmonic component, | Z | representing the equivalent module value of the first-order equivalent RC circuit, ∠ Z representing the equivalent phase angle of the first-order equivalent RC circuit, and for the support capacitor C on the rectification side1The algorithm is as follows:
according to the formula (3), reconstructing a 50Hz alternating current component on the output direct current side of the rectification side by using the collected current on the rectification side, the voltage on the rectification side and the voltage on the direct current side, wherein the 50Hz alternating current component on the output direct current side of the rectification side and the alternating current component flowing through the support capacitor C on the inversion side2Subtracting the 50Hz current component to calculate the current flowing through the supporting capacitor C of the rectifying side1Of the alternating current component of 50 Hz. The voltage at the DC side of 50Hz flows through the support capacitor C at the rectification side1The 50Hz AC current component is substituted into the formulas (1) and (2), and the supporting capacitor C at the rectifying side can be calculated1The equivalent capacitance value C and the equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit;
Figure BDA0002255318770000101
in the formula (3)
Figure BDA0002255318770000102
50Hz voltage components of the A B C three-phase voltage respectively,
Figure BDA0002255318770000103
respectively are the direct current components of the AB C three-phase current,
Figure BDA0002255318770000104
and
Figure BDA0002255318770000105
respectively as the output DC side of the rectification sideThe voltage, current components of 50Hz of the voltage,
Figure BDA0002255318770000106
and
Figure BDA0002255318770000107
the voltage and current dc components on the dc side are provided.
5. And judging the current capacitance state and the residual life according to the equivalent capacitance value and the equivalent resistance value of the first-order equivalent resistance-capacitance circuit and the initial capacitance value and the initial resistance value input by a user.
Those not described in detail in this specification are within the skill of the art.

Claims (7)

1. The utility model provides a PWM converter direct current supports electric capacity remaining life on-line monitoring system which characterized in that adopts DSP + FPGA framework, includes: the system comprises a core board, a bottom board, an AD7656 sampling module, a W5300 communication module and an upper computer; the core board comprises a DSP system and an FPGA minimum system; the DSP system comprises: a DSP minimum system and a plug-in storage unit; the plug-in storage unit includes: the device comprises a FLASH chip and a RAM chip, the AD7656 sampling module comprises 3 AD7656 chips and a low-pass filter, the W5300 communication module comprises a WIZnet W5300 chip and an Ethernet transformer,
a data address bus, a PWM output signal line, a BOOT guide signal line and a general input/output signal line of the DSP chip are all connected with the FPGA chip; the EM1CS2 pin of the DSP chip is connected with the FLASH chip and is used for selecting the FLASH chip; the EM1CS3 pin of the DSP chip is connected with the RAM chip and is used for chip selection of the RAM chip; the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the FLASH chip; the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the RAM chip; a 19-bit address bus and a 16-bit data bus of the DSP chip are respectively connected with an address pin and a data pin of the FLASH chip; a 19-bit address bus and a 16-bit data bus of the DSP chip are respectively connected with an address pin and a data pin of the RAM chip;
the EM1CS4 pin of the DSP chip is connected with the pin CS of the WIZnet W5300 chip, the EM1OE pin and the EM1WE pin of the DSP chip are respectively connected with the read pin and the write pin of the WIZnet W5300 chip, the 8-bit address bus of the DSP chip is connected with the address line input pin of the WIZnet W5300 chip, and the 16-bit data bus of the DSP chip is connected with the data input pin of the WIZnet W5300 chip;
12 GPIO pins of the FPGA chip are respectively connected with a chip selection pin CS, a RESET signal pin RESET, a feedback signal pin BUSY and a start conversion signal pin CONVST of the 3 AD7656 chips, and data pins of the 3 AD7656 chips are all connected with a 16 data bus of the DSP chip; the 6-path sampling input pins of the AD7656 chip are connected with the output end of a low-pass filter, the input end of one low-pass filter is connected with a voltage sensor, and the input end of the other low-pass filter is connected with a current sensor;
the bottom plate is connected with the core board and provides a power supply for the control chip of the core board; the expansion interface of the core board comprises: the device comprises a multi-protocol serial communication interface, an ADC sampling input interface, a data address bus interface, a PWM output interface and a plurality of digital input and output interfaces.
2. The PWM converter dc support capacitor remaining life on-line monitoring system according to claim 1, wherein said on-line monitoring system employs an expandable connector design that allows a user to freely design a backplane for core board functions and target functions.
3. The PWM converter direct current support capacitor residual life online monitoring system of claim 1, wherein the DSP system adopts a window voltage detection chip to perform over-voltage and under-voltage protection circuit design, and performs protection and reset operation on the DSP system; the DSP minimum system unit comprises a crystal oscillator circuit, a reset circuit, a power supply circuit, a boot mode setting circuit and a JTAG interface circuit; the model of the DSP chip is TMS320F28377 d; the DSP system also includes a plurality of data communication protocols including I2C, SCI, SPI, CAN, USB; the DSP system is provided with an ADC sampling module for realizing 16-bit precisionAnd 12-bit precision single-ended input signal sampling.
4. The PWM converter direct-current support capacitor residual life online monitoring system of claim 1, wherein the FLASH chip adopts SST39VF822 chip, and the RAM chip adopts IS61LV25616AL-10TLI chip; the W5300 communication module is connected and communicated with an upper computer through an Ethernet transformer HR 911103A.
5. The PWM converter direct current support capacitor residual life online monitoring system of claim 1, wherein the communication interface of the upper computer comprises an oscilloscope part, a capacitor equivalent circuit, a capacitor life and a capacitor state; the oscilloscope part comprises an oscilloscope control box, a waveform display frame and an oscilloscope setting part and is used for observing the waveform of the capacitor voltage and the capacitor current obtained by sampling; the capacitance equivalent circuit adopts a first-order series resistance-capacitance equivalent circuit, and different algorithms are selected to calculate the actual capacitance value.
6. The PWM converter direct current support capacitor residual life online monitoring system of claim 1, wherein the FPGA minimum system comprises a power supply circuit, a clock circuit, a JTAG circuit, a programming configuration circuit and an input-output circuit, wherein the power supply circuit is used for supplying power to an FPGA chip and a kernel and providing a reference level for the FPGA kernel; the clock circuit comprises a 50MHz clock signal input provided by an external active crystal oscillator circuit and a synchronous clock signal input output by the DSP chip; the JTAG circuit is used for burning programs and debugging chips on line; the programming configuration circuit adopts a four-way serial configuration chip EPCQ64, and the programming mode is selected to be an active serial mode and is used for solidifying a program circuit when the FPGA chip is electrified and started; the input/output circuit includes digital input and output, and can be freely designed.
7. A method for monitoring the residual life of a DC double-support capacitor of a fully-controlled AC-DC-AC converter system applies the PWM converter DC double-support capacitor on-line monitoring system of any one of the claims 1 to 6, which is characterized by comprising the following steps:
s1, initializing a DSP chip and an FPGA chip;
s2, initializing an AD7656 chip and a W5300 chip;
s3, setting the interrupt frequency of the DSP system to be 10kHz, triggering sampling once when the DSP system is interrupted, and setting the sampling frequency to be 10 kHz;
s4, starting the converter system after initialization: executing a three-phase current transformation program, outputting stable direct current voltage at a direct current side, and waiting for the voltage at the direct current side to be stable;
s5, executing a current injection program: increasing direct current bias in a current feedback loop at a rectification input side to enable voltage at the direct current side to generate 50Hz fluctuation with small amplitude;
s6, voltage sensors VT1, VT2 and VT acquire voltage analog signals, current sensors CT1, CT2 and CT acquire current analog signals, the acquired voltage and current analog signals are processed by a low-pass filter and then transmitted to an AD7656 chip, and the AD7656 chip converts the voltage and current analog signals into 16-bit-precision voltage and current digital signals;
s7, sampling: the DSP chip sends a sampling instruction to the FPGA chip, the FPGA chip controls the AD7656 chip to sample, the AD7656 chip transmits voltage and current digital signals to the FPGA chip, and the FPGA chip transmits the voltage and current digital signals to the DSP chip through a bus;
s8, after the DSP chip receives the voltage and current digital signals:
support capacitance C for inversion side2The algorithm is as follows:
selecting a fundamental wave frequency as 50Hz by adopting a discrete Fourier algorithm, solving the amplitude and the phase angle of a fundamental wave component in direct current voltage and direct current, solving an equivalent modulus value and an equivalent phase angle of a first-order equivalent resistance-capacitance circuit according to a formula (1), solving an equivalent capacitance value C and an equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit according to a formula (2), and transmitting the solved equivalent capacitance value and equivalent resistance value to an upper computer through a WIZnet W5300 chip and an Ethernet transformer;
or the direct current voltage and direct current digital signals are transmitted to an upper computer through a WIZnet W5300 chip and an Ethernet transformer, MATLAB software in the upper computer respectively carries out band-pass filtering on the voltage and current digital signals by adopting an equal ripple FIR band-pass filter, the band-pass frequency is set to be 50Hz, the band-pass width is 2Hz, the order is 395, and the filtering is carried out to obtain 50Hz capacitance voltage and current waveforms; calculating an equivalent modulus value and an equivalent phase angle of the first-order equivalent resistance-capacitance circuit according to the obtained 50Hz capacitor voltage and current waveforms, and then calculating an equivalent capacitance value C and an equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit according to a formula (2);
or the direct current voltage digital signals and the direct current digital signals are transmitted to an upper computer through a WIZnet W5300 chip and an Ethernet transformer, MATLAB software in the upper computer respectively carries out band-pass filtering on the voltage digital signals and the current digital signals by adopting a Butterworth IIR band-pass filter, the band-pass frequency is 49 Hz-51 Hz, the order is 4, and the filtering is carried out to obtain 50Hz capacitance voltage waveforms and current waveforms; calculating an equivalent modulus value and an equivalent phase angle of the first-order equivalent resistance-capacitance circuit according to the obtained 50Hz capacitor voltage and current waveforms, and then calculating an equivalent capacitance value C and an equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit according to a formula (2);
Figure FDA0002255318760000041
Figure FDA0002255318760000042
in the formula (1, | U50|、∠U50Respectively representing the amplitude and phase angle, | I, of the harmonic component of the 50Hz voltage50|、∠I50respectively representing the amplitude and phase angle of the harmonic component of the 50Hz current, ∠ Z ∠ representing the equivalent module value of the first-order equivalent RC circuit, ∠ Z representing the equivalent phase angle of the first-order equivalent RC circuit,
supporting the capacitor C for the rectification side1The algorithm is as follows:
reconstructing the output DC side of the rectifier side from the collected rectifier side current, rectifier side voltage and DC side voltage according to equation (3)A 50Hz AC current component, a 50Hz AC current component on the DC output side of the rectifier and a supporting capacitor C on the inverter side2Subtracting the 50Hz current component to calculate the current flowing through the supporting capacitor C of the rectifying side150Hz DC side voltage and the voltage flowing through the rectifying side support capacitor C1The 50Hz alternating current component is substituted into the formulas (1) and (2), and the supporting capacitor C at the rectifying side is calculated1The equivalent capacitance value C and the equivalent resistance value ESR of the first-order equivalent resistance-capacitance circuit;
Figure FDA0002255318760000051
in the formula (3)
Figure FDA0002255318760000052
50Hz voltage components of the A B C three-phase voltage respectively,
Figure FDA0002255318760000053
are respectively the direct current components of the phase current of the A, B and C phases,
Figure FDA0002255318760000054
and
Figure FDA0002255318760000055
respectively the 50Hz voltage and current components of the rectifying side output DC side,
Figure FDA0002255318760000056
and
Figure FDA0002255318760000057
voltage and current direct current components on the direct current side respectively;
and S9, judging the current capacitance state and the residual life according to the equivalent capacitance value and the equivalent resistance value of the first-order equivalent resistance-capacitance circuit and the initial capacitance value and the initial resistance value input by the user.
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