CN111149232A

CN111149232A - Manufacture of carbon nanotube thin film transistor substrate and display integration thereof

Info

Publication number: CN111149232A
Application number: CN201780092111.1A
Authority: CN
Inventors: 李华平
Original assignee: ATOM NANOELECTRONICS Inc
Current assignee: ATOM NANOELECTRONICS Inc
Priority date: 2017-05-08
Filing date: 2017-05-08
Publication date: 2020-05-12
Also published as: KR102366816B1; KR20200024771A; WO2018208284A1; KR102511414B1; KR20220025950A

Abstract

Methods for producing single-walled carbon nanotubes (SWCNTs) and integrating them into existing TFT backplane fabrication lines are provided. Compared to LTPS and oxide TFT backplanes, SWCNT TFT backplanes exhibit equivalent or better quality factors such as high field emission mobility, low temperature fabrication, good stability, uniformity, scalability, flexibility, transparency, mechanical deformability, low voltage and power consumption, flexibility, and low cost. Also provided are methods and processes for integrating SWCNTs into existing TFT backplane fabrication lines, without additional capital requirements to begin preliminary testing and high volume manufacturing.

Description

Manufacture of carbon nanotube thin film transistor substrate and display integration thereof

Technical Field

Methods for fabricating and integrating carbon nanotube thin film transistor backplanes into a display.

Background

Flat Panel Displays (FPDs) have infiltrated consumer electronics products with integrated display functionality. In existing FPDs, Thin Film Transistor (TFT) -Liquid Crystal Displays (LCDs) occupy the current display market, with a market share of 97.5% in 2013, although there are some limitations in color, contrast, and response time. Recently, display capital expenditure has been rapidly shifted from TFT-LCD to AMOLED, not only because of the excellent display quality of AMOLED in terms of color, contrast and response time, but also the cost advantage of large AMOLED of 8 generations or larger fabrication over TFT-LCD. To be able to fabricate AMOLEDs larger than Gen 8 size, there are several technical challenges here, including limitations in conventional active matrix Thin Film Transistor (TFT) backplanes. (see, e.g., G.Gu and S.R.Forrest, IEEE Journal of selected toptics in Quantum Electronics, vol.4, pp.83-99,1998, the disclosures of which are incorporated herein by reference.)

Current active matrix TFT backplanes for driving AM-LCD pixels are typically constructed with low mobility (-1 cm)²V^-1s^-1) And amorphous silicon (a-Si) having poor stability, and thus is not suitable for the AMOLED pixel. (see, m.j.powell, ieee transactions on Electron Devices, vol.36, pp.2753-2763,1989, the disclosure of which is incorporated herein by reference.) due to these drawbacks, current AMOELD displays are driven by low temperature poly-Si (poly-Si) TFTs, which suffer from high manufacturing costs and time, as well as device size, orientation, and non-uniformity limitations, all of which present a serious challenge to increase display size and product yield. (see, e.g., C. -P.Chang and Y. -C.S.Wu, IEEE electron devices, vol.30, pp.130-132,2009; Y. -J.park, M. -H.Jung, S. -H.park and O.Kim, Japanese journal of Applied Physics, vol.49, pp.03CD01, 2010; and P. -S.Lin and T. -S.Li, IEEEelectron device drivers, vol.15, pp.138-139,1994, the disclosures of each of which are incorporated herein by reference.)

Although Low Temperature Polysilicon (LTPS) backplanes have been in mass production until 5.5 generations, LTPS fabrication techniques including Excimer Laser Annealing (ELA) and Advanced Solid Phase Crystallization (ASPC) have created substantial obstacles to scale-up for >8 generations. For example, both ELA and ASPC fabs have very slow overall average cycle times, more than twice the typical 60 seconds for a-Si. This doubles the capital cost of the a-Si array process. In addition, scaling up of ELA can lead to non-uniformity and array failure. The high temperatures of the ASPC process (about 600 ℃) require expensive glass to avoid glass warpage and shrinkage. (B.Young, Information Display, vol.10, pp.24,2010, the disclosure of which is incorporated herein by reference.) the higher processing temperatures and more complex photomasks required to manufacture LTPS increase capital expenditure and the difficulty of achieving high yields. This makes the 5"LTPSTFT-LCD (1920 × 1080 pixels) 14% more expensive than the same size a-Si TFT-LCD.

Therefore, there is a need for manufacturing techniques that allow for the production of less expensive TFT backplanes.

Disclosure of Invention

Methods for fabricating carbon nanotube thin film transistor backplanes and integrating them into displays are provided.

Many embodiments are directed to methods for fabricating a single-walled carbon nanotube thin film transistor backplane, the method comprising:

providing a substrate;

depositing an insulator comprising a thin film layer of single-walled carbon nanotubes atop the substrate; and is

Patterning at least the drain and source electrodes, the dielectric, the one or more top gate electrodes, and the one or more pixel electrodes atop the insulator using a photomask and photolithography process.

In other embodiments, the insulator is deposited by a spray technique selected from the group consisting of aerosol spray, air spray, and ultrasonic spray.

In some such embodiments, the single-walled carbon nanotube aerosol is formed by a technique selected from the group consisting of: ultrasonic atomization at a voltage ranging from 20V to 48V and pneumatic atomization with an atomizer flow rate of about 600 cubic centimeters per minute to generate an aerosol having a diameter of about 1 μm to 5 μm; and wherein the aerosol is carried to the spray head by a carrier gas flow rate of about 10 cubic centimeters to 20 cubic centimeters per minute.

In yet other such embodiments, the single-walled carbon nanotube aerosol is formed from an aqueous solution of single-walled carbon nanotubes that are ultrasonically and emitted at a carrier gas flow rate of about 10 to 20 cubic centimeters per minute in an ultrasonic nozzle.

In yet other embodiments, the insulator is printed atop the substrate using aerosol jet printing as a single-walled carbon nanotube aerosol.

In some such embodiments, the single-walled carbon nanotube aerosol is formed by a technique selected from the group consisting of: ultrasonic atomization at a voltage ranging from 20V to 48V and pneumatic atomization with an atomizer flow rate of about 600 cubic centimeters per minute to generate aerosols having a diameter of 1 μm to 5 μm; and wherein the aerosol is carried by a carrier gas flow of 10 to 20 cubic centimeters per minute to a fine nozzle of less than 100 μm and is focused through a sheath gas flow of 25 to 50 ccm.

In other such embodiments, the deposited line width is less than 10 μm, while having an alignment accuracy of <2 μm.

In yet other embodiments, the single-walled carbon nanotubes are high-purity single-chiral single-walled carbon nanotubes.

In some such embodiments, the single-walled carbon nanotubes have an index selected from the group consisting of (6, 4), (9, 1), (8, 3), (6, 5), (7, 3), (7, 5), (10, 2), (8, 4), (7, 6), (9, 2), and mixtures thereof.

In yet other embodiments, the single-walled carbon nanotube film is formed from a plurality of discrete films.

In some such embodiments, the discrete single-walled carbon nanotube film is patterned using a photomask lithography process.

In yet other embodiments, the method further comprises treating the single-walled carbon nanotube film with an acidic gas.

In some such embodiments, the acid gas is deposited via aerosol spraying.

In still other such embodiments, the method further comprises washing the treated single-walled carbon nanotube film with isopropanol.

In still other such embodiments, the method further comprises sintering the single-walled carbon nanotube film at a temperature of from about 100 ℃ to 200 ℃.

In yet other embodiments, forming a thin film having a subthreshold leakage current comprises:

spin coating photoresist on the single-walled carbon nanotube film;

defining a pattern on top of the photoresist by photolithography to create areas of defined photoresist and undefined photoresist;

solution developing the defined pattern to form a developed photoresist; and is

Plasma or wet etching the single-walled carbon nanotube film using the developed photoresist to form a patterned single-walled carbon nanotube film.

In yet other embodiments, a method includes integrating a single-walled carbon nanotube thin film transistor backplane into a display device.

Various other embodiments are directed to a system configured to deposit a single-walled carbon nanotube thin film transistor backplane, the system comprising:

a plurality of print heads mounted in association with the mobile station;

the plurality of print heads are in fluid communication with a solution of an aqueous solution of single-walled carbon nanotubes for depositing a thin film of single-walled carbon nanotubes atop a substrate deposited on the moving stage; and is

Wherein the print head is integrated with a photomask and lithography process for patterning and forming at least the drain and source electrodes, the dielectric, the one or more top gate electrodes and the one or more pixel electrodes on top of the deposited thin film.

Additional embodiments and features are set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the specification or may be learned by practice of the invention. A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the drawings which form a part hereof.

Drawings

The specification will be more fully understood with reference to the following drawings and data graphs, which are presented as exemplary embodiments of the invention and are not to be construed as a complete illustration of the scope of the invention, wherein:

fig. 1 provides a data graph illustrating absorption spectra of single-walled carbon nanotubes according to an embodiment of the present invention.

Fig. 2a and 2b provide schematic illustrations of exemplary vertical light emitting transistors according to embodiments of the present invention.

Fig. 3 a-3 k provide schematic illustrations of a method of forming an etch-stop vertical light emitting transistor, according to an embodiment.

Fig. 4 a-4 f provide schematic illustrations of a method of forming a vertical light emitting transistor according to an embodiment.

Fig. 5a to 5c provide schematic illustrations showing: a) a plurality of spray heads for a solution spray apparatus in a mobile station, b) a spray gun for ultrasonic spraying, and c) an aerosol spray system, each according to an embodiment of the present invention.

Fig. 6 provides an image of a spray gun sprayed carbon nanotube film according to an embodiment of the present invention.

Fig. 7 provides an image of an aerosol sprayed carbon nanotube film according to an embodiment of the invention.

Fig. 8 is an Atomic Force Microscope (AFM) image of a spray gun sprayed single-walled carbon nanotube film according to an embodiment of the present invention.

Fig. 9 is an Atomic Force Microscope (AFM) image of an aerosol sprayed single-walled carbon nanotube film according to an embodiment of the present invention.

Figure 10 provides a flow diagram illustrating a fabrication process for fabricating a top-gate carbon nanotube TFT backplane according to an embodiment of the present invention.

Fig. 11 provides an image of an aerosol printer for printing a carbon nanotube pattern on drain/source indicia according to an embodiment of the present invention.

Fig. 12 provides a photograph and optical image of a drain/source mark prior to aerosol printing of a single-walled carbon nanotube patterned film according to an embodiment of the invention.

Fig. 13 provides a photograph and optical image of an aerosol printed single-walled carbon nanotube patterned film on drain/source indicia according to an embodiment of the invention.

Fig. 14 provides an optical image of an aerosol jet printed carbon nanotube film according to an embodiment of the invention, and wherein the inset is an SEM image.

Fig. 15 provides an optical image of an aerosol jet printed carbon nanotube film on a lithographically patterned electrode according to an embodiment of the present invention, and wherein the inset is an IV curve of such a carbon nanotube film showing purely semiconductor properties.

Figure 16 provides a photographic image of a device having multiple aerosol jet printer heads mounted on a roll-to-roll table according to an embodiment of the present invention.

Fig. 17 provides a flow chart illustrating a manufacturing process for manufacturing a standard bottom gate a-Si TFT backplane according to the prior art.

Figure 18 provides a flow chart illustrating a fabrication process for fabricating a top-gate carbon nanotube TFT backplane according to an embodiment of the present invention.

Figure 19 provides a flow chart illustrating a fabrication process for fabricating a top-gate printed carbon nanotube TFT backplane according to an embodiment of the present invention.

Figure 20 provides a cross-sectional view of a single-walled carbon nanotube thin film transistor according to an embodiment of the present invention.

Detailed Description

Turning to figures, apparatus, materials and methods for producing and integrating single-walled carbon nanotubes (SWCNTs) into existing TFT backplane fabrication lines. In particular, SWCNT TFT backplanes exhibit equivalent or better quality factors such as high field emission mobility, low temperature fabrication, good stability, uniformity, scalability, flexibility, transparency, mechanical deformability, low voltage and power, flexibility, and low cost compared to LTPS and oxide TFT backplanes. Accordingly, many embodiments are directed to methods and processes for integrating SWCNT technology into existing TFT backplane fabrication lines without additional capital expenditure to begin preliminary testing and mass production. Moreover, other embodiments are directed to methods and processes for integrating such SWCNT TFT backplanes into video displays, including high-end glass-free 3-D and ultra-clear panel displays such as head-mounted displays (HMDs) in various embodiments. Hereinafter, the carbon nanotube refers to a single-walled carbon nanotube including a high-purity single-chiral SWCNT such as SWCNTs having an index of (6, 4), (9, 1), (8, 3), (6, 5), (7, 3), (7, 5), (10, 2), (8, 4), (7, 6), (9, 2), and a mixture thereof.

Active Matrix Organic Light Emitting Displays (AMOLEDs) are attractive due to their power saving, ultra high definition and wide viewing angle. In particular, advances in Organic Light Emitting Transistors (OLETs) have shown improved external efficiency over Organic Light Emitting Diodes (OLEDs) by directly modulating the charge carriers of the light emitting material. Furthermore, by providing short channel lengths, the introduction of vertical structures in OLETs avoids the inherently low mobility of organic materials, such that high conductivity can be achieved at low power and low voltage, thus enhancing the energy conversion efficiency, lifetime and stability of the organic materials. Furthermore, combining Thin Film Transistor (TFT) switches with OLED light emitting properties in a single device results in simplified manufacturing processes and reduced costs. However, the technical challenges of forming the underlying TFT backplane in these devices limit display size variation and cost reduction. As will be described below, the use of novel SWCNT materials and fabrication combinations, such as highly transparent porous conductive SWCNT electrodes, enables the formation of SWCNT TFTs that can be incorporated into fabrication lines for TFT backplanes, overcoming the limitations of display backplanes fabricated with amorphous/single crystalline/polycrystalline silicon, metal oxides and organic materials, and will be adaptable to various needs.

Accordingly, various embodiments are directed to methods of integrating printed SWCNT technology into a-Si TFT-LCD fabrication lines. With such SWCNT backplanes, the higher mobility enables LTPS TFT backplanes with higher pixel density, lower power consumption, and integration with driver circuitry on the glass substrate.

SWCNT selection/purification techniques

With the advent of separation techniques, ultra-pure single-walled carbon nanotubes with purity greater than 95% can be produced and scaled up for bulk handling. Using these processes, high-purity mono-chiral SWCNTs with various indices can be produced. In many embodiments, high purity mono-chiral SWCNTs and mixtures comprising SWCNTs having indices of (6, 4), (9, 1), (8, 3), (6, 5), (7, 3), (7, 5), (10, 2), (8, 4), (7, 6), (9, 2) are formed. The NIR-Vis absorption spectra of SWCNTs (6, 5) are presented in FIG. 1 to show the main S11 and S22 peaks at 978nm and 562 nm. Their electrical properties are characterized as characteristics of pure semiconductors with negligible off-current (I-V curves are provided in the inset of fig. 1). Thus, using such techniques, the purity of these materials can be ensured via conventional spectroscopy, and their electrical properties determined for selection.

TFT backplane fabrication

Embodiments are directed to methods and processes for replacing an amorphous silicon layer with ultrapure semiconductor single-walled carbon nanotubes in an industrial TFT backplane fabrication line. In particular, as shown in fig. 2a and 2b, the CNT layer according to embodiments may be implemented in a bottom gate etch stop CNT TFT (e.g., fig. 2a) and a bottom gate backside channel etch CNT TFT (e.g., fig. 2b), among others. However, although the methods and processes will be described with reference to a particular TFT backplane configuration, it should be understood that any TFT backplane design that can replace a silicon layer with a CNT layer can be implemented in accordance with embodiments, including, for example, coplanar TFTs, short channel TFTs, staggered TFTs, planar TFTs, and self-aligned TFTs.

While many processes may be used to form such CNF TFTs including certain bottom gate etch stop CNT TFTs, many such embodiments use processes as outlined in fig. 3 a-3 k and described below. As shown, this method requires multiple process steps into which the CNT layer is integrated. These steps include:

preparing the substrate and forming a patterned gate electrode on top of the substrate (fig. 3 a).

Depositing a gate electrode dielectric on top of the gate electrode layer (fig. 3 b).

Depositing a CNT thin film backside layer on top of the dielectric layer (fig. 3 c).

Depositing a CNT protection layer on top of the CNT thin film backside layer (fig. 3 d).

Patterning the CNT protection layer to expose portions of the CNT backside layer above the gate electrode, leaving at least the edges of the CNT thin film covered by the CNT protection layer (fig. 3 e).

Depositing an etch stop dielectric layer on top of the exposed part of the CNT thin film and the remaining CNT protection layer (fig. 3 f).

Patterning and etching the etch stop dielectric layer to selectively deposit a second dielectric layer on top of the portion of the CNT thin film over the gate electrode (fig. 3 g).

Remove the remaining CNT protection layer to expose the CNT film on the edges of the gate electrode channel (fig. 3 h).

Depositing an n + doped layer on top of the CNT thin film and the etch stop dielectric layer (fig. 3 i).

Depositing a drain/source electrode layer on top of the n + doped layer (fig. 3 j).

Patterning and etching the drain/source electrodes (fig. 3 k).

Such a process of Etch Stop (ES) CNT TFT requires some additional deposition steps, however it may be advantageous in certain aspects because it has an etch stop layer that protects the backside channel so the intrinsic layer may be kept thin (e.g., less than about 200 nm). Although described above, it is to be understood that the CNT backside channel layer may also be combined with other structures and techniques including, for example, Backside Channel Etch (BCE) TFTs. An exemplary process for such BCE TFTs is provided in fig. 4a to 4f and described below. These steps include:

preparing the substrate and forming a patterned gate electrode on top of the substrate (fig. 4 a).

Depositing a gate electrode dielectric on top of the gate electrode layer (fig. 4 b).

Depositing both the drain/source electrode and the n + doped layer on top of the dielectric layer (fig. 4 c).

Patterning and etching the drain/source electrodes and the n + layer (fig. 4 d).

Depositing a CNT thin film backside layer on top of the n + layer (fig. 4 e).

Depositing a passivation layer on top of the CNT thin film backside layer (fig. 4 f).

Although the above methods are described in fig. 3 and 4 with respect to a specific deposition technique, it should be understood that many alternative embodiments and techniques may be used in conjunction with the CNT backside layer according to embodiments.

For example, in some such embodiments, a substrate having a gate electrode formed thereon is provided, as shown in fig. 3a and 4 a. Although the substrate in the figures is listed as being glass, it should be understood that any material that has sufficient optical transmission (e.g., about 80% or greater in many embodiments) and is resistant to degradation at industry standard processing temperatures (e.g., 100 ℃ and higher) may be used. Exemplary substrate materials may include glass, polyethylene terephthalate (PET), Polyethersulfone (PES), Polyacrylate (PAR), and Polycarbonate (PA), among others. Similarly, the gate electrode itself may be made of any suitable metal, such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, or W, or an alloy of two or more of these metals. The gate metal layer may be a single-layer structure or a multi-layer structure, and the multi-layer structure may be, for example, Cu \ Mo, Ti \ Cu \ Ti, Mo \ Al \ Mo, or the like. As shown in fig. 3a and 4a, the thickness of the gate electrode may be any suitable dimension, such as from 10nm to greater than 100 μm, and in some embodiments about 400 nm.

Likewise, while the process for depositing the gate electrode is listed as including steps of sputtering and patterning, it should be understood that many suitable and standard industry processes may be used to pattern and deposit the gate electrode atop the substrate. Sputtering (or physical vapor deposition), for example, may include one or a combination of electron, electrical potential, etching, and chemical sputtering, among others. The deposition techniques may alternatively include, for example, Chemical (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), thermal evaporation, and/or the like.

Similarly, patterning of the underlying gate electrode can comprise any suitable photolithographic process, such as wet or dry etching, including the use of any suitable photoresist and etch chemistries. In many such embodiments, the gate electrode layer may be coated with a suitable photoresist layer, and the photoresist may then be exposed and developed through a mask plate to form photoresist unreserved regions and photoresist reserved regions, respectively. In many such embodiments, the photoresist-remaining regions correspond to regions where the gate electrodes are disposed, and the photoresist-unreserved regions correspond to other regions. In such an embodiment, the gate metal layer of the photoresist-unreserved region may be completely etched away by the etching process, and the remaining photoresist is removed, thereby forming the gate electrode.

Once the gate electrode is formed, a suitable dielectric layer is formed atop the substrate and the gate electrode layer, as shown in fig. 3b and 4 b. Further, although a PECVD process and a SiN dielectric material are specified in the figures, it should be understood that any suitable dielectric material and deposition process may be combined with the method. For example, in many embodiments, the dielectric layer may be made of inorganic and organic materials, oxides, nitrides, or oxynitrides (such as, for example, SiNx, SiOx, TaOx, AlOx, or si (on) x). Also, the dielectric layer may be a single layer structure, a double layer structure, or a multi-layer structure. The thickness of such a structure may take any dimension suitable for providing the dielectric function. In addition, a dielectric layer can be formed atop the substrate and the gate electrode by any suitable film formation process, including, for example, magnetron sputtering, thermal evaporation, CVD (remote plasma, photocatalytic, etc.), PECVD, spin coating, liquid phase growth, etc. In various such embodiments, as shown in FIGS. 3b and 4b, the CNT TFT comprises SiNx/SiO deposited via PECVD to a thickness of about 200nm₂And (3) a layer. Finally, if desired, such dielectric materials (including SiHx, NHx, N) may be used₂And hydrogen radicals and ions) to produce various raw material gas molecules. Similar techniques and materials may be used for other passivation layers, including those formed in fig. 3f and the passivation layer shown in fig. 4 f. In these steps, the deposition temperature and thickness of the passivation material may be selected as desired.

Regardless of whether the TFT is an ES TFT or a BEC TFT, all TFTs also require the deposition of n + and drain/source layers, as shown in FIGS. 3i and 3j and FIG. 4 c. Although sputter deposition of an approximately 400nm Mo drain/source layer and PECVD deposition of a thin (approximately 10nm) n + doped layer are illustrated, it should be understood that any suitable combination of deposition techniques and materials may be utilized. For example, the drain/source electrode layer may be made of any suitable metal, such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, or W, or an alloy of two or more of these metals. The gate metal layer may be a single-layer structure or a multi-layer structure, and the multi-layer structure may be, for example, Cu \ Mo, Ti \ Cu \ Ti, Mo \ Al \ Mo, or the like. As shown in the figure, the thickness of the gate electrode may similarly be any suitable dimension, such as from 10nm to greater than 100 μm, and in some embodiments about 400 nm. Likewise, while the process for depositing the electrode is listed as including the steps of sputtering and patterning, it should be understood that many suitable and standard industry processes may be used to pattern and deposit the gate electrode atop the substrate. Sputtering (or physical vapor deposition), for example, may include one or a combination of electron, electrical potential, etching, and chemical sputtering, among others. The deposition techniques may alternatively include, for example, Chemical (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), thermal evaporation, and/or the like.

Similarly, any suitable n + material may be incorporated into the TFT, including, for example, n + doped amorphous Si or other suitable semiconductors (including gallium arsenide and phosphide and cadmium telluride and sulfide), depending on the embodiment. Likewise, suitable plasma and/or n-type dopant materials may be used with such semiconductors, including, for example, phosphorus, arsenic, antimony, bismuth, lithium, beryllium, zinc, chromium, germanium, magnesium, tin, lithium, and sodium. Also, as noted above, these materials may be deposited using any suitable deposition technique, including thermal, physical, plasma, and chemical vapor deposition techniques. Some suitable techniques include, for example, aerosol-assisted CVD, direct liquid injection CVD, microwave plasma-assisted CVD, atomic layer CVD, combustion chemical vapor deposition, hot-filament CVD, hybrid physical chemical vapor deposition, rapid thermal CVD, vapor phase epitaxy, and photo-induced CVD. Alternatively, atomic layer deposition may replace CVD for thinner and more precise layers.

Many steps in such processes also require patterning and etching of materials (see, e.g., 3e, 3h, 3k, and 4 d). In such processes, any suitable patterning and etching techniques may be incorporated with the embodiments. In particular, many of the steps include a patterning process by which a passivation layer is deposited and patterned through the passivation layer. In particular, in many embodiments, the passivation layer may be coated with any suitable photoresist layer. In such an embodiment, the photoresist may be exposed and developed through a mask plate to form the photoresist unreserved region and the photoresist remaining region, respectively. For example, in various embodiments, the photoresist of the unreserved region may correspond to a region of the via in which the passivation layer is disposed.

Any suitable optical lithography technique may be used, including, for example, immersion lithography, bi-tone resist and multiple patterned electron beam lithography, X-ray lithography, extreme ultraviolet lithography, ion projection lithography, extreme ultraviolet lithography, nanoimprint lithography, dip pen nanolithography, chemical lithography, soft lithography, and magnetic lithography, among others.

Regardless of the particular technique and light source used, such lithographic techniques typically involve several steps. In many embodiments, the layer to be patterned is first coated with a photoresist, such as by spin coating. In such techniques, a viscous liquid solution of photoresist is dispensed onto a wafer, and the wafer is spun rapidly to produce a uniformly thick layer. Spin coating is typically run at 1200 to 4800rpm for 30 to 60 seconds and produces a layer 0.5 to 2.5 microns thick. The spin coating process produces a thin, uniform layer, typically having a uniformity of 5 to 10 nanometers or more. In various embodiments, the photoresist-coated material may then be pre-baked (typically at 90 to 100 ℃ for 30 to 60 seconds on a hot plate) to drive off excess photoresist solvent. After etching the unmasked portion of the layer by liquid ("wet") or plasma ("dry") chemistry, to remove the uppermost layer of the substrate in areas not protected by photoresist. After the photoresist is no longer needed, the photoresist is then removed from the substrate. The photoresist may be removed chemically or by plasma or by heating.

Although specific deposition and patterning methods are disclosed, as well as specific materials for substrates, electrodes, dielectrics, passivation layers, etc., and specific conditions including thicknesses, temperatures, etc., it will be understood that any of these parameters may be adjusted as desired for specific TFT configurations and operating parameters without radically changing the principles of the embodiments incorporating CNTs disclosed herein.

SWCNT deposition techniques

Turning to embodiments of methods for depositing CNT layers in TFTs, in many embodiments, various techniques including various deposition and spray coating methods may be used.

In many embodiments, the single-walled carbon nanotube film is solution coated using a spray coating technique such as air, aerosol, or ultrasonic spray in conjunction with a mobile station manufacturing line, as described with respect to fig. 5 a-5 c. As shown in fig. 5a, in many embodiments, a moving stage is provided on which the substrate is loaded, and the carbon nanotube solution can be sprayed (e.g., by aerosol or air spraying) onto a substrate of suitable size (e.g., 4"-100") while heating the moving stage and the carbon nanotube solution at a desired process temperature (e.g., from 60-200 ℃, or any temperature allowed by the underlying material and the CNT material itself). In such embodiments, the speed of movement of the stage can be controlled to maintain film thickness and uniformity (e.g., 1mm/s-1000 mm/s).

In other embodiments, ultrasonic spraying may be used. As shown in fig. 5b, in such embodiments, the compressed air flow passes through an aspirator that causes a local reduction in air pressure to allow the carbon nanotube solution to be drawn from the container at normal atmospheric pressure. During the treatment, the ultrasonic nozzle atomizes the carbon nanotube solution into very fine droplets, e.g., from a few μm to around 1000 μm in diameter. The tiny droplets are then deposited onto a substrate at a suitable processing temperature (e.g., up to 400 ℃) such that the droplets immediately dry to mitigate O-ring polymerization. In various embodiments, a temperature of 100 ℃ may be used. While any suitable air pressure may be used (depending on the viscosity of the material), in many embodiments, the compressed air pressure may be in the range of 20psi (1.38bar) to 100psi (6.8bar), depending on the solution viscosity and the size of the aspirator required for deposition.

In embodiments incorporating aerosol spray coating (as shown in FIG. 5 c), the carbon nanotube solution can be atomized using high pressure gas (e.g., 200-1000 standard cubic centimeters per minute (sccm)) or sonication (e.g., 20V-48V, 10-100 watts) to produce 1-5 micron aerosols that are carried to the showerhead by a carrier gas (e.g., 10-30 sccm). It should be understood that these process parameters are merely exemplary, and that other deposition properties may be used depending on the type of material, the desired properties of the aerosol, and the thickness of the coating to be formed.

Fig. 6 and 7 show images of thin films of SWCNTs sprayed onto a substrate using a spray gun technique (fig. 6) and using an aerosol technique (fig. 7), according to embodiments. In many embodiments, the carbon nanotube film thus formed is treated with acetic acid gas generated by spray gun spraying or aerosol spraying, and then washed with isopropyl alcohol to obtain a clean carbon nanotube surface. The clean carbon nanotube surface was characterized using Atomic Force Microscopy (AFM). Because of the high insulating properties of glass substrates, these samples cannot be characterized on such substrates using scanning electron microscopy. As shown, fig. 8 provides an AFM image of a spray gun sprayed SWCNT thin film, and fig. 9 provides an AFM image of an aerosol sprayed SWCNT thin film. This image provides evidence of the robust nature of the deposition process, as well as the ability to deposit high quality thin film coatings of SWCNTs.

In an embodiment, a carbon nanotube film formed according to such a spray coating process is used to replace amorphous silicon in a 4-photomask lithography process to pattern drain/source electrodes, dielectric, top gate electrode, and pixel electrode according to industry manufacturing standard methods, as described above with respect to fig. 3 and 4.

Although shown in FIGS. 3 and 4The embodiments shown are shown as extending beyond the channel in order to reduce sub-threshold current leakage, but other embodiments may employ at least one additional photomask to pattern the active carbon nanotube sheet using photolithography. In such embodiments, this may be by a process such as, for example, O₂A suitable etching technique, such as plasma or wet etching, removes the CNT layer outside the transistor channel. In various such embodiments, the clean, uniform carbon nanotube film may be coated with a Photoresist (PR) and exposed to light, and then developed with a solution. On these developed areas, use is made of, for example, O₂Plasma or wet chemical etching (such as buffered HF solution) to etch the carbon nanotube film. The undeveloped PR is then stripped away to leave a patterned carbon nanotube film. A flow chart providing one embodiment of such a method is provided in fig. 10. It should be understood that any of the steps and techniques listed in the flow chart may be substituted as alternatives as detailed above.

In yet other embodiments, to reduce the use of additional photomasks to pattern the active carbon nanotubes and reduce the consumption of the carbon nanotube solution, a SWCNT film may be printed on top of the substrate. In many such embodiments, an aerosol jet printer may be used to print active carbon nanotube films using small nozzle sizes (e.g., < 100 μm). The aerosol jet printer can deposit line widths <10 μm with alignment accuracy <2 μm. To this end, the aerosol jet printer prints carbon nanotubes on patterned drain/source marks. An image of such an aerosol printing device is provided in fig. 11. Fig. 12 shows a photograph and optical image of exemplary drain/source marks before printing SWCNT films. Fig. 13 provides photographic and optical images of SWCNT films printed on drain/source marks. As described above, the aerosol jet printed carbon nanotubes may be treated with an acetic acid gas by aerosol spray or spray gun spray, and then washed with isopropyl alcohol. These clean carbon nanotube films can then be characterized by SEM. According to an example, SEM images (fig. 14) show a clean carbon nanotube film on drain/source marks. As shown in fig. 15, clean carbon nanotube films have been characterized by a Keithly 4200 semiconductor characterization system to show semiconductor properties.

To further take advantage of the low cost, low environmental impact and large area manufacturing due to the small number of process steps, limited material volume and high manufacturing volume, embodiments propose the above-described aerosol jet printing method (including its high accuracy: alignment accuracy of 1-2 μm) with a roll-to-roll system of high speed processing. With such a roll-to-roll aerosol jet printer, SWCNT inks can be printed in a fast manner for high volume manufacturing in an a-Si TFT backplane manufacturing line. In addition, fully printed SWCNT TFT backplanes can be manufactured in large quantities using a roll-to-roll system. To match industrial speeds, embodiments disclose multiple aerosol jet printer heads mounted on a moving stage, such as shown in fig. 16, which can be used to print carbon nanotube films at high speeds. Such multiple aerosol jet printer heads can print a large number of carbon nanotube patterns on a moving table.

Exemplary embodiments

Additional embodiments and features are set forth in part in the exemplary embodiments below and, in part, will become apparent to those skilled in the art upon examination of the description or may be learned by practice of the invention. The specific embodiments are not intended to limit the scope of the remainder of the specification and the drawings, and they are provided as examples of the apparatus, methods, and materials disclosed herein. In particular, although specific configurations and specific combinations of materials are enumerated, it should be understood that these are provided as examples only, and may be substituted for any suitable alternative architectures and materials.

Example 1: comparison of conventional a-Si TFT and CNT TFT technologies

A flow chart of an exemplary method for fabricating an amorphous silicon TFT backplane on a fabrication line is provided in fig. 17. As shown in the method, amorphous silicon is deposited over a large area by plasma enhanced chemical vapor deposition, and then other devices are fabricated according to other conventional fabrication steps. In an embodiment, amorphous silicon may be replaced with CNTs. Such CNT films may be deposited and/or printed according to the techniques previously described. Using such a clean carbon nanotube film according to embodiments, as described in fig. 18 and/or fig. 19, the drain/source electrode, the dielectric, the top gate electrode, and the pixel electrode may be further patterned using standard industrial fabrication methods.

Example 3: SWCNT TFT

Using the techniques described above, a single-walled carbon nanotube thin film transistor can be formed, for example, as shown in fig. 20.

Example 2: display device

Finally, while the above exemplary embodiments and discussion have focused on methods, architectures, and structures for separate devices and backplanes, it will be understood that the same architectures and structures may be combined as pixels into a display device. In such embodiments, a plurality of SWCNT TFTs as described herein may be combined and interconnected, such as by electrically coupling devices into addressing electrode lines to form a TFT backplane for a display, such as an AMOLED display, as known to those skilled in the art.

Principle of equivalence

Having described several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the invention. In other instances, well-known processes and principles have not been described in order to avoid unnecessarily obscuring the present invention. Accordingly, the above description should not be taken as limiting the scope of the invention.

Those skilled in the art will appreciate that the presently disclosed embodiments are taught by way of example and not by way of limitation. It is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense. The following claims are intended to cover all generic and specific features described herein, and all statements of the scope of the present method and system, which, as a matter of language, might be said to fall therebetween.

Claims

1. A method for fabricating a single-walled carbon nanotube thin film transistor backplane, comprising:

providing a substrate;

patterning the gate electrode and the dielectric layer on the substrate to form a channel;

depositing a back layer of a thin film layer comprising single-walled carbon nanotubes on the dielectric layer; and is

At least the n + layer and the drain and source electrodes on the back layer are patterned using a photomask and a photolithography process so that a portion of the back layer overlapping the channel is exposed.

2. The method of claim 1, wherein the backing layer is deposited by a spray technique selected from the group consisting of aerosol spray, air spray, and ultrasonic spray.

3. The method of claim 2, wherein the single-walled carbon nanotube aerosol is formed from an aqueous solution of single-walled carbon nanotubes that are ultrasonically and emitted in a carrier gas flow in an ultrasonic nozzle.

4. The method of claim 1, wherein the backing layer is printed atop the substrate using aerosol jet printing as a single-walled carbon nanotube aerosol.

5. The method of claim 4, wherein the single-walled carbon nanotube aerosol is formed by a technique selected from ultrasonic atomization.

6. The method of claim 5, wherein the deposited line width is less than 10 μm with an alignment accuracy of <2 μm.

7. The method of claim 1, wherein the single-walled carbon nanotubes are high-purity single-chiral single-walled carbon nanotubes.

8. The method of claim 8, wherein the single-walled carbon nanotubes have an index selected from the group consisting of (6, 4), (9, 1), (8, 3), (6, 5), (7, 3), (7, 5), (10, 2), (8, 4), (7, 6), (9, 2), and mixtures thereof.

9. The method of claim 1, wherein the single-walled carbon nanotube film is formed from a plurality of discrete films.

10. The method of claim 1, further comprising depositing and patterning an etch stop layer atop the back layer such that the etch stop overlaps the channel.

11. The method of claim 1, further comprising treating the single-walled carbon nanotube film with an acid gas.

12. The method of claim 12, wherein the acid gas is deposited via aerosol spraying.

13. The method of claim 12, further comprising washing the treated single-walled carbon nanotube film.

14. The method of claim 14, further comprising sintering the single-walled carbon nanotube film at a temperature of at least 100 ℃.

15. The method of claim 1, wherein forming a thin film having a subthreshold leakage current comprises:

spin-coating a photoresist on the single-walled carbon nanotube film;

defining a pattern on top of the photoresist by photolithography to create defined photoresist and undefined regions of photoresist;

solution developing the defined pattern to form a developed photoresist; and is

16. A method for fabricating a single-walled carbon nanotube thin film transistor backplane, comprising:

providing a substrate;

patterning a gate electrode and a dielectric layer on a substrate to form;

patterning at least the n + layer and the drain and source electrodes on the dielectric layer using a photomask and a photolithography process such that portions of the dielectric that overlap the channel are exposed;

depositing a back layer of a thin film layer comprising single walled carbon nanotubes on the n + layer, drain and electrode layers and dielectric layer; and is

A passivation layer is deposited on the back layer.

17. The method of claim 17, wherein the backing layer is deposited by a spray technique selected from the group consisting of aerosol spray, air spray, and ultrasonic spray.

18. The method of claim 17, wherein the backing layer is printed atop the substrate using aerosol jet printing as a single-walled carbon nanotube aerosol.

19. The method of claim 17, wherein the single-walled carbon nanotubes are high-purity single-chiral single-walled carbon nanotubes.

20. The method of claim 20, wherein the single-walled carbon nanotubes have an index selected from the group consisting of (6, 4), (9, 1), (8, 3), (6, 5), (7, 3), (7, 5), (10, 2), (8, 4), (7, 6), (9, 2), and mixtures thereof.

21. The method of claim 1 or 17, further comprising integrating the single-walled carbon nanotube thin film transistor backplane into a display device.

22. A system configured to deposit a single-walled carbon nanotube thin film transistor backplane, comprising:

a plurality of print heads mounted in association with the mobile station;

Wherein a print head is integrated with a photomask and photolithography process for patterning and forming at least drain and source electrodes, a dielectric, one or more top gate electrodes, and one or more pixel electrodes on top of the deposited thin film.