CN111147069A - Frequency division output method for arbitrary pulse - Google Patents
Frequency division output method for arbitrary pulse Download PDFInfo
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- CN111147069A CN111147069A CN201911360742.4A CN201911360742A CN111147069A CN 111147069 A CN111147069 A CN 111147069A CN 201911360742 A CN201911360742 A CN 201911360742A CN 111147069 A CN111147069 A CN 111147069A
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000001208 nuclear magnetic resonance pulse sequence Methods 0.000 claims abstract description 6
- 238000004891 communication Methods 0.000 abstract description 4
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- 238000006243 chemical reaction Methods 0.000 description 3
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/08—Output circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
- G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
- G01D5/244—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trains; generating pulses or pulse trains
- G01D5/245—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trains; generating pulses or pulse trains using a variable number of pulses in a train
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
- G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
- G01D5/244—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trains; generating pulses or pulse trains
- G01D5/249—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trains; generating pulses or pulse trains using pulse code
- G01D5/2497—Absolute encoders
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- General Physics & Mathematics (AREA)
- Control Of Electric Motors In General (AREA)
Abstract
The invention discloses an arbitrary pulse frequency division output method, which is realized based on a servo motor and a servo driver, wherein the servo driver comprises an arithmetic processor, the servo motor comprises an encoder, and an encoder interface establishes communication with the arithmetic processor, and the method comprises the following steps: step S1, the arithmetic processor obtains the current data of the shaft encoder through the encoder interface; step S2, reconstructing shaft encoder data in a preset time period by the arithmetic processor, and generating a high-frequency pulse signal corresponding to the shaft position by using the high main frequency of the arithmetic processor according to the shaft encoder data; step S3, the arithmetic processor forms an original high-frequency pulse sequence of the shaft according to the reconstructed shaft encoder data; in step S4, the arithmetic processor forms a pulse train of the frequency-divided output based on the input parameters. The invention can completely and accurately realize the frequency division output function, reduce the resource consumption of the operation processor and save the hardware cost without reducing the system performance.
Description
Technical Field
The invention relates to a servo motor encoder data output method, in particular to an arbitrary pulse frequency division output method.
Background
At present, frequency division output is widely applied to machine tool equipment so as to explain a pulse frequency division output technology in the machine tool application. The pulse frequency division output function refers to a function that a servo driver converts position information received from a motor shaft encoder into pulse strings and feeds the pulse strings back to an upper computer, a frequency division ratio is an important parameter for describing the frequency division function, and the frequency division ratio is defined as: and dividing the ratio of the equivalent pulse number of the output circuit to the equivalent pulse number of the shaft encoder within one rotation of the motor. The formula is expressed as follows:
K＝M/N；
wherein M is the number of pulses fed back to an upper computer by one-circle internal servo; n is the actual number of pulses of the servo motor shaft encoder in one circle, generally the resolution, and 17bit is 2^17 (0-131071).
Most of the current implementations are: the number and direction of pulses in unit time are calculated by a multiplier and a divider in combination with a frequency division ratio, then the counting period of the pulses is calculated according to the number and the direction of the pulses, and finally the corresponding pulses are counted and sent out.
In summary, the following problems mainly exist in the existing implementation schemes:
firstly, a multiplier and a divider are needed to calculate the pulse number of a pulse domain to realize the frequency division function, and more FPGA hardware resources are occupied;
secondly, when there is a decimal part in the calculated number of pulses per unit time, the decimal part needs to be accumulated to the next time period for continuous calculation, the real-time performance is poor, and there is distortion of feedback data.
Disclosure of Invention
The present invention provides an arbitrary pulse frequency division output method, which can completely and accurately implement the frequency division output function, reduce the resource consumption of the operation processor, and save the hardware cost without reducing the system performance, aiming at the deficiencies of the prior art.
In order to solve the technical problems, the invention adopts the following technical scheme.
An arbitrary pulse frequency division output method is realized based on a servo motor and a servo driver, wherein the servo driver comprises an arithmetic processor, the servo motor comprises an encoder, and an encoder interface is communicated with the arithmetic processor, and the method comprises the following steps: step S1, the arithmetic processor obtains the current data of the shaft encoder through the encoder interface; step S2, reconstructing shaft encoder data in a preset time period by the arithmetic processor, and generating a high-frequency pulse signal corresponding to the shaft position by using the high main frequency of the arithmetic processor according to the shaft encoder data; step S3, the arithmetic processor forms an original high-frequency pulse sequence of the shaft according to the reconstructed shaft encoder data; in step S4, the arithmetic processor forms a pulse train of the frequency-divided output based on the input parameters.
Preferably, in step S1, the arithmetic processor requests shaft encoder data at time Tn to obtain shaft encoder data Pn, where n is a number of a fixed time unit and the fixed time Ts is 62.5us on the way.
Preferably, the parameter input in step S4 includes a "frequency dividing ratio" or a "number of pulses per turn".
Preferably, in the step S4, the original shaft pulse number and the encoder resolution of a unit rotation are both N, and the output pulse number per rotation after frequency division is M, it can be known from the step S3 that each rotation has at least N equivalent shaft pulses, and the conversion is performed to realize an expression M/N in space, and the operation processor obtains N generation points of the shaft pulses according to the expression M/N, and the pulse generation points and the reconstructed pulse data have correlation.
Preferably, in step S4, the implementation of the expression M/N in space includes:
M/N＝(M*N)/(N*N)；
in the above expression, (M × N) is implemented in the arithmetic processor by using an adder, and at the generation point of each N pulse, a value of + M is determined, and then whether the value after the addition processing is greater than N is determined, if so, the pulse count value of the frequency division output domain is calculated as +1 or-1 according to the direction of the pulse.
Preferably, the arithmetic processor is an FPGA processor or a CPLD processor.
The invention discloses an arbitrary pulse frequency division output method, which fully utilizes the high main frequency characteristic of an operation processor such as FPGA and the like to completely reproduce the position information of a motor shaft to obtain an original high-frequency pulse signal, then completes the conversion from shaft pulse to frequency division domain pulse by utilizing the high-frequency characteristic of the operation processor again according to the parameter 'frequency division ratio' or 'pulse number per circle', does not need to consume the resources of a multiplier and a divider, can realize the reproduction of arbitrary shaft position information only by at most one adder and one subtracter, and then realizes the output of the arbitrary frequency division pulse by utilizing the adder and the subtracter again, thereby having the characteristics of less consumption of FPGA resources, strong real-time performance and the like.
Drawings
FIG. 1 is a timing diagram of a process of periodically requesting encoder data;
FIG. 2 is a timing diagram of the encoder data reconstruction process within a unit period;
FIG. 3 is a timing diagram of the process of generating a high frequency pulse sequence from reconstructed encoder data;
FIG. 4 is a schematic diagram of N pulse generation points within a circle;
fig. 5 is a schematic diagram of pulse frequency division output using a frequency division ratio as an example.
Detailed Description
The invention is described in more detail below with reference to the figures and examples.
The invention discloses an arbitrary pulse frequency division output method, which is realized based on a servo motor and a servo driver, wherein the servo driver comprises an arithmetic processor, the servo motor comprises an encoder, an encoder interface establishes communication with the arithmetic processor, and the method comprises the following steps:
step S1, the arithmetic processor obtains the current data of the shaft encoder through the encoder interface; and the communication with the encoder is a fixed period request; referring to fig. 1, in step S1, the arithmetic processor requests shaft encoder data at time Tn to obtain shaft encoder data Pn, where n is a number of a fixed time unit and the fixed time Ts in the middle is 62.5 us;
step S2, referring to fig. 2, the arithmetic processor reconstructs shaft encoder data within a preset time period, and generates a high-frequency pulse signal corresponding to the shaft position by using the high main frequency of the arithmetic processor according to the shaft encoder data;
step S3, referring to fig. 3, the arithmetic processor forms an original high-frequency pulse sequence of the shaft from the reconstructed shaft encoder data;
step S4, the arithmetic processor forms a pulse sequence of frequency division output according to the input parameters; the parameters input in step S4 include "frequency dividing ratio" or "number of pulses per turn".
Referring to fig. 4, in the step S4, the original axis pulse number and the encoder resolution of a unit rotation are both N, and the output pulse number of each loop after frequency division is M, it can be known from the step S3 that each loop has at least N equivalent axis pulses, which is converted into an expression M/N realized in space, and the operation processor obtains N generation points of the axis pulses according to the expression M/N, and the pulse generation points and the reconstructed pulse data have correlation.
Further, referring to fig. 5, in step S4, the implementation process of the expression M/N in space includes:
M/N＝(M*N)/(N*N)；
in the above expression, (M × N) is implemented in the arithmetic processor by using an adder, and at the generation point of each N pulse, a value of + M is determined, and then whether the value after the addition processing is greater than N is determined, if so, the pulse count value of the frequency division output domain is calculated as +1 or-1 according to the direction of the pulse.
Preferably, the arithmetic processor is an FPGA processor or a CPLD processor.
The invention discloses an arbitrary pulse frequency division output method, which fully utilizes the high main frequency characteristic of an operation processor such as FPGA and the like to completely reproduce the position information of a motor shaft to obtain an original high-frequency pulse signal, then completes the conversion from shaft pulse to frequency division domain pulse by utilizing the high-frequency characteristic of the operation processor again according to the parameter 'frequency division ratio' or 'pulse number per circle', does not need to consume the resources of a multiplier and a divider, can realize the reproduction of arbitrary shaft position information only by at most one adder and one subtracter, and then realizes the output of the arbitrary frequency division pulse by utilizing the adder and the subtracter again, thereby having the characteristics of less consumption of FPGA resources, strong real-time performance and the like.
In summary, compared with the prior art, the invention mainly has the following characteristics:
firstly, absolute value encoder information is reconstructed, a communication interface of an encoder can only receive position information of the encoder, and position detailed information of a sub-frequency domain can be reconstructed through reconstruction;
secondly, a multiplier and a divider are not needed, a multiplier and a divider are needed to convert the pulse of a motor encoder unit into the pulse number in the frequency division field in the general realization of pulse frequency division output, and the strategy provided by the invention can be realized without a multiplier/divider;
and thirdly, a division function is realized by at most one addition and subtraction in a frequency division output period, and pulse output with any frequency and number is uniformly and accurately output.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents or improvements made within the technical scope of the present invention should be included in the scope of the present invention.
Claims (6)
1. An arbitrary pulse frequency division output method is characterized in that the method is realized based on a servo motor and a servo driver, the servo driver comprises an arithmetic processor, the servo motor comprises an encoder, and an encoder interface is communicated with the arithmetic processor, and the method comprises the following steps:
step S1, the arithmetic processor obtains the current data of the shaft encoder through the encoder interface;
step S2, reconstructing shaft encoder data in a preset time period by the arithmetic processor, and generating a high-frequency pulse signal corresponding to the shaft position by using the high main frequency of the arithmetic processor according to the shaft encoder data;
step S3, the arithmetic processor forms an original high-frequency pulse sequence of the shaft according to the reconstructed shaft encoder data;
in step S4, the arithmetic processor forms a pulse train of the frequency-divided output based on the input parameters.
2. The arbitrary pulse frequency division output method according to claim 1, wherein in the step S1, the arithmetic processor requests shaft encoder data at time Tn, and obtains shaft encoder data Pn, where n is a number of fixed time units, and the fixed time Ts in the middle is 62.5 us.
3. The arbitrary pulse frequency division output method according to claim 1, wherein the parameter input in step S4 includes "frequency division ratio" or "number of pulses per turn".
4. The method as claimed in claim 1, wherein in step S4, the original axial pulse number and the encoder resolution are both N, and the output pulse number per revolution after frequency division is M, and it can be known from step S3 that at least N equivalent axial pulses per revolution are converted into the spatially implemented expression M/N, and the processor obtains the generation points of N axial pulses from the equivalent axial pulses, and the pulse generation points and the reconstructed pulse data have correlation.
5. The arbitrary pulse frequency division output method according to claim 4, wherein in the step S4, the implementation of the expression M/N in space includes:
M/N＝(M*N)/(N*N)；
in the above expression, (M × N) is implemented in the arithmetic processor by using an adder, and at the generation point of each N pulse, a value of + M is determined, and then whether the value after the addition processing is greater than N is determined, if so, the pulse count value of the frequency division output domain is calculated as +1 or-1 according to the direction of the pulse.
6. The arbitrary pulse frequency division output method according to claim 1, wherein said operation processor is an FPGA processor or a CPLD processor.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114347679A (en) * | 2021-12-31 | 2022-04-15 | 东莞市启思达智能技术有限公司 | Variable-precision signal processing method and system |
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| JPH07218289A (en) * | 1994-02-09 | 1995-08-18 | Yokogawa Electric Corp | Encoder system |
| CN102412828A (en) * | 2011-12-27 | 2012-04-11 | 哈尔滨工业大学 | Complex programmable logic device (CPLD) based arbitrary decimal frequency division system and method of orthogonal impulse of photoelectric coded disc |
| CN103185603A (en) * | 2011-12-29 | 2013-07-03 | 苏州汇川技术有限公司 | Incremental encoder signal processing system and method |
| CN105388817A (en) * | 2015-12-23 | 2016-03-09 | 珠海格力电器股份有限公司 | Pulse generation method and device |
| CN105553466A (en) * | 2015-12-03 | 2016-05-04 | 天津凌浩科技有限公司 | CPLD-based photoelectric coded disc orthogonal pulse arbitrary decimal frequency division method |
| CN106092156A (en) * | 2016-08-04 | 2016-11-09 | 泉州市桑川电气设备有限公司 | AC servo serial communication encoder position feedback pulse frequency dividing output system and method |
| CN106595724A (en) * | 2016-12-02 | 2017-04-26 | 中国科学院自动化研究所 | Incremental encoder frequency-dividing circuit |
| CN109714030A (en) * | 2018-12-26 | 2019-05-03 | 天津长荣数码科技有限公司 | A kind of pulse processing generation method and device |
-
2019
- 2019-12-25 CN CN201911360742.4A patent/CN111147069A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07218289A (en) * | 1994-02-09 | 1995-08-18 | Yokogawa Electric Corp | Encoder system |
| CN102412828A (en) * | 2011-12-27 | 2012-04-11 | 哈尔滨工业大学 | Complex programmable logic device (CPLD) based arbitrary decimal frequency division system and method of orthogonal impulse of photoelectric coded disc |
| CN103185603A (en) * | 2011-12-29 | 2013-07-03 | 苏州汇川技术有限公司 | Incremental encoder signal processing system and method |
| CN105553466A (en) * | 2015-12-03 | 2016-05-04 | 天津凌浩科技有限公司 | CPLD-based photoelectric coded disc orthogonal pulse arbitrary decimal frequency division method |
| CN105388817A (en) * | 2015-12-23 | 2016-03-09 | 珠海格力电器股份有限公司 | Pulse generation method and device |
| CN106092156A (en) * | 2016-08-04 | 2016-11-09 | 泉州市桑川电气设备有限公司 | AC servo serial communication encoder position feedback pulse frequency dividing output system and method |
| CN106595724A (en) * | 2016-12-02 | 2017-04-26 | 中国科学院自动化研究所 | Incremental encoder frequency-dividing circuit |
| CN109714030A (en) * | 2018-12-26 | 2019-05-03 | 天津长荣数码科技有限公司 | A kind of pulse processing generation method and device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114347679A (en) * | 2021-12-31 | 2022-04-15 | 东莞市启思达智能技术有限公司 | Variable-precision signal processing method and system |
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