CN111147050B - Anti-single-particle reinforcement CML transmitter - Google Patents
Anti-single-particle reinforcement CML transmitter Download PDFInfo
- Publication number
- CN111147050B CN111147050B CN201911330758.0A CN201911330758A CN111147050B CN 111147050 B CN111147050 B CN 111147050B CN 201911330758 A CN201911330758 A CN 201911330758A CN 111147050 B CN111147050 B CN 111147050B
- Authority
- CN
- China
- Prior art keywords
- resistor
- resistance
- output
- delay
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
Abstract
A CML transmitter resistant to single event reinforcement, comprising: the system comprises a digital three-mode processing module, a DR offset module, an SR offset module, a voting-delay-difference module, an output pull-up module and the like. The multimode backup mode is adopted to strengthen single-event resistance of the internal module, so that the reliability of space application can be ensured. In addition, the invention can improve the signal quality and ensure reliable data transmission.
Description
Technical Field
The invention relates to an anti-single particle reinforcement CML transmitter, and belongs to the technical field of integrated circuits.
Background
With the increase of the complexity of electronic systems, the data exchange amount between the systems is larger and larger, and higher requirements are put on interfaces between chips. The high-speed SerDes interface can realize high-speed communication between chips, so that the high-speed SerDes interface is widely applied.
The high-speed SerDes interface is divided into two components, a transmitter and a receiver, wherein the transmitter typically transmits data in the form of a CML, the basic structure of which is shown in fig. 1. The NMOS tube N110 and the NMOS tube N111 form a group of switches, and only one NMOS tube is in a conducting state at any time. In this way, the current of the current source C100 can only flow through the NMOS transistor N110 or the NMOS transistor N111, so that when the current is transmitted to the termination resistor through the transmission line, the directions of the currents are different, which represents different digital states ("0" or "1"), and signal transmission is realized. To determine the level of the output and improve signal integrity, two termination resistors, shown as resistor R120 and resistor R121, are typically added to the CML transmitter.
The traditional CML transmitter can reliably work in the ground environment, and the error rate is ensured to be in an acceptable range. However, in the field of aerospace application, the transient error rate is continuously increased due to the single event effect, and the error rate is not acceptable. The reinforcement technology is applied in the circuit design, and the single particle reinforcement resistant design is carried out at the cost of proper performance cost, so that the method is a necessary means for realizing high-reliability operation in a space radiation environment.
Disclosure of Invention
The technical solution of the invention is as follows: the method overcomes the defects of the prior art, provides an anti-single particle reinforcement CML transmitter, and is an implementation scheme of a high-speed SerDes transmitter in the field of aerospace application. The anti-single particle reinforcement design is carried out by adopting a multimode backup mode, so that the problem of single particle effect in space application can be relieved.
The technical scheme of the invention is as follows:
a single event resistant ruggedized CML transmitter, comprising: the system comprises a digital three-mode processing module, an SR bias module, a DR bias module, a voting-delay-differential driving module and an output pull-up module;
digital three-mode processing module: receiving an externally input data signal D, sampling the input data signal D under the control of a clock signal CLK, and generating three identical sets of output signals Q <1>, Q <2> and Q <3>; the digital three-mode processing module performs secondary sampling on the output signals Q <1>, Q <2> and Q <3>, generates three delayed groups of identical output signals QD <1>, QD <2> and QD <3>, and transmits the output signals Q <1>, Q <2>, Q <3>, QD <1>, QD <2> and QD <3> to the voting-delay-differential driving module for processing;
there are 10 identical voting-delay-differential driving modules, 6 of which are used to receive Q <1>, Q <2> and Q <3> signals, and the remaining 4 receive QD <1>, QD <2> and QD <3> signals; q <1>, Q <2>, Q <3> are data transmitted at the current time; QD <1>, QD <2>, QD <3> are data that have been transmitted at a previous time;
the output current polarity connection mode of the 4 voting-delay-differential driving modules receiving the QD <1>, the QD <2> and the QD <3> signals is opposite to that of the 6 voting-delay-differential driving modules receiving the Q <1>, the Q <2> and the Q <3> signals, so that when the Q <1>, the Q <2> and the Q <3> signals are identical to the QD <1>, the QD <2> and the QD <3> signals, a part of currents cancel each other, and the total output current is smaller; when the Q <1>, Q <2> and Q <3> signals are different from the QD <1>, QD <2> and QD <3> signals, the situation that the currents cancel each other does not exist, and the total output current is larger;
the digital three-mode processing module, the SR bias module, the DR bias module and the output pull-up module are respectively connected with 10 voting-delay-differential driving modules;
the voting-delay-differential driving module performs majority voting on the received signals Q <1>, Q <2> and Q <3> to generate an internal signal Q; then generates signals QD and QDN through LATCH, wherein QD is in phase with Q, and QDN is in phase with Q; finally, QD and QDN are used for controlling the output differential pair, so that tail current flows to VOP or VON to generate different output states;
the voting-delay-differential driving module increases delay in the process of generating QD and QDN, and the delay is controlled by bias voltage;
the SR bias module generates 10 different bias voltages, so that the voting-delay-differential driving module adds 10 different delays on the signal transmission path; when the output terminals VOP and VON change state, the output state thereof will change gradually with the states of the 10 voting-delay-differential driving modules.
A digital three-mode processing module comprising: d flip-flop D300, D flip-flop D301, D flip-flop D302, D flip-flop D303, D flip-flop D304, D flip-flop D305;
d flip-flop D300, D flip-flop D302, D flip-flop D304 are a group of three-mode redundant units, sample the input data signal D under the control of clock signal CLK, output is Q <1>, Q <2>, Q <3>, respectively; d flip-flop D301, D flip-flop D303, D flip-flop D305 resample Q <1>, Q <2>, Q <3>, respectively, outputting QD <1>, QD <2>, QD <3>.
The voting-delay-difference module comprises: and gate G400, and gate G401, and gate G402, or gate G403, not gate G404, PMOS transistor P410, PMOS transistor P411, PMOS transistor P412, PMOS transistor P413, NMOS transistor N414, NMOS transistor N415, not gate G420, not gate G421, not gate G422, not gate G423, NMOS transistor N430, NMOS transistor N431, NMOS transistor N432;
and gate G400, and gate G401, and gate G402, or gate G403 constitute a voting circuit that votes on three input signals A, B, C: when most of A, B, C is "1", the or gate G403 outputs "1"; when most of A, B, C is "0", the or gate G403 outputs "0";
the output end of the OR gate G403 is connected with the input end of the NOT gate G404 and the gates of the PMOS tube P410, the PMOS tube P411 and the NMOS tube N414, and the output end of the NOT gate G404 is connected with the gates of the PMOS tube P412, the PMOS tube P413 and the NMOS tube N415;
the PMOS tube P410, the PMOS tube P411 and the NMOS tube N414 form a delay control unit; the PMOS pipe P412, the PMOS pipe P413 and the NMOS pipe N415 form another delay control unit;
the SR bias voltage sr_b controls the driving strength of the PMOS transistors P411 and P413, thereby controlling the delay time: the higher the SR_B level is, the weaker the driving strength of the PMOS pipe P411 and the PMOS pipe P413 is, and the longer the delay time is; the lower the SR_B level is, the stronger the driving strength of the PMOS pipe P411 and the PMOS pipe P413 is, and the shorter the delay time is;
the NOT gate G420, the NOT gate G421, the NOT gate G422 and the NOT gate G423 form a Latch, and output data of the two delay control units are latched;
the NMOS tube N430, the NMOS tube N431 and the NMOS tube N432 form a differential driving unit.
The SR bias module comprises: resistance R500, resistance R501, resistance R510, resistance R511, resistance R520, resistance R521, resistance R522, resistance R523, resistance R524, resistance R525, resistance R526, resistance R527, resistance R528, resistance R529, resistance R530, resistance R531, resistance R532, resistance R533, resistance R534, resistance R535, resistance R536, resistance R537, resistance R538, resistance R539, resistance R540, resistance R541, resistance R542, resistance R543, resistance R544, resistance R545, resistance R546, resistance R547, resistance R548, resistance R549, resistance R550, resistance R551, resistance R552, resistance R553, resistance R554, resistance R555, resistance R556, resistance R557, resistance R558, resistance R559;
one end of the resistor R510 is connected with the power supply VDD, the other end of the resistor R510 is connected with one end of the resistor R529, and the other end of the resistor R529 is connected with one end of the resistor R549 and one end of the resistor R528; the other end of the resistor R528 is connected with one end of the resistor R548 and one end of the resistor R527; the other end of the resistor R527 is connected with one end of the resistor R547 and one end of the resistor R526; the other end of the resistor R526 is connected with one end of the resistor R546 and one end of the resistor R525; the other end of the resistor R525 is connected with one end of the resistor R545 and one end of the resistor R524; the other end of the resistor R524 is connected with one end of the resistor R544 and one end of the resistor R523; the other end of the resistor R523 is connected with one end of the resistor R543 and one end of the resistor R522; the other end of the resistor R522 is connected with one end of the resistor R542 and one end of the resistor R521; the other end of the resistor R521 is connected with one end of the resistor R541 and one end of the resistor R520; the other end of the resistor R520 is connected with one end of the resistor R540 and one end of the resistor R500; the other end of the resistor R500 is grounded;
one end of the resistor R511 is connected with an external power supply, the other end of the resistor R511 is connected with one end of the resistor R539, and the other end of the resistor R539 is connected with one end of the resistor R559 and one end of the resistor R538; the other end of the resistor R538 is connected with one end of the resistor R558 and one end of the resistor R537; the other end of the resistor R537 is connected with one end of the resistor R557 and one end of the resistor R536; the other end of the resistor R536 is connected with one end of the resistor R556 and one end of the resistor R535; the other end of the resistor R535 is connected with one end of the resistor R555 and one end of the resistor R534; the other end of the resistor R534 is connected with one end of the resistor R554 and one end of the resistor R533; the other end of the resistor R533 is connected with one end of the resistor R553 and one end of the resistor R532; the other end of the resistor R532 is connected with one end of the resistor R552 and one end of the resistor R531; the other end of the resistor R531 is connected with one end of the resistor R551 and one end of the resistor R530; the other end of the resistor R530 is connected with one end of the resistor R550 and one end of the resistor R501; the other end of the resistor R501 is grounded;
the other end of the resistor R549 is connected with the other end of the resistor R559, the other end of the resistor R548 is connected with the other end of the resistor R558, the other end of the resistor R547 is connected with the other end of the resistor R557, the other end of the resistor R546 is connected with the other end of the resistor R556, the other end of the resistor R545 is connected with the other end of the resistor R555, the other end of the resistor R543 is connected with the other end of the resistor R553, the other end of the resistor R542 is connected with the other end of the resistor R552, the other end of the resistor R541 is connected with the other end of the resistor R551, and the other end of the resistor R540 is connected with the other end of the resistor R550;
the other end of the resistor R549 is used as an output end to output bias voltage SR_B <9> to the corresponding voting-delay-difference module; the other end of the resistor R548 is used as an output end to output bias voltage SR_B <8> to the corresponding voting-delay-difference module; the other end of the resistor R547 is used as an output end to output bias voltage SR_B <7> to the corresponding voting-delay-difference module; the other end of the resistor R546 is used as an output end to output bias voltage SR_B <6> to the corresponding voting-delay-difference module; the other end of the resistor R545 is used as an output end to output bias voltage SR_B <5> to the corresponding voting-delay-difference module; the other end of the resistor R544 is used as an output end to output bias voltage SR_B4 to the corresponding voting-delay-difference module; the other end of the resistor R543 is used as an output end to output bias voltage SR_B3 to the corresponding voting-delay-difference module; the other end of the resistor R542 is used as an output end to output bias voltage SR_B2 to the corresponding voting-delay-difference module; the other end of the resistor R541 is used as an output end to output bias voltage SR_B1 to the corresponding voting-delay-difference module; the other end of the resistor R540 is used as an output end to output bias voltage SR_B <0> to the corresponding voting-delay-difference module;
bias voltage SR_B0 > less than bias voltage SR_B1 > less than bias voltage SR_B2 > less than bias voltage SR_B3 > less than bias voltage SR_B4 > less than bias voltage SR_B5 > less than bias voltage SR_B6 > less than bias voltage SR_B7 > less than bias voltage SR_B8 > less than bias voltage SR_B9 >.
Compared with the prior art, the invention has the beneficial effects that:
1) The CML transmitter provided by the invention considers the influence of the space irradiation effect on the working state of the circuit in the design, and performs the anti-single particle reinforcement design, so that the reliability of space application can be ensured.
2) The invention can control the SlewRate of CML transmitter, to reduce the design requirement of power supply, improve the signal quality and confirm the reliable data transmission.
Drawings
FIG. 1 is a schematic diagram of the working principle of CML;
FIG. 2 is a schematic diagram of the overall structure of the anti-single particle reinforced CML transmitter of the present invention;
FIG. 3 is a schematic diagram of a digital three-mode processing module according to the present invention;
FIG. 4 is a schematic diagram of a voting-delay-differential driving module structure according to the present invention;
FIG. 5 is a schematic diagram of an SR bias module structure in the disclosure;
FIG. 6 is a schematic diagram of a DR bias module according to the present invention;
FIG. 7 is a schematic diagram of an output pull-up module according to the present invention;
FIG. 8 is a schematic diagram of the output waveform when a single event occurs in the SR bias circuit of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
The single event resistant ruggedized CML transmitter is an output interface for transmitting high speed serial data. As shown in fig. 2, the CML transmitter of the present invention includes: the device comprises a digital three-mode processing module, an SR bias module, a DR bias module, a voting-delay-differential driving module and an output pull-up module. The CML transmitter of the present invention receives the input data signal D and the clock signal CLK and transmits the data to the output terminals VOP and VON.
Digital three-mode processing module: receiving an externally input data signal D, sampling the input data signal D under the control of a clock signal CLK, and generating three identical sets of output signals Q <1>, Q <2> and Q <3>; the digital three-mode processing module performs secondary sampling on the output signals Q <1>, Q <2> and Q <3>, generates three delayed groups of identical output signals QD <1>, QD <2> and QD <3>, and transmits the output signals Q <1>, Q <2>, Q <3>, QD <1>, QD <2> and QD <3> to the voting-delay-differential driving module for processing;
the invention has 10 identical voting-delay-differential driving modules, 6 of which are used for receiving Q <1>, Q <2> and Q <3> signals, and the other 4 of which are used for receiving QD <1>, QD <2> and QD <3> signals; q <1>, Q <2>, Q <3> are data transmitted at the current time; QD <1>, QD <2>, QD <3> are data that have been transmitted at a previous time;
the polarity connection mode of the output currents of the 4 voting-delay-differential driving modules receiving QD <1:3> is opposite to that of the output currents of the 6 voting-delay-differential driving modules receiving Q <1:3>, so that when Q <1:3> is identical to QD <1:3>, a part of currents cancel each other, and the total output current is smaller; when Q <1:3> is different from QD <1:3>, the condition that currents cancel each other does not exist, and the total output current is larger;
the digital three-mode processing module, the SR bias module, the DR bias module and the output pull-up module are respectively connected with 10 voting-delay-differential driving modules;
the voting-delay-differential driving module performs majority voting on the received signals Q <1>, Q <2> and Q <3> to generate an internal signal Q; then generates signals QD and QDN through LATCH, wherein QD is in phase with Q, and QDN is in phase with Q; finally, QD and QDN are used for controlling the output differential pair, so that tail current flows to VOP or VON to generate different output states;
the voting-delay-differential driving module increases delay in the process of generating QD and QDN, and the delay is controlled by bias voltage;
the SR bias module generates 10 different bias voltages, so that the voting-delay-differential driving module adds 10 different delays on the signal transmission path; when the states of the output terminals VOP and VON are changed, the output states of the output terminals VOP and VON are changed gradually along with the states of the 10 voting-delay-differential driving modules, so that the purpose of controlling the output slope (SlewRate) is achieved. In addition, 6 of the 10 voting-delay-differential driving modules receive Q <1> to Q <3> signals, and 4 receive QD <1> to QD <3> signals, which introduces an emphasis function at the output.
The voting-delay-difference module includes: and gate G400, and gate G401, and gate G402, or gate G403, not gate G404, PMOS transistor P410, PMOS transistor P411, PMOS transistor P412, PMOS transistor P413, NMOS transistor N414, NMOS transistor N415, not gate G420, not gate G421, not gate G422, not gate G423, NMOS transistor N430, NMOS transistor N431, NMOS transistor N432;
and gate G400, and gate G401, and gate G402, or gate G403 constitute a voting circuit that votes on three input signals A, B, C: when most of A, B, C is "1", the or gate G403 outputs "1"; when most of A, B, C is "0", the or gate G403 outputs "0";
the output end of the OR gate G403 is connected with the input end of the NOT gate G404 and the gates of the PMOS tube P410, the PMOS tube P411 and the NMOS tube N414, and the output end of the NOT gate G404 is connected with the gates of the PMOS tube P412, the PMOS tube P413 and the NMOS tube N415;
the PMOS tube P410, the PMOS tube P411 and the NMOS tube N414 form a delay control unit; the PMOS pipe P412, the PMOS pipe P413 and the NMOS pipe N415 form another delay control unit;
the SR bias voltage sr_b controls the driving strength of the PMOS transistors P411 and P413, thereby controlling the delay time: the higher the SR_B level is, the weaker the driving strength of the PMOS pipe P411 and the PMOS pipe P413 is, and the longer the delay time is; the lower the SR_B level is, the stronger the driving strength of the PMOS pipe P411 and the PMOS pipe P413 is, and the shorter the delay time is;
the NOT gate G420, the NOT gate G421, the NOT gate G422 and the NOT gate G423 form a Latch, and output data of the two delay control units are latched;
the NMOS tube N430, the NMOS tube N431 and the NMOS tube N432 form a differential driving unit.
The SR bias module comprises: resistance R500, resistance R501, resistance R510, resistance R511, resistance R520, resistance R521, resistance R522, resistance R523, resistance R524, resistance R525, resistance R526, resistance R527, resistance R528, resistance R529, resistance R530, resistance R531, resistance R532, resistance R533, resistance R534, resistance R535, resistance R536, resistance R537, resistance R538, resistance R539, resistance R540, resistance R541, resistance R542, resistance R543, resistance R544, resistance R545, resistance R546, resistance R547, resistance R548, resistance R549, resistance R550, resistance R551, resistance R552, resistance R553, resistance R554, resistance R555, resistance R556, resistance R557, resistance R558, resistance R559;
one end of the resistor R510 is connected with the power supply VDD, the other end of the resistor R510 is connected with one end of the resistor R529, and the other end of the resistor R529 is connected with one end of the resistor R549 and one end of the resistor R528; the other end of the resistor R528 is connected with one end of the resistor R548 and one end of the resistor R527; the other end of the resistor R527 is connected with one end of the resistor R547 and one end of the resistor R526; the other end of the resistor R526 is connected with one end of the resistor R546 and one end of the resistor R525; the other end of the resistor R525 is connected with one end of the resistor R545 and one end of the resistor R524; the other end of the resistor R524 is connected with one end of the resistor R544 and one end of the resistor R523; the other end of the resistor R523 is connected with one end of the resistor R543 and one end of the resistor R522; the other end of the resistor R522 is connected with one end of the resistor R542 and one end of the resistor R521; the other end of the resistor R521 is connected with one end of the resistor R541 and one end of the resistor R520; the other end of the resistor R520 is connected with one end of the resistor R540 and one end of the resistor R500; the other end of the resistor R500 is grounded;
one end of the resistor R511 is connected with an external power supply, the other end of the resistor R511 is connected with one end of the resistor R539, and the other end of the resistor R539 is connected with one end of the resistor R559 and one end of the resistor R538; the other end of the resistor R538 is connected with one end of the resistor R558 and one end of the resistor R537; the other end of the resistor R537 is connected with one end of the resistor R557 and one end of the resistor R536; the other end of the resistor R536 is connected with one end of the resistor R556 and one end of the resistor R535; the other end of the resistor R535 is connected with one end of the resistor R555 and one end of the resistor R534; the other end of the resistor R534 is connected with one end of the resistor R554 and one end of the resistor R533; the other end of the resistor R533 is connected with one end of the resistor R553 and one end of the resistor R532; the other end of the resistor R532 is connected with one end of the resistor R552 and one end of the resistor R531; the other end of the resistor R531 is connected with one end of the resistor R551 and one end of the resistor R530; the other end of the resistor R530 is connected with one end of the resistor R550 and one end of the resistor R501; the other end of the resistor R501 is grounded;
the other end of the resistor R549 is connected with the other end of the resistor R559, the other end of the resistor R548 is connected with the other end of the resistor R558, the other end of the resistor R547 is connected with the other end of the resistor R557, the other end of the resistor R546 is connected with the other end of the resistor R556, the other end of the resistor R545 is connected with the other end of the resistor R555, the other end of the resistor R543 is connected with the other end of the resistor R553, the other end of the resistor R542 is connected with the other end of the resistor R552, the other end of the resistor R541 is connected with the other end of the resistor R551, and the other end of the resistor R540 is connected with the other end of the resistor R550;
the other end of the resistor R549 is used as an output end to output bias voltage SR_B <9> to the corresponding voting-delay-difference module; the other end of the resistor R548 is used as an output end to output bias voltage SR_B <8> to the corresponding voting-delay-difference module; the other end of the resistor R547 is used as an output end to output bias voltage SR_B <7> to the corresponding voting-delay-difference module; the other end of the resistor R546 is used as an output end to output bias voltage SR_B <6> to the corresponding voting-delay-difference module; the other end of the resistor R545 is used as an output end to output bias voltage SR_B <5> to the corresponding voting-delay-difference module; the other end of the resistor R544 is used as an output end to output bias voltage SR_B4 to the corresponding voting-delay-difference module; the other end of the resistor R543 is used as an output end to output bias voltage SR_B3 to the corresponding voting-delay-difference module; the other end of the resistor R542 is used as an output end to output bias voltage SR_B2 to the corresponding voting-delay-difference module; the other end of the resistor R541 is used as an output end to output bias voltage SR_B1 to the corresponding voting-delay-difference module; the other end of the resistor R540 is used as an output end to output bias voltage SR_B <0> to the corresponding voting-delay-difference module;
bias voltage SR_B0 > less than bias voltage SR_B1 > less than bias voltage SR_B2 > less than bias voltage SR_B3 > less than bias voltage SR_B4 > less than bias voltage SR_B5 > less than bias voltage SR_B6 > less than bias voltage SR_B7 > less than bias voltage SR_B8 > less than bias voltage SR_B9 >.
The basic working process of the single particle reinforcement resistant CML transmitter is as follows: the digital three-mode processing module samples and caches data D to be transmitted and outputs two groups of digital signals of Q <1:3> and QD <1:3>. The voting-delay-differential driving module B230, the voting-delay-differential driving module B231, the voting-delay-differential driving module B232, the voting-delay-differential driving module B233 process the signal QD <1:3>, the voting-delay-differential driving module B234, the voting-delay-differential driving module B235, the voting-delay-differential driving module B236, the voting-delay-differential driving module B237, the voting-delay-differential driving module B238 and the voting-delay-differential driving module B239 process the signal QD <1:3>. The output stage of the voting-delay-differential driving module adopts a CML structure, the output signal of the CML structure is a pair of currents with opposite polarities, the polarities of the currents are determined by Q <1:3> or QD <1:3>, and the intensity of the currents is determined by the bias voltage DR_B output by the DR bias module B210. The simultaneous voting-delay-differential driving module inserts a controllable delay unit in the signal transmission path, and the delay is controlled by the bias voltage SR_B output by the SR bias circuit B220. By providing different bias voltages SR_B to different voting-delay-differential driving modules, different voting-delay-differential driving modules can have different delays, and finally, when the output current is added at the output end, the current intensity can be gradually changed within a controllable time length, so that the purpose of controlling the SlewRate is achieved.
The operation of each circuit module is described in detail below. For ease of understanding, the circuit blocks will be described in the order of the digital three-mode processing block, the voting-delay-differential driving block, the SR bias block, the DR bias block, and the output pull-up block. After describing each module, the influence on the CML transmitter of the invention when single event occurs to different modules is described.
The circuit structure of the digital three-mode processing module is shown in fig. 3. The method comprises the following steps: d flip-flop D300, D flip-flop D301, D flip-flop D302, D flip-flop D303, D flip-flop D304, D flip-flop D305. The working principle is as follows:
the D flip-flops D300, D flip-flop D302 and D flip-flop D304 are a group of triple-modular redundancy units, and sample the input data signal D under the control of the clock signal CLK, and the outputs are Q <1>, Q <2> and Q <3>, respectively. D flip-flop D301, D flip-flop D303, D flip-flop D305 resample Q <1>, Q <2>, Q <3>, respectively, outputting QD <1>, QD <2>, QD <3>.
In the anti-single-particle reinforcement CML transmitter, Q <1:3> is data transmitted at the current moment, QD <1:3> is data transmitted at the previous moment, and final output signals can be subjected to emphasis processing by combining the data transmitted at the current moment and the data transmitted at the previous moment. As shown in fig. 2, the anti-single-event-hardened CML transmitter of the present invention has a total of 10 voting-delay-differential driving modules, of which 4 modules receive QD <1:3>, and 6 modules receive Q <1:3>. The output current polarity connection mode of the 4 voting-delay-differential driving modules receiving QD <1:3> is opposite to that of the 6 voting-delay-differential driving modules receiving Q <1:3>, so that: when Q <1:3> is the same as QD <1:3>, a part of currents cancel each other out, and the total output current is smaller; when Q <1:3> is different from QD <1:3>, the condition that the currents cancel each other does not exist, and the total output current is larger. From the above analysis, when the transmitted data changes, Q <1:3> is different from QD <1:3>, and the output current is larger; when the transmitted data is unchanged, Q <1:3> is the same as QD <1:3>, and the output current is smaller. The current variation is the same as the de-emphasis output mode. As the A, B, C ends of the 8 voting-delay-differential driving modules are connected with Q <1:3>, the A, B, C ends of the 2 voting-delay-differential driving modules are connected with QD <1:3>, and the output swing is changed into full swing (8-2)/(8+2) under the serious condition, which is about 60%.
The circuit structure of the voting-delay-differential driving module is shown in fig. 4. The method comprises the following steps: and gate G400, and gate G401, and gate G402, or gate G403, not gate G404, PMOS transistor P410, PMOS transistor P411, PMOS transistor P412, PMOS transistor P413, NMOS transistor N414, NMOS transistor N415, not gate G420, not gate G421, not gate G422, not gate G423, NMOS transistor N430, NMOS transistor N431, NMOS transistor N432. The working principle is as follows:
and gate G400, and gate G401, and gate G402, or gate G403 constitute a voting circuit that votes on three input signals A, B, C: when most of A, B, C is "1", the or gate G403 outputs "1"; when most of A, B, C is "0", the or gate G403 outputs "0". Since the subsequent circuit processes the two-phase signal at the same time, the NOT gate G404 is added to facilitate subsequent circuit design.
The PMOS tube P410, the PMOS tube P411 and the NMOS tube N414 form a delay control unit; the PMOS transistor P412, the PMOS transistor P413, and the NMOS transistor N415 form another delay control unit. The two delay control units are identical, and delay is performed on the two-phase signals at the same time. The SR bias voltage sr_b can control the driving strength of the PMOS transistors P411 and P413, thereby controlling the delay time: the higher the SR_B level is, the weaker the driving strength of the PMOS pipe P411 and the PMOS pipe P413 is, and the longer the delay time is; the lower the SR_B level is, the stronger the driving strength of the PMOS pipes P411 and P413 is, and the shorter the delay time is.
The NOT gate G420, the NOT gate G421, the NOT gate G422 and the NOT gate G423 form a Latch to Latch the output data of the two delay control units. The latch can imitate the problem that two-phase signals generated by delay control are not overlapped (two signals are simultaneously high or simultaneously low), and on the other hand, the signal edge can be steeper.
The NMOS tube N430, the NMOS tube N431 and the NMOS tube N432 form a differential driving unit. NMOS transistor N430 performs the function of current source C100 of FIG. 1, and its current is controlled by DR bias voltage DR_B; the NMOS transistors N431 and N432 realize the functions of the NMOS transistors N110 and N111 in fig. 1, and are current switches.
The circuit structure of the SR bias module is shown in fig. 5. The method comprises the following steps: resistance R500, resistance R501, resistance R510, resistance R511, resistance R520, resistance R521, resistance R522, resistance R523, resistance R524, resistance R525, resistance R526, resistance R527, resistance R528, resistance R529, resistance R530, resistance R531, resistance R532, resistance R533, resistance R534, resistance R535, resistance R536, resistance R537, resistance R538, resistance R539, resistance R540, resistance R541, resistance R542, resistance R543, resistance R544, resistance R545, resistance R546, resistance R547, resistance R548, resistance R549, resistance R550, resistance R551, resistance R552, resistance R553, resistance R554, resistance R555, resistance R556, resistance R557, resistance R558, resistance R559.
The working principle is as follows:
the SR bias module is mainly composed of two resistor voltage-dividing chains, the circuit structures and parameters of the two resistor voltage-dividing chains are identical, and the output of the SR bias module is the average voltage value of the same node of the two resistor voltage-dividing chains. The first resistor voltage division chain consists of a resistor R500, a resistor R510, a resistor R520, a resistor R521, a resistor R522, a resistor R523, a resistor R524, a resistor R525, a resistor R526, a resistor R527, a resistor R528 and a resistor R529, and the outputs of the first resistor voltage division chain are respectively negative ends of the resistor R520, the resistor R521, the resistor R522, the resistor R523, the resistor R524, the resistor R525, the resistor R526, the resistor R527, the resistor R528 and the resistor R529; the second resistor divider chain is composed of a resistor R501, a resistor R511, a resistor R530, a resistor R531, a resistor R532, a resistor R533, a resistor R534, a resistor R535, a resistor R536, a resistor R537, a resistor R538 and a resistor R539, and the outputs are negative terminals of the resistor R530, the resistor R531, the resistor R532, the resistor R533, the resistor R534, the resistor R535, the resistor R536, the resistor R537, the resistor R538 and the resistor R539 respectively. Resistor R540 and resistor R550 achieve an average of the voltages at the negative terminal of resistor R520 and the negative terminal of resistor R530, producing an output voltage SR_B <0>; the resistor R541 and the resistor R551 realize the average of the voltage at the negative end of the resistor R521 and the voltage at the negative end of the resistor R531, and generate an output voltage SR_B <1>; by analogy, the final resistor R549 and resistor R559 achieve an average of the negative terminal of resistor R529 and the negative terminal voltage of resistor R539, resulting in an output voltage SR_B <9>. The structure of the resistor voltage division chain is known: SR_B <0> is less than SR_B <1> is less than … … and SR_B <8> is less than SR_B <9>.
The circuit structure of the DR bias module is shown in fig. 6. The method comprises the following steps: resistor R600, resistor R601, operational amplifier B610, PMOS device P620, NMOS device N621, NMOS device N622, resistor R623, PMOS device P630, NMOS device N631, resistor R640, capacitor C641.
The working principle is as follows:
resistor R600 and resistor R601 form a resistor divider that generates an internal bias voltage VBias that is used to determine the output common mode level of the anti-single event ruggedized CML transmitter of the present invention. The NMOS transistor N621 and the NMOS transistor N622 form a current mirror, so that the current in the resistor R623 is the same as the current in the PMOS transistor P620. The operational amplifier B610 adjusts the gate voltage of the PMOS transistor P620, thereby adjusting the current in the PMOS transistor P620, and adjusts the current in the resistor R623 through a current mirror composed of the NMOS transistor N621 and the NMOS transistor N622. The operational amplifier B610 continuously adjusts the gate voltage of the PMOS transistor P620 until the voltage at the negative terminal of the resistor R623 is the same as VBias, and the PMOS transistor P620. The current in the resistor R623 is (VDD-VBias)/R 623 =ibias. The PMOS transistor P630 has the same size as the PMOS transistor P620, so that the current flowing in the PMOS transistor P630 is also IBias. The NMOS tube N631 and the NMOS tube N430 in the voting-delay-differential driving check block form a current mirror to control the current in the differential driving circuit, and the size ratio of the NMOS tube N631 to the NMOS tube N430 is 10:1. the resistor R640 and the capacitor C641 form a low-pass filter to filter the disturbance on the gate voltage of the NMOS tube N631.
The circuit structure of the pull-up control module is shown in fig. 7. The method comprises the following steps: resistor R700 and resistor R701. The pull-up control module generates output voltage through two pull-up resistors, and the sizes of the two pull-up resistors are the same as the resistor R623 in the DR bias module.
The following focuses on the overall impact of each module when a single event occurs.
a) And a digital three-mode processing module. Because the three-mode processing is performed in the module, and the voting-delay-difference driving module performs majority voting on the output of the digital three-mode processing module, any single event occurring in the digital three-mode processing module cannot affect the final output VOP/VON.
b) And a DR bias module. Because the DR bias module does not have any data storage device inside, the influence of the single event on the DR bias module is a transient event. The low-pass filter at the output end of the DR offset module can process any level fluctuation in the DR offset module, and the output cannot be affected. The capacitor C641 in the DR bias circuit is relatively large, and the influence of a single event on the capacitor C is negligible.
c) And an SR bias module. The SR bias module is a dual-mode backup, and the output voltage of the SR bias module is less influenced by a single event. Furthermore, the single output of the SR biasing module controls the delay of only 1 cell of the 10 voting-delay-differential driving modules with limited impact on the final output VOP/VON, as shown in fig. 8. In the figure, the solid line is the VOP/VON waveform without single event, and the dotted line is the VOP/VON waveform when the SR bias module is affected by the single event, and the waveform is expressed as the early and late arrival of a certain voltage step. To simplify the waveforms, there are only 4 voltage steps in the figure. The anti-single event reinforcement CML driver has 10 voting-delay-differential driving modules, and 10 voltage steps.
d) And a voting-delay-differential driving module. The voting-delay-differential driving module is internally provided with no data storage device, and the influence of a single event on the DR biasing module is a transient event. Since the final output voltage state is commonly determined by 10 voting-delay-differential driving modules, the effect of transient changes of a single voting-delay-differential driving module on the final output voltage is extremely limited. If a single event occurs during the settling of the electrical increment, a jitter occurs in the output settling level, which is 20% of the full amplitude and 33% of the emphasis amplitude. If a single event occurs during a voltage change, the output behaves similarly to when the SR bias module occurs a single event.
e) And outputting a pull-up module. The output pull-up module is provided with two resistors, and is not affected by a single event.
What is not described in detail in the present specification is a known technology to those skilled in the art.
Claims (4)
1. A CML transmitter resistant to single event reinforcement, comprising: the system comprises a digital three-mode processing module, an SR bias module, a DR bias module, a voting-delay-differential driving module and an output pull-up module;
digital three-mode processing module: receiving an externally input data signal D, sampling the input data signal D under the control of a clock signal CLK, and generating three identical sets of output signals Q <1>, Q <2> and Q <3>; the digital three-mode processing module performs secondary sampling on the output signals Q <1>, Q <2> and Q <3>, generates three delayed groups of identical output signals QD <1>, QD <2> and QD <3>, and transmits the output signals Q <1>, Q <2>, Q <3>, QD <1>, QD <2> and QD <3> to the voting-delay-differential driving module for processing;
there are 10 identical voting-delay-differential driving modules, 6 of which are used to receive Q <1>, Q <2> and Q <3> signals, and the remaining 4 receive QD <1>, QD <2> and QD <3> signals; q <1>, Q <2>, Q <3> are data transmitted at the current time; QD <1>, QD <2>, QD <3> are data that have been transmitted at a previous time;
the output current polarity connection mode of the 4 voting-delay-differential driving modules receiving the QD <1>, the QD <2> and the QD <3> signals is opposite to that of the 6 voting-delay-differential driving modules receiving the Q <1>, the Q <2> and the Q <3> signals, so that when the Q <1>, the Q <2> and the Q <3> signals are identical to the QD <1>, the QD <2> and the QD <3> signals, a part of currents cancel each other, and the total output current is smaller; when the Q <1>, Q <2> and Q <3> signals are different from the QD <1>, QD <2> and QD <3> signals, the situation that the currents cancel each other does not exist, and the total output current is larger;
the digital three-mode processing module, the SR bias module, the DR bias module and the output pull-up module are respectively connected with 10 voting-delay-differential driving modules;
the voting-delay-differential driving module performs majority voting on the received signals Q <1>, Q <2> and Q <3> to generate an internal signal Q; then generates signals QD and QDN through LATCH, wherein QD is in phase with Q, and QDN is in phase with Q; finally, QD and QDN are used for controlling the output differential pair, so that tail current flows to VOP or VON to generate different output states;
the voting-delay-differential driving module increases delay in the process of generating QD and QDN, and the delay is controlled by bias voltage;
the SR bias module generates 10 different bias voltages, so that the voting-delay-differential driving module adds 10 different delays on the signal transmission path; when the output terminals VOP and VON change state, the output state thereof will change gradually with the states of the 10 voting-delay-differential driving modules.
2. The CML transmitter of claim 1 wherein the digital three-mode processing module comprises: d flip-flop D300, D flip-flop D301, D flip-flop D302, D flip-flop D303, D flip-flop D304, D flip-flop D305;
d flip-flop D300, D flip-flop D302, D flip-flop D304 are a group of three-mode redundant units, sample the input data signal D under the control of clock signal CLK, output is Q <1>, Q <2>, Q <3>, respectively; d flip-flop D301, D flip-flop D303, D flip-flop D305 resample Q <1>, Q <2>, Q <3>, respectively, outputting QD <1>, QD <2>, QD <3>.
3. The CML transmitter of claim 1 wherein the voting-delay-difference module comprises: and gate G400, and gate G401, and gate G402, or gate G403, not gate G404, PMOS transistor P410, PMOS transistor P411, PMOS transistor P412, PMOS transistor P413, NMOS transistor N414, NMOS transistor N415, not gate G420, not gate G421, not gate G422, not gate G423, NMOS transistor N430, NMOS transistor N431, NMOS transistor N432;
and gate G400, and gate G401, and gate G402, or gate G403 constitute a voting circuit that votes on three input signals A, B, C: when most of A, B, C is "1", the or gate G403 outputs "1"; when most of A, B, C is "0", the or gate G403 outputs "0";
the output end of the OR gate G403 is connected with the input end of the NOT gate G404 and the gates of the PMOS tube P410, the PMOS tube P411 and the NMOS tube N414, and the output end of the NOT gate G404 is connected with the gates of the PMOS tube P412, the PMOS tube P413 and the NMOS tube N415;
the PMOS tube P410, the PMOS tube P411 and the NMOS tube N414 form a delay control unit; the PMOS pipe P412, the PMOS pipe P413 and the NMOS pipe N415 form another delay control unit;
the SR bias voltage sr_b controls the driving strength of the PMOS transistors P411 and P413, thereby controlling the delay time: the higher the SR_B level is, the weaker the driving strength of the PMOS pipe P411 and the PMOS pipe P413 is, and the longer the delay time is; the lower the SR_B level is, the stronger the driving strength of the PMOS pipe P411 and the PMOS pipe P413 is, and the shorter the delay time is;
the NOT gate G420, the NOT gate G421, the NOT gate G422 and the NOT gate G423 form a Latch, and output data of the two delay control units are latched;
the NMOS tube N430, the NMOS tube N431 and the NMOS tube N432 form a differential driving unit.
4. A CML transmitter as claimed in any one of claims 1 to 3 wherein the SR biasing module comprises: resistance R500, resistance R501, resistance R510, resistance R511, resistance R520, resistance R521, resistance R522, resistance R523, resistance R524, resistance R525, resistance R526, resistance R527, resistance R528, resistance R529, resistance R530, resistance R531, resistance R532, resistance R533, resistance R534, resistance R535, resistance R536, resistance R537, resistance R538, resistance R539, resistance R540, resistance R541, resistance R542, resistance R543, resistance R544, resistance R545, resistance R546, resistance R547, resistance R548, resistance R549, resistance R550, resistance R551, resistance R552, resistance R553, resistance R554, resistance R555, resistance R556, resistance R557, resistance R558, resistance R559;
one end of the resistor R510 is connected with the power supply VDD, the other end of the resistor R510 is connected with one end of the resistor R529, and the other end of the resistor R529 is connected with one end of the resistor R549 and one end of the resistor R528; the other end of the resistor R528 is connected with one end of the resistor R548 and one end of the resistor R527; the other end of the resistor R527 is connected with one end of the resistor R547 and one end of the resistor R526; the other end of the resistor R526 is connected with one end of the resistor R546 and one end of the resistor R525; the other end of the resistor R525 is connected with one end of the resistor R545 and one end of the resistor R524; the other end of the resistor R524 is connected with one end of the resistor R544 and one end of the resistor R523; the other end of the resistor R523 is connected with one end of the resistor R543 and one end of the resistor R522; the other end of the resistor R522 is connected with one end of the resistor R542 and one end of the resistor R521; the other end of the resistor R521 is connected with one end of the resistor R541 and one end of the resistor R520; the other end of the resistor R520 is connected with one end of the resistor R540 and one end of the resistor R500; the other end of the resistor R500 is grounded;
one end of the resistor R511 is connected with an external power supply, the other end of the resistor R511 is connected with one end of the resistor R539, and the other end of the resistor R539 is connected with one end of the resistor R559 and one end of the resistor R538; the other end of the resistor R538 is connected with one end of the resistor R558 and one end of the resistor R537; the other end of the resistor R537 is connected with one end of the resistor R557 and one end of the resistor R536; the other end of the resistor R536 is connected with one end of the resistor R556 and one end of the resistor R535; the other end of the resistor R535 is connected with one end of the resistor R555 and one end of the resistor R534; the other end of the resistor R534 is connected with one end of the resistor R554 and one end of the resistor R533; the other end of the resistor R533 is connected with one end of the resistor R553 and one end of the resistor R532; the other end of the resistor R532 is connected with one end of the resistor R552 and one end of the resistor R531; the other end of the resistor R531 is connected with one end of the resistor R551 and one end of the resistor R530; the other end of the resistor R530 is connected with one end of the resistor R550 and one end of the resistor R501; the other end of the resistor R501 is grounded;
the other end of the resistor R549 is connected with the other end of the resistor R559, the other end of the resistor R548 is connected with the other end of the resistor R558, the other end of the resistor R547 is connected with the other end of the resistor R557, the other end of the resistor R546 is connected with the other end of the resistor R556, the other end of the resistor R545 is connected with the other end of the resistor R555, the other end of the resistor R543 is connected with the other end of the resistor R553, the other end of the resistor R542 is connected with the other end of the resistor R552, the other end of the resistor R541 is connected with the other end of the resistor R551, and the other end of the resistor R540 is connected with the other end of the resistor R550;
the other end of the resistor R549 is used as an output end to output bias voltage SR_B <9> to the corresponding voting-delay-difference module; the other end of the resistor R548 is used as an output end to output bias voltage SR_B <8> to the corresponding voting-delay-difference module; the other end of the resistor R547 is used as an output end to output bias voltage SR_B <7> to the corresponding voting-delay-difference module; the other end of the resistor R546 is used as an output end to output bias voltage SR_B <6> to the corresponding voting-delay-difference module; the other end of the resistor R545 is used as an output end to output bias voltage SR_B <5> to the corresponding voting-delay-difference module; the other end of the resistor R544 is used as an output end to output bias voltage SR_B4 to the corresponding voting-delay-difference module; the other end of the resistor R543 is used as an output end to output bias voltage SR_B3 to the corresponding voting-delay-difference module; the other end of the resistor R542 is used as an output end to output bias voltage SR_B2 to the corresponding voting-delay-difference module; the other end of the resistor R541 is used as an output end to output bias voltage SR_B1 to the corresponding voting-delay-difference module; the other end of the resistor R540 is used as an output end to output bias voltage SR_B <0> to the corresponding voting-delay-difference module;
bias voltage SR_B0 > less than bias voltage SR_B1 > less than bias voltage SR_B2 > less than bias voltage SR_B3 > less than bias voltage SR_B4 > less than bias voltage SR_B5 > less than bias voltage SR_B6 > less than bias voltage SR_B7 > less than bias voltage SR_B8 > less than bias voltage SR_B9 >.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911330758.0A CN111147050B (en) | 2019-12-20 | 2019-12-20 | Anti-single-particle reinforcement CML transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911330758.0A CN111147050B (en) | 2019-12-20 | 2019-12-20 | Anti-single-particle reinforcement CML transmitter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111147050A CN111147050A (en) | 2020-05-12 |
| CN111147050B true CN111147050B (en) | 2023-07-04 |
Family
ID=70519273
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911330758.0A Active CN111147050B (en) | 2019-12-20 | 2019-12-20 | Anti-single-particle reinforcement CML transmitter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111147050B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1427241A (en) * | 2001-07-03 | 2003-07-02 | 株式会社三丰 | Treating system and method for low voltage high-precision differential signal of measurer |
| CN105207660A (en) * | 2015-09-11 | 2015-12-30 | 中国科学院微电子研究所 | Differential-mode feedback circuit |
| CN105577164A (en) * | 2016-01-20 | 2016-05-11 | 北京时代民芯科技有限公司 | Single event transient resistant differential driver applicable to FPGA for space flight |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8836394B2 (en) * | 2012-03-26 | 2014-09-16 | Rambus Inc. | Method and apparatus for source-synchronous signaling |
| CN102624374B (en) * | 2012-04-18 | 2014-12-03 | 烽火通信科技股份有限公司 | Current-mode logic (CML) level driving circuit with pre-emphasis function |
| CN105634454B (en) * | 2016-02-26 | 2018-07-06 | 北京时代民芯科技有限公司 | A kind of electrification reset circuit reinforced suitable for aerospace with the single-particle of SRAM type FPGA |
-
2019
- 2019-12-20 CN CN201911330758.0A patent/CN111147050B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1427241A (en) * | 2001-07-03 | 2003-07-02 | 株式会社三丰 | Treating system and method for low voltage high-precision differential signal of measurer |
| CN105207660A (en) * | 2015-09-11 | 2015-12-30 | 中国科学院微电子研究所 | Differential-mode feedback circuit |
| CN105577164A (en) * | 2016-01-20 | 2016-05-11 | 北京时代民芯科技有限公司 | Single event transient resistant differential driver applicable to FPGA for space flight |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111147050A (en) | 2020-05-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7728620B2 (en) | System including preemphasis driver circuit and method | |
| US5359235A (en) | Bus termination resistance linearity circuit | |
| JP5313418B2 (en) | On-chip termination | |
| US5687330A (en) | Semiconductor process, power supply and temperature compensated system bus integrated interface architecture with precision receiver | |
| US6980021B1 (en) | Output buffer with time varying source impedance for driving capacitively-terminated transmission lines | |
| US5479123A (en) | Externally programmable integrated bus terminator for optimizing system bus performance | |
| US6275077B1 (en) | Method and apparatus for programmable adjustment of bus driver propagation times | |
| DE69936097T2 (en) | HIGH-SPEED SIGNALING FOR INTERFACE FORMATION OF VLSI CMOS CIRCUIT ARRANGEMENTS | |
| US20080136443A1 (en) | Input Termination For Delay Locked Loop Feedback With Impedance Matching | |
| Gangasani et al. | A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology | |
| WO2002039685A2 (en) | Low-voltage differential receiver/transmitter and calibration method thereof | |
| US5657456A (en) | Semiconductor process power supply voltage and temperature compensated integrated system bus driver rise and fall time | |
| US6452433B1 (en) | High phase margin low power flip-flop | |
| US7924056B2 (en) | Low voltage differential signalling driver | |
| KR20140053241A (en) | Apparatuses and methods of communicating differential serial signals including charge injection | |
| JP2007505577A (en) | Tx line driver with common mode idle state and selectable slew rate | |
| US5361042A (en) | Compensated offset voltage, low gain, high bandwidth, full swing, wide common mode range, CMOS differential voltage amplifier | |
| US7352755B2 (en) | Network interface card (NIC) with phase lock rise time control generating circuit | |
| US6249164B1 (en) | Delay circuit arrangement for use in a DAC/driver waveform generator with phase lock rise time control | |
| US6535945B1 (en) | Method and apparatus for programmable adjustment of computer system bus parameters | |
| US5634014A (en) | Semiconductor process, power supply voltage and temperature compensated integrated system bus termination | |
| US6657460B2 (en) | Spatially filtered data bus drivers and receivers and method of operating same | |
| US20050285648A1 (en) | Closed-loop independent DLL-controlled rise/fall time control circuit | |
| CN111147050B (en) | Anti-single-particle reinforcement CML transmitter | |
| EP1190420B1 (en) | Method and apparatus for testing an impedance-controlled input/output (i/o) buffer in a highly efficient manner |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |