CN111146106A - Method for rapidly screening failure risk of chip - Google Patents
Method for rapidly screening failure risk of chip Download PDFInfo
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- CN111146106A CN111146106A CN201911396641.2A CN201911396641A CN111146106A CN 111146106 A CN111146106 A CN 111146106A CN 201911396641 A CN201911396641 A CN 201911396641A CN 111146106 A CN111146106 A CN 111146106A
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000012216 screening Methods 0.000 title claims abstract description 12
- 230000002093 peripheral effect Effects 0.000 claims abstract description 4
- 238000012360 testing method Methods 0.000 claims description 14
- 238000004806 packaging method and process Methods 0.000 claims description 7
- 235000012431 wafers Nutrition 0.000 description 12
- 239000013078 crystal Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention discloses a method for rapidly screening failure risks of chips, which comprises the steps of calculating failure rates of chips around a good product and judging, wherein the original good product with the failure rate of more than 87.5 percent of the peripheral chips is judged to be a bad product, 8 chips are arranged around one good product, wherein 7 or 8 failed products are tested to be the bad product, the middle good product is judged to be the bad product, 7 chips are arranged around one good product, and 7 failed products are arranged around the periphery of the middle good product, and the middle good product is judged to be the bad product; the method for rapidly screening the failure risk of the chip provided by the invention can remove the chip with the potential risk and ensure the product quality.
Description
Technical Field
The invention relates to the technical field of wafer testing, in particular to a method for rapidly screening failure risks of a chip.
Background
After the wafer is tested, each chip can be divided into a good product and a bad product, the bad products are marked on a wafer real object in the traditional method to be divided or generated into one, and a test result graph is directly produced in the next step for cutting and packaging, so that the chips with potential risks cannot be judged. As integrated circuits become larger and more complex, good chips under certain requirements are at risk of potential failure.
Specifically, the first prior art: the scheme has low efficiency and high risk, and can only manually compare test results to print ink dots on the real object, so that error printing is possible and the risk of pollution is also possible on the wafer. The second prior art is: according to the scheme, risk chips are manually removed according to the test result graph, after the inkless map is generated, the encapsulation map is manually updated according to the test result graph, the efficiency is low, and the potential risk chips cannot be completely eliminated.
The invention provides a method for rapidly screening failure risks of chips, and aims to save packaging cost, improve chip quality and prevent chips with potential defects from entering a packaging stage.
Disclosure of Invention
The technical scheme adopted by the invention for solving the technical problems is to provide a method for rapidly screening failure risks of chips, and the technical scheme is to provide an algorithm for eliminating potential risk chips, reduce abnormal wafers to a minimum range and improve the production efficiency.
The specific technical scheme is as follows:
the first scheme is as follows: calculating the failure rate of chips around a good product and judging the failure rate of the chips around the good product, wherein the failure rate of the chips around the good product is more than 87.5 percent, the middle good product is judged to be a bad product, 8 chips are arranged around one good product, the failure rate of 7 or 8 chips is tested to be a bad product, the good product in the middle is judged to be a bad product, 7 chips are arranged around one good product, the good product in the middle is judged to be a bad product, 6 chips are arranged around one good product, the failure rate of 6 chips is judged to be around the good product, the good product in the middle is judged to be a bad product, 5 chips are arranged around one good product, the failure rate of 5 chips are arranged around the good product, the good product in the middle is judged to be a bad product, 4 chips are arranged around one good chip, 4 chips are arranged around the good product, the good product in the middle is judged to be a bad product, 3 chips are arranged around one good chip, the good chip; the chips which are not tested into good products after the wafer test is finished are free of problems, and in order to ensure that the functions of the chips are continuous and stable, the good products surrounded by the bad products have potential risks, and are removed before packaging, so that the product quality is ensured.
Scheme II: scoring according to the scores of the 4 neighborhoods and the 8 neighborhoods, judging that the score is greater than or equal to 8, the die is dropped, and the 8 surrounding fields are all tested die to participate in the operation, as shown in FIG. 2; and (3) dropping a circle of peripheral points of more than or equal to 20 continuous failures in the 8-neighborhood, wherein X is the original failed chip, and 0 is a good product to be dropped, as shown in figure 3.
Compared with the prior art, the invention has the following beneficial effects: according to the invention, the chips with potential risks are removed through an algorithm, so that the product quality is ensured.
Drawings
FIG. 1 is a schematic drawing of a scoring example.
Fig. 2-3 are schematic diagrams of embodiment 2.
In the figure:
g: and (4) good product B: and (3) bad product T: test judgment chip
Detailed Description
Wafer: a silicon wafer for use in the fabrication of silicon semiconductor integrated circuits has a circular shape.
Testing a wafer: and each crystal grain on the wafer is subjected to needle testing, a probe card is arranged on the detection head to be contacted with the contact points on the crystal grains, the electrical characteristics of the crystal grains are tested, qualified and unqualified crystal grains are distinguished, and the cost of the next step is saved.
And generating a graph for packaging according to the wafer test result by using the Inkless map.
The test machine comprises: and the equipment automatically detects the quality of the chip.
The technical scheme adopted by the invention for solving the technical problems is to provide a method for rapidly screening the failure risk of a chip.
Example 1: calculating the failure rate of chips around a good product and judging the failure rate of the chips around the good product, wherein the failure rate of the chips around the good product is more than 87.5 percent, the middle good product is judged to be a bad product, 8 chips are arranged around one good product, the failure rate of 7 or 8 chips is tested to be a bad product, the good product in the middle is judged to be a bad product, 7 chips are arranged around one good product, the good product in the middle is judged to be a bad product, 6 chips are arranged around one good product, the failure rate of 6 chips is judged to be around the good product, the good product in the middle is judged to be a bad product, 5 chips are arranged around one good product, the failure rate of 5 chips are arranged around the good product, the good product in the middle is judged to be a bad product, 4 chips are arranged around one good chip, 4 chips are arranged around the good product, the good product in the middle is judged to be a bad product, 3 chips are arranged around one good chip, the good chip; the chips which are not tested into good products after the wafer test is finished are free of problems, and in order to ensure that the functions of the chips are continuous and stable, the good products surrounded by the bad products have potential risks, and are removed before packaging, so that the product quality is ensured.
Example 2: scoring according to the scores of the 4 neighborhoods and the 8 neighborhoods, judging that the score is greater than or equal to 8, the die is dropped, and the 8 surrounding fields are all tested die to participate in the operation, as shown in FIG. 2; and (3) dropping a circle of peripheral points of more than or equal to 20 continuous failures in the 8-neighborhood, wherein X is the original failed chip, and 0 is a good product to be dropped, as shown in figure 3.
Although the present invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (4)
1. A method for rapidly screening failure risks of chips is characterized in that: and calculating the failure rate of the chips around the good product and judging the original good product with the failure rate of the chips around being more than 87.5 percent as a bad product.
2. The method for rapidly screening the risk of chip failure according to claim 1, wherein: there are 8 chips around a good article, wherein fail 7 or 8 tests are bad articles, judge that good article in the middle is bad article, there are 7 chips around a good article, wherein fail 7 around, judge that good article in the middle is bad article, there are 6 chips around a good article, fail 6 around, judge that good article in the middle is bad article, there are 5 chips around a good article chip, there are 5 failures around, judge that good article in the middle is bad article, there are 4 chips around a good chip, 4 failures around, judge that good article in the middle is bad article, there are 3 chips around a good chip, 3 failures around, judge that good article in the middle is bad article.
3. The method for rapidly screening the risk of chip failure according to claim 1, wherein: scoring according to the scores of the 4 neighborhoods and the 8 neighborhoods, judging that the score is greater than or equal to 8, the die is dropped, and the 8 surrounding fields are all tested die to participate in the operation, as shown in FIG. 2; and (3) dropping a circle of peripheral points of more than or equal to 20 continuous failures in the 8-neighborhood, wherein X is the original failed chip, and 0 is a good product to be dropped.
4. The method for rapid screening of risk of chip failure according to any of claims 1 to 3, wherein: after the wafer test is finished, the wafer is removed before packaging, and the product quality is ensured.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911396641.2A CN111146106A (en) | 2019-12-30 | 2019-12-30 | Method for rapidly screening failure risk of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911396641.2A CN111146106A (en) | 2019-12-30 | 2019-12-30 | Method for rapidly screening failure risk of chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111146106A true CN111146106A (en) | 2020-05-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911396641.2A Pending CN111146106A (en) | 2019-12-30 | 2019-12-30 | Method for rapidly screening failure risk of chip |
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| Country | Link |
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| CN (1) | CN111146106A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111554598A (en) * | 2020-05-22 | 2020-08-18 | 深圳市耀芯微电子有限公司 | Portable chip removing device capable of being screened |
| CN113130342A (en) * | 2021-04-15 | 2021-07-16 | 筏渡(上海)科技有限公司 | Method and device for marking wafer low-reliability failed tube core |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101290901A (en) * | 2007-04-17 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Wafer quality analysis method and device |
| CN103811298A (en) * | 2012-11-15 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for test alignment chip |
| CN105095618A (en) * | 2014-05-07 | 2015-11-25 | 华为技术有限公司 | Chip screening method and apparatus |
| CN109389598A (en) * | 2018-10-25 | 2019-02-26 | 上海哥瑞利软件有限公司 | A kind of continuous chip failing quantity statistics algorithm of efficient wafer |
-
2019
- 2019-12-30 CN CN201911396641.2A patent/CN111146106A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101290901A (en) * | 2007-04-17 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Wafer quality analysis method and device |
| CN103811298A (en) * | 2012-11-15 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for test alignment chip |
| CN105095618A (en) * | 2014-05-07 | 2015-11-25 | 华为技术有限公司 | Chip screening method and apparatus |
| CN109389598A (en) * | 2018-10-25 | 2019-02-26 | 上海哥瑞利软件有限公司 | A kind of continuous chip failing quantity statistics algorithm of efficient wafer |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111554598A (en) * | 2020-05-22 | 2020-08-18 | 深圳市耀芯微电子有限公司 | Portable chip removing device capable of being screened |
| CN111554598B (en) * | 2020-05-22 | 2023-01-20 | 深圳市耀芯微电子有限公司 | Portable chip removing device capable of being screened |
| CN113130342A (en) * | 2021-04-15 | 2021-07-16 | 筏渡(上海)科技有限公司 | Method and device for marking wafer low-reliability failed tube core |
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Application publication date: 20200512 |
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