CN111143274B

CN111143274B - Hierarchical structure optimization method, device and system with logic comprehensive result as guide

Info

Publication number: CN111143274B
Application number: CN201911105850.7A
Authority: CN
Inventors: 刘奎; 王宁; 王维; 宋宁; ***
Original assignee: Gowin Semiconductor Corp
Current assignee: Gowin Semiconductor Corp
Priority date: 2019-11-13
Filing date: 2019-11-13
Publication date: 2022-07-12
Anticipated expiration: 2039-11-13
Also published as: CN111143274A

Abstract

The invention discloses a hierarchical structure optimization method, a device and a system which take a logic comprehensive result as a guide, wherein the method comprises the following steps: the front-end logic synthesis device generates a synthesized netlist; the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device and judges whether the hierarchical structure of the read synthesized netlist needs to be optimized; if yes, generating a hierarchical structure optimization instruction and feeding the hierarchical structure optimization instruction back to the front-end logic comprehensive device; when the hierarchical structure optimization instruction is received, the front-end logic synthesis device executes optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction so as to generate a new synthesized netlist. Therefore, the hierarchical structure optimization method can realize the optimization of the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction fed back by the back-end processing device, improve the quality of front-end logic synthesis and the matching degree of the hierarchical structure in the synthesized netlist generated by the front-end logic synthesis and the actual requirement of the back end, and further facilitate the improvement of the design time sequence and the reduction of the power consumption.

Description

Hierarchical structure optimization method, device and system with logic comprehensive result as guide

Technical Field

The invention relates to the technical field of FPGA (field programmable gate array), in particular to a hierarchical structure optimization method, a device and a system which take a logic comprehensive result as a guide.

Background

The Design process of an FPGA (Field-Programmable Gate Array) is a process of developing an FPGA chip by using EDA (electronic Design Automation) development software and a programming tool. The development process of the EDA development software mainly includes a front-end logic synthesis process and a back-end layout and wiring, timing analysis, power consumption analysis and other processes, wherein the front-end logic synthesis process is used for converting user designs (such as register transmission level description of a digital circuit) into a device netlist and optimizing the device netlist, the back-end places the device netlist generated by the front-end on a specific position of an FPGA chip and winds according to a mapping relation between devices, and finally outputs a layout and wiring result, and the quality of the layout and wiring result directly influences the height of the back-end timing and the use of chip resources.

Currently, based on factors such as design orderliness and maintainability, a user usually distinguishes and organizes a user design by modules, which leads to a complex and variable hierarchical structure of the user design, but provides a better analysis basis for front-end logic synthesis and back-end layout and wiring, wherein the front-end logic synthesis can perform logic reasoning, logic optimization, technical mapping and the like according to the hierarchical structure of the user design.

However, practice finds that when a synthesis tool needs to synthesize across modules, a newly generated device changes a hierarchical structure of a user design, each stage of synthesis may involve use and modification of the hierarchical structure of the user design, and it is difficult to ensure that each modification of the hierarchical structure conforms to the user design itself, each modification of the hierarchical structure of the user design affects subsequent logic synthesis, layout and routing, and the like, so that the problem that the hierarchical structure of a synthesized netlist is not matched with the requirement of a back-end algorithm is caused, and further the problems that the layout and routing result of a back-end is unreasonable, the design timing is difficult to improve, the power consumption is difficult to reduce, and the like are caused. Therefore, how to improve the matching degree of the hierarchical structure of the synthesized netlist and the requirements of back-end layout and wiring is very important.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a hierarchical structure optimization method, device and system using a logic synthesis result as a guide, which can optimize the hierarchical structure of a synthesized netlist using the logic synthesis result as the guide, and improve the matching degree of the hierarchical structure of the synthesized netlist and the rear-end requirement.

In order to solve the above technical problem, a first aspect of the embodiments of the present invention discloses a hierarchical structure optimization method using a logic synthesis result as a guide, where the method includes:

the front-end logic synthesis device generates a synthesized netlist;

the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device and judges whether the hierarchical structure of the synthesized netlist needs to be optimized; when the hierarchical structure of the synthesized netlist needs to be optimized, generating a hierarchical structure optimization instruction, and feeding the hierarchical structure optimization instruction back to the front-end logic synthesis device;

when the hierarchical structure optimization instruction sent by the back-end processing device is received, the front-end logic synthesis device executes optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate a new synthesized netlist;

wherein the synthesized netlist generated by the front-end logic synthesis device is used for providing to the back-end processing device.

As an optional implementation manner, in the first aspect of the embodiment of the present invention, after the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device, the method further includes:

the back-end processing device executes at least one operation in the operation set on the synthesized netlist to obtain an operation result matched with the executed operation, and triggers and executes the operation for judging whether the hierarchical structure of the synthesized netlist needs to be optimized; wherein the operation set comprises one or more combinations of a layout and routing operation, a timing analysis operation, a hierarchical relationship complexity analysis operation, a critical path analysis operation, a power consumption analysis operation and a grid surface integral analysis operation;

and the back-end processing device judges whether the hierarchical structure of the synthesized netlist needs to be optimized, and the method comprises the following steps:

and the back-end processing device judges whether the hierarchical structure of the synthesized netlist needs to be optimized or not according to the operation result.

As an optional implementation manner, in the first aspect of the embodiment of the present invention, the determining, by the back-end processing device, whether the hierarchical structure of the synthesized netlist needs to be optimized according to the operation result includes:

the back-end processing device judges whether the hierarchical structure of the local device in the synthesized netlist needs to be optimized or not according to the operation result; and/or the presence of a gas in the gas,

and the back-end processing device judges whether the hierarchical structure of the local module in the synthesized netlist needs to be optimized or not according to the operation result.

As an alternative implementation manner, in the first aspect of the embodiment of the present invention, the hierarchical structure optimization indication includes at least a hierarchical optimization location area and/or a hierarchical optimization target direction;

the hierarchical optimization position area is used for indicating the position of an object to be optimized in the synthesized netlist, and the hierarchical optimization target direction is used for indicating the hierarchical identification of a target hierarchy to which the object to be optimized needs to move;

when the hierarchical structure of a local device in the synthesized netlist needs to be optimized, the target to be optimized comprises the local device; when the hierarchical structure of a local module in the synthesized netlist needs to be optimized, the target to be optimized comprises the local module; when the hierarchical structure of the local device and the hierarchical structure of the local module need to be optimized, the target to be optimized includes the local device and the local module.

As an alternative implementation, in the first aspect of the embodiment of the present invention, the front-end logic synthesis apparatus performing an optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate a new synthesized netlist, includes:

the front-end logic synthesis device modifies the hierarchical structure of the target to be optimized in the synthesized netlist according to the hierarchical structure optimization instruction and judges whether target operation needs to be executed on the synthesized netlist;

when the target operation does not need to be executed, the front-end logic synthesis device generates a new synthesized netlist according to the synthesized netlist after the hierarchical structure of the target to be optimized is modified;

wherein the target operation comprises at least one of a local synthesis operation and a local cross-module optimization operation.

As an optional implementation manner, in the first aspect of this embodiment of the present invention, the method further includes:

when the target operation needs to be executed, the front-end logic synthesis device executes the target operation on a target area which needs to execute the target operation in the synthesized netlist after the hierarchical structure of the target to be optimized is modified;

and the front-end logic synthesis device generates a new synthesized netlist according to the synthesized netlist after modifying the hierarchical structure of the target to be optimized and executing the target operation on the target region.

As an optional implementation manner, in the first aspect of the embodiment of the present invention, the determining, by the front-end logic synthesis apparatus, whether a target operation needs to be performed on the synthesized netlist includes:

and the front-end logic synthesis device judges whether the target operation needs to be executed on the synthesized netlist or not according to the type of the target to be optimized and the connection relation between the target to be optimized and the device under the target level.

As an optional implementation manner, in the first aspect of the embodiment of the present invention, after determining that the hierarchical structure of the synthesized netlist needs to be optimized, the method further includes:

the back-end processing device counts target times and judges whether the target times reach a preset time threshold value;

and when the target frequency is judged not to reach the preset frequency threshold value, the back-end processing device executes the operation of generating the hierarchical structure optimization instruction.

As an optional implementation manner, in the first aspect of the embodiment of the present invention, the target number is a total number of times of generation of the hierarchical optimization instruction corresponding to the back-end processing apparatus in a time period from the first time to the current time; or the target times are the total receiving times of the synthesized netlist corresponding to the back-end processing device in a time period from a second moment to the current moment;

the first time is earlier than the time when the back-end processing device generates the hierarchical structure optimization instruction corresponding to the initial synthesized netlist, the second time is earlier than the time when the back-end processing device receives the initial synthesized netlist, and the initial synthesized netlist is generated by the front-end logic synthesis device according to the read user design.

the back-end processing device determines a netlist mark of the read synthesized netlist, judges whether the netlist mark is one of a netlist mark set or not, and triggers and executes the operation of judging whether the hierarchical structure of the synthesized netlist needs to be optimized or not when judging that the netlist mark is not one of the netlist mark set;

the netlist identification set is used for storing netlist identifications of all synthesized netlists of which the backend processing device judges whether corresponding hierarchical structures need to be optimized or not.

The second aspect of the embodiments of the present invention discloses a front-end logic synthesis device, which includes:

the generating module is used for generating a synthesized netlist;

the detection module is used for detecting whether a hierarchical structure optimization instruction fed back by the back-end processing device aiming at the synthesized netlist generated by the generation module is received;

the generating module is further configured to, when the detecting module detects the hierarchical structure optimization instruction fed back by the back-end processing device, perform an optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate a new synthesized netlist;

the synthesized netlist generated by the generation module is used for being provided to the back-end processing device, so that the back-end processing device judges whether the hierarchical structure of the synthesized netlist needs to be optimized, and the hierarchical structure optimization indication is generated when the back-end processing device judges that the hierarchical structure of the synthesized netlist needs to be optimized.

As an alternative implementation manner, in the second aspect of the embodiment of the present invention, the hierarchical structure optimization indication includes at least a hierarchical optimization location area and/or a hierarchical optimization target direction;

As an alternative implementation, in the second aspect of the embodiment of the present invention, a specific manner of performing, by the generation module, an optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate a new synthesized netlist includes:

modifying the hierarchical structure of the target to be optimized in the synthesized netlist according to the hierarchical structure optimization instruction, and judging whether target operation needs to be executed on the synthesized netlist;

when the target operation is judged not to be executed, generating a new synthesized netlist according to the synthesized netlist after the hierarchical structure of the target to be optimized is modified;

As an optional implementation manner, in the second aspect of the embodiment of the present invention, a specific manner in which the generating module performs an optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate a new synthesized netlist further includes:

when the target operation is judged to be executed, executing the target operation on a target area which needs to execute the target operation in the synthesized netlist after the hierarchical structure of the target to be optimized is modified;

and generating a new synthesized netlist according to the synthesized netlist after modifying the hierarchical structure of the target to be optimized and executing the target operation on the target region.

As an optional implementation manner, in the second aspect of the embodiment of the present invention, the specific manner of determining whether the target operation needs to be performed on the synthesized netlist by the generation module is as follows:

and judging whether target operation needs to be executed on the synthesized netlist or not according to the type of the target to be optimized and the connection relation between the target to be optimized and the device under the target level.

A third aspect of the present invention discloses a back-end processing apparatus, including:

the reading module is used for reading a synthesized netlist generated by the front-end logic synthesis device;

the judging module is used for judging whether the hierarchical structure of the synthesized netlist needs to be optimized or not;

the optimization generation module is used for generating a hierarchical structure optimization instruction when the judgment module judges that the hierarchical structure of the synthesized netlist needs to be optimized;

and the communication module is used for feeding back the hierarchical structure optimization instruction to the front-end logic synthesis device so as to trigger the front-end logic synthesis device to execute optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate a new synthesized netlist and send the new synthesized netlist to the back-end processing device.

As an optional implementation manner, in the third aspect of the embodiment of the present invention, the back-end processing apparatus further includes:

the execution module is used for executing at least one operation in an operation set on the synthesized netlist after the reading module reads the synthesized netlist generated by the front-end logic synthesis device to obtain an operation result matched with the executed operation, and triggering the judgment module to execute the operation for judging whether the hierarchical structure of the synthesized netlist needs to be optimized; wherein the operation set comprises one or more of layout and wiring operation, timing analysis operation, hierarchical relationship complexity analysis operation, critical path analysis operation, power consumption analysis operation and net surface integral analysis operation;

and the specific way for judging whether the hierarchical structure of the synthesized netlist needs to be optimized by the judging module is as follows:

and judging whether the hierarchical structure of the synthesized netlist needs to be optimized or not according to the operation result.

As an optional implementation manner, in the third aspect of the embodiment of the present invention, the specific way for the determining module to determine whether the hierarchical structure of the synthesized netlist needs to be optimized according to the operation result is as follows:

judging whether the hierarchical structure of the local device in the synthesized netlist needs to be optimized or not according to the operation result; and/or the presence of a gas in the gas,

and judging whether the hierarchical structure of the local module in the synthesized netlist needs to be optimized or not according to the operation result.

As an optional implementation manner, in the third aspect of the embodiment of the present invention, the hierarchical structure optimization indication includes at least a hierarchical optimization location area and/or a hierarchical optimization target direction;

the statistical module is used for counting the target times after the judging module judges that the hierarchical structure of the synthesized netlist needs to be optimized;

the judging module is also used for judging whether the target times reach a preset time threshold value;

the optimization generation module is specifically configured to:

and generating a hierarchical structure optimization instruction when the judging module judges that the hierarchical structure of the synthesized netlist needs to be optimized and judges that the target times do not reach the preset times threshold value.

As an optional implementation manner, in the third aspect of the embodiment of the present invention, the target number is a total number of times of generation of the hierarchical optimization instruction corresponding to the back-end processing apparatus in a time period from the first time to the current time; or the target times are the total receiving times of the synthesized netlist corresponding to the back-end processing device in a time period from a second moment to the current moment;

the determining module is used for determining the netlist mark of the read synthesized netlist after the reading module reads the synthesized netlist generated by the front-end logic synthesizing device;

the judging module is further configured to judge whether the netlist mark is one of a set of netlist marks, and when it is judged that the netlist mark is not one of the set of netlist marks, trigger execution of the operation of judging whether the hierarchical structure of the synthesized netlist needs to be optimized;

The fourth aspect of the present invention discloses another front-end logic synthesis apparatus, where the front-end logic synthesis apparatus includes:

a memory storing executable program code;

a processor coupled with the memory;

the processor calls the executable program code stored in the memory to execute the steps executed by the front-end logic synthesis device in the hierarchical structure optimization method using the logic synthesis result as the guide disclosed by the first aspect of the embodiment of the invention.

A fifth aspect of the present invention discloses another back-end processing apparatus, including:

a memory storing executable program code;

a processor coupled with the memory;

the processor calls the executable program code stored in the memory to execute the steps executed by the back-end processing device in the hierarchical structure optimization method with the logic synthesis result as the guide disclosed in the first aspect of the embodiment of the invention.

A sixth aspect of the present invention discloses a computer-readable storage medium, where the computer-readable storage medium stores computer instructions, and the computer instructions, when called, are used to execute steps executed by a front-end logic synthesis apparatus in the hierarchical structure optimization method based on logic synthesis results disclosed in the first aspect of the present invention.

A seventh aspect of the present embodiment discloses a computer-readable storage medium, where the computer-readable storage medium stores a computer instruction, and the computer instruction is used, when being called, to execute steps executed by a back-end processing device in the hierarchical structure optimization method based on a logic synthesis result disclosed in the first aspect of the present embodiment.

An eighth aspect of the present invention discloses a hierarchical structure optimization system using a logic synthesis result as a guide, where the system includes a front-end logic synthesis apparatus disclosed in the second aspect of the present invention and a back-end processing apparatus disclosed in the third aspect of the present invention.

Compared with the prior art, the embodiment of the invention has the following beneficial effects:

by implementing the embodiment of the invention, whether the hierarchical structure of the synthesized netlist needs to be optimized can be judged after the back-end processing device reads the synthesized netlist, if the hierarchical structure needs to be optimized, the hierarchical structure optimization instruction is directly fed back to the front-end logic synthesis device, so that the front-end logic synthesis device optimizes the hierarchical structure in the synthesized netlist and generates a new synthesized netlist, the hierarchical structure of the synthesized netlist can be optimized according to the hierarchical structure optimization instruction fed back by the back-end processing device, the quality of front-end logic synthesis and the matching degree of the hierarchical structure in the synthesized back netlist generated by the front-end logic synthesis and the actual requirement of the back end are improved, and the design time sequence is improved and the power consumption is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic flow chart of a method for optimizing a hierarchical structure based on logic synthesis results according to an embodiment of the present invention;

FIG. 2 is a schematic flow chart of another method for optimizing a hierarchical structure based on logic synthesis results according to an embodiment of the present invention;

FIG. 3 is a schematic flow chart of another method for optimizing a hierarchical structure based on logic synthesis results according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a front-end logic synthesis apparatus according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of another front-end logic synthesis apparatus disclosed in the embodiments of the present invention;

fig. 6 is a schematic structural diagram of a back-end processing apparatus according to an embodiment of the disclosure;

FIG. 7 is a schematic structural diagram of another back-end processing apparatus disclosed in the embodiments of the present invention;

FIG. 8 is a schematic structural diagram of another back-end processing apparatus according to the disclosure of the present invention;

fig. 9 is a schematic structural diagram of a hierarchical structure optimization system oriented by a logic synthesis result according to an embodiment of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," and the like in the description and claims of the present invention and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, article, or article that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or article.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The invention discloses a hierarchical structure optimization method, a device and a system which take a logic synthesis result as a guide, which can realize the optimization of the hierarchical structure of a synthesized netlist according to the hierarchical structure optimization instruction fed back by a back-end processing device, improve the quality of front-end logic synthesis and the matching degree of the hierarchical structure in the synthesized netlist generated by the front-end logic synthesis and the actual requirement of the back end, and further are beneficial to improving the design time sequence and reducing the power consumption. The following are detailed below.

Referring to fig. 1, fig. 1 is a schematic flowchart illustrating a method for optimizing a hierarchical structure based on a logic synthesis result according to an embodiment of the present invention. Therein, the method described in fig. 1 may be applied in an EDA development tool comprising at least a front-end logic synthesis means and a back-end processing means. As shown in fig. 1, the method for optimizing a hierarchical structure based on logic synthesis results may include the following operations:

101. and the front-end logic synthesis device generates a synthesized netlist.

In the embodiment of the present invention, as an optional implementation manner, the generating of the synthesized netlist by the front-end logic synthesis device may include:

the front-end logic synthesis device reads the user design and generates a synthesized netlist according to the user design, wherein the synthesized netlist generated according to the read user design can also be called as an initial synthesized netlist.

In this alternative embodiment, the user design may be that the developer represents the designed system or circuit in some form required by the EDA development tool and inputs it to the EDA development tool by the developer. The input mode designed by the user can be an image input mode or an HDL text input mode, wherein the image input mode can comprise at least one of a schematic diagram input mode, a state diagram input mode and a waveform diagram input mode, and the HDL text input mode is specifically to edit and input a circuit design text using a hardware description language.

In this alternative embodiment, specifically, the generating the synthesized netlist according to the user design by the front-end logic synthesis apparatus may include:

the front-end logic synthesis device carries out compiling operation on the read user design to obtain a compiling result, wherein the compiling result is a topological structure between the functional blocks compiled by the user design;

the front-end logic synthesis device carries out logic recombination and logic optimization on the compiling result according to constraint control conditions applied by an operator so as to optimize the compiling result, wherein the constraint control conditions comprise a time sequence constraint control condition and an area constraint control condition, and can further comprise an environment constraint control condition;

the front-end logic synthesis device searches units meeting the conditions from the target process library according to the constraint control conditions applied by the operator and the optimized compiling result so as to form a synthesized netlist of the actual circuit.

The process of generating the synthesized netlist according to the user design can also be understood as a process of compiling, synthesizing, optimizing and mapping according to a given hardware structure component and a constraint control condition to finally obtain the synthesized netlist, and the synthesized netlist can be a gate-level circuit netlist or can describe netlist data for a circuit of a lower layer. The mapping process can be understood as an adaptation process, and the purpose of the mapping process is to configure the comprehensively optimized netlist data in a specified target device so as to generate a final download file.

Optionally, after reading the user design, the front-end logic synthesis apparatus may further perform the following operations:

and the front-end logic synthesis device determines the type of the user design, judges whether the type of the user design is one of the types in a preset type set, and triggers and executes the operation of generating the synthesized netlist according to the user design when the judgment result is yes, wherein the preset type set comprises all types of the user design which can be identified or processed by the front-end logic synthesis device.

Therefore, the optional implementation method can judge whether the type of the user design meets the requirement or not after reading the user design, and if so, the operation of generating the synthesized netlist is performed, so that the situation that the synthesized netlist cannot be generated or an incorrect synthesized netlist is generated due to the fact that the read user design does not meet the requirement can be reduced.

In this embodiment of the present invention, as another optional implementation, the generating a synthesized netlist by the front-end logic synthesis apparatus may also include:

and after receiving the hierarchical structure optimization instruction fed back by the back-end processing device, the front-end logic synthesis device executes optimization operation on the hierarchical structure of the synthesized netlist generated latest before according to the hierarchical structure optimization instruction to generate a new synthesized netlist.

102. The back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device, judges whether the hierarchical structure of the synthesized netlist needs to be optimized, and triggers to execute the step 103 when the judgment result of the step 102 is yes; when the determination result in step 102 is negative, the present process may be ended.

In the embodiment of the invention, the synthesized netlist generated by the front-end logic synthesis device read by the back-end processing device is the synthesized netlist newly generated by the front-end logic synthesis device. Optionally, the reading, by the back-end processing device, of the synthesized netlist generated by the front-end logic synthesis device may include:

the back-end processing device receives the synthesized netlist sent by the front-end logic synthesis device; alternatively, the first and second electrodes may be,

the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device from the storage device which stores the synthesized netlist generated by the front-end logic synthesis device directly or according to the copying operation/cutting operation of an operator; alternatively, the first and second liquid crystal display panels may be,

the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device from the memory data block in which the synthesized netlist generated by the front-end logic synthesis device is stored, and optionally, the memory data block may be a shared memory data block.

It should be noted that, in an implementation manner in which the back-end processing device receives the synthesized netlist sent by the front-end logic synthesis device, after the front-end logic synthesis device generates the synthesized netlist, the generated synthesized netlist may be directly sent to the back-end processing device, or the generated synthesized netlist may be sent to the back-end processing device according to a sending instruction triggered by an operator, or the generated synthesized netlist may be sent to the back-end processing device according to a synthesized netlist obtaining instruction sent by the back-end processing device, which is not limited in the embodiment of the present invention.

In the embodiment of the present invention, the back-end processing device may determine whether the hierarchical structure of the synthesized netlist needs to be optimized according to a preset algorithm, where the preset algorithm may include, but is not limited to, at least one of a layout and routing algorithm, a timing analysis algorithm, a power consumption analysis algorithm, a critical path analysis algorithm, a hierarchical complexity analysis algorithm, a local grid surface area analysis algorithm, and the like.

103. The back-end processing device generates a hierarchical structure optimization instruction and feeds the hierarchical structure optimization instruction back to the front-end logic synthesis device.

In the embodiment of the present invention, the hierarchical structure optimization instruction is generated according to the synthesized netlist received by the back-end processing device this time, and the hierarchical structure optimization instruction is used to instruct the front-end logic synthesis device to perform optimization operation on the hierarchical structure of the synthesized netlist newly sent to the back-end processing device so as to update the synthesized netlist needed to be sent to the back-end processing device (that is, to generate a new synthesized netlist needed to be sent to the back-end processing device). Optionally, the hierarchical optimization instruction may include a location area (also referred to as a "hierarchical optimization location area") that needs to be subjected to hierarchical optimization, and when the hierarchical optimization instruction includes a plurality of location areas that need to be subjected to hierarchical optimization, the hierarchical optimization instruction may further include a priority corresponding to each location area that needs to be subjected to hierarchical optimization, so that the front-end logic synthesis apparatus determines, when resources are insufficient when optimizing the hierarchical structure of the synthesized netlist, a location area corresponding to the content that is preferentially optimized according to the priority corresponding to each location area that needs to be subjected to hierarchical optimization. The higher the priority is, the higher the importance of the content to be optimized in the corresponding position area is, and under the condition of insufficient resources, the front-end logic synthesis device preferentially optimizes the content to be optimized in the position area with the higher priority so as to ensure the efficiency and accuracy of optimizing the part of content.

104. And when the hierarchical structure optimization instruction sent by the back-end processing device is received, the front-end logic synthesis device executes optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction so as to generate a new synthesized netlist.

In the embodiment of the present invention, it should be noted that the synthesized netlist generated by the front-end logic synthesis apparatus is used for providing to the back-end processing apparatus. After the step 104 is completed, the back-end processing device may continue to trigger the step 102. Optionally, the front-end logic synthesis device may directly optimize the hierarchical structure to be optimized on the basis of the synthesized netlist, so that the efficiency of optimizing the hierarchical structure can be improved.

In an alternative embodiment, the synthesized netlist generated by the front-end logic synthesis device each time has a netlist identification uniquely corresponding to the synthesized netlist. Further optionally, after generating the synthesized netlist, the front-end logic synthesis apparatus may further perform the following operations:

the front-end logic synthesis device sets a netlist mark uniquely corresponding to the synthesized netlist for the generated synthesized netlist, and optionally, the netlist mark may be generated according to the generation sequence and/or the generation time of the synthesized netlist.

In this alternative embodiment, after the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device, the following operations may be further performed:

the back-end processing device determines the netlist mark of the currently read synthesized netlist and judges the validity of the netlist mark of the currently read synthesized netlist;

and when judging that the netlist mark of the currently read synthesized netlist is effective, executing the operation of judging whether the hierarchical structure of the synthesized netlist needs to be optimized by the back-end processing device.

The netlist mark of the currently read synthesized netlist effectively indicates that the currently read synthesized netlist is the synthesized netlist which is not subjected to hierarchical structure optimization judgment by the back-end processing device, and optionally, when the netlist mark of the currently read synthesized netlist is judged to be invalid, the back-end processing device can output an error prompt for prompting that the currently read synthesized netlist is the repeatedly read synthesized netlist. Therefore, the method for judging the effectiveness of the currently read synthesized netlist can reduce the operation of repeatedly judging whether the hierarchical structure of the synthesized netlist needs to be optimized or not caused by the fact that the back-end processing device misreads the repeated synthesized netlist, and improves the accuracy and reliability of the optimized judgment of the read hierarchical structure of the synthesized netlist.

In this optional embodiment, as an optional implementation, the determining, by the back-end processing apparatus, validity of the netlist identification of the currently read synthesized netlist may include:

judging whether the netlist mark of the currently read synthesized netlist is one of the netlist mark sets or not by the back-end processing device, and determining that the netlist mark of the currently read synthesized netlist is valid when the netlist mark is judged not to be one of the netlist mark sets; and when the netlist mark is judged to be one of the netlist mark sets, determining that the netlist mark of the currently read synthesized netlist is invalid.

In this alternative embodiment, the netlist id set is used to store netlist ids of all synthesized netlists for which the back-end processing device has determined whether the corresponding hierarchical structure needs to be optimized. It should be noted that, after determining whether the hierarchical structure of one synthesized netlist needs to be optimized, the back-end processing device may automatically add a netlist identifier uniquely corresponding to the synthesized netlist to the netlist identifier set, so that after reading one synthesized netlist, the read netlist identifier of the synthesized netlist and the netlist identifier in the netlist identifier set are compared, and only when the read netlist identifier of the synthesized netlist does not exist in the netlist identifier set or when the netlist identifier set does not include the netlist identifier of the synthesized netlist currently read by the back-end processing device, subsequent determination operations are performed. Therefore, the validity of the netlist mark of the currently read synthesized netlist can be judged by comparing the netlist mark of the currently read synthesized netlist with the netlist marks in the netlist mark set, and the accuracy is high.

In this optional embodiment, as another optional implementation, the judging, by the back-end processing apparatus, the validity of the netlist identification of the currently read synthesized netlist may include:

the back-end processing device judges whether the netlist mark of the currently read synthesized netlist is the same as the netlist mark of the synthesized netlist read last time by the back-end processing device, and when the netlist mark of the currently read synthesized netlist is different, the back-end processing device determines that the netlist mark of the currently read synthesized netlist is valid; and when the two identical netlists are judged, determining that the netlist mark of the currently read synthesized netlist is invalid.

Therefore, the effectiveness judgment of the netlist mark of the currently read synthesized netlist can be performed according to the netlist mark of the currently read synthesized netlist and the netlist mark of the last read synthesized netlist, the comparison between the netlist mark of the currently read synthesized netlist and the netlist marks in the netlist mark set is not needed, the effectiveness judgment efficiency of the netlist mark of the currently read synthesized netlist is improved, and the optimization efficiency of optimizing the hierarchical structure of the synthesized netlist is further improved.

Therefore, by implementing the embodiment of the invention, the layout and wiring result is not directly output according to the synthesized netlist generated by the front-end logic synthesis device after the rear-end processing device reads the synthesized netlist, whether the hierarchical structure of the read synthesized netlist needs to be optimized is firstly judged, and the rear-end processing device feeds back the hierarchical structure optimization indication to the front-end logic synthesis device under the condition that the hierarchical structure optimization indication is judged, so that the front-end logic synthesis device optimizes the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization indication, namely, the front-end logic synthesis device and the rear-end processing device are not mutually independent in the FPGA chip development process, and the quality of front-end logic synthesis and the hierarchical structure of the synthesized rear-end netlist generated by the front-end logic synthesis and the actual rear-end need to be improved in a mode that the hierarchical structure optimization indication is fed back by the rear-end processing device and the hierarchical structure of the synthesized netlist is optimized by the front-end logic synthesis device according to the hierarchical structure optimization indication The matching degree is obtained, and therefore the design time sequence is promoted and the power consumption is reduced.

Example two

Referring to fig. 2, fig. 2 is a schematic flowchart of another method for optimizing a hierarchical structure based on logic synthesis results according to an embodiment of the present invention. Therein, the method described in fig. 2 can be applied in an EDA development tool, which comprises at least a front-end logic synthesis means and a back-end processing means. As shown in fig. 2, the method for optimizing a hierarchical structure based on logic synthesis results may include the following operations:

201. and the front-end logic synthesis device generates a synthesized netlist.

202. And the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device.

In the embodiment of the present invention, please refer to the detailed description of the steps 101-102 in the first embodiment for the detailed description of the steps 201-202, and the detailed description of the embodiment of the present invention is not repeated.

203. And the back-end processing device executes at least one operation in the operation set on the synthesized netlist to obtain an operation result matched with the executed operation.

In an embodiment of the present invention, the operation set at least includes one or more of a layout operation, a timing analysis operation, a hierarchical relationship complexity analysis operation, a critical path analysis operation, a power consumption analysis operation, and a grid surface integration analysis operation.

204. The back-end processing device judges whether the hierarchical structure of the synthesized netlist needs to be optimized according to the operation result, and when the judgment result of the step 204 is yes, the step 205 is triggered to be executed; when the determination result in step 204 is negative, the process may be ended.

Therefore, the embodiment of the invention can judge whether the hierarchical structure of the synthesized netlist needs to be optimized according to the operation requirement of the back-end processing device, namely whether the hierarchical structure of the synthesized netlist needs to be optimized according to the matching degree of the hierarchical structure of the synthesized netlist generated by the front-end logic synthesis device and the back-end requirement.

Specifically, the back-end processing device may determine whether the hierarchical structure of the synthesized netlist needs to be optimized by analyzing a connection relationship between modules and/or devices in the synthesized netlist and a back-end requirement. For example, if a device in the synthesized netlist has a single connection relationship with other devices in the same level, but the device has more connections with devices in other levels and the connections are relatively tight, the back-end processing device determines that the hierarchical structure of the device in the synthesized netlist needs to be optimized, and the corresponding optimization direction is to move the device to other levels with more connections and relatively tight connections, so that the connection relationships of the devices in different levels are simple, and the devices with tight connections are at the same level, thereby optimizing the hierarchical structure of the synthesized netlist; if the connection relationship between a device and other devices in the same level is equivalent to the connection relationship between the device and devices in other levels, whether the device is moved to other levels can be further determined according to the factors such as whether the layout structure of the device in the current level is matched with the chip structure, whether the routing resources are sufficient, whether the improvement of the time sequence is facilitated, and the like. Similarly, the optimized judgment and optimization direction of the hierarchical structure of the local module in the synthesized netlist can refer to the optimized judgment and optimization direction of the hierarchical structure of the local device in the synthesized netlist, and the embodiment of the invention is not described in detail.

205. The back-end processing device generates a hierarchical structure optimization instruction and feeds the hierarchical structure optimization instruction back to the front-end logic synthesis device.

In this embodiment of the present invention, optionally, the hierarchical structure optimization indication includes at least a hierarchical optimization location area and/or a hierarchical optimization target direction. The hierarchical optimization position area is used for indicating the position of the target to be optimized in the synthesized netlist, and the hierarchical optimization target direction is used for indicating the hierarchical identification of the target hierarchy to which the target to be optimized needs to move. When the hierarchical structure of the local device in the synthesized netlist needs to be optimized, the target to be optimized comprises the local device; when the hierarchical structure of the local module in the synthesized netlist needs to be optimized, the target to be optimized comprises the local module; when the hierarchical structure of the local device and the hierarchical structure of the local module need to be optimized, the target to be optimized includes the local device and the local module.

206. And the front-end logic synthesis device receives the hierarchical structure optimization instruction sent by the back-end processing device, and modifies the hierarchical structure of the target to be optimized in the synthesized netlist according to the hierarchical structure optimization instruction.

In the embodiment of the present invention, taking the target to be optimized as a local device as an example, if the device 1 is currently under level a and it connects level a and level B, when the back-end processing device finds that the device 1 is more appropriate under the level B, for example, better layout and routing results can be produced, the problem of shortage of routing resources can be solved, the time sequence can be improved, and the like, the back-end processing device generates a hierarchical structure optimization instruction comprising the device 1 (namely, a hierarchical optimization position area) and the level B (namely, a hierarchical optimization target direction) and feeds the hierarchical structure optimization instruction back to the front-end logic synthesis device, to instruct the front-end logic synthesis apparatus to move device 1 in the synthesized netlist from level a to below level B, and device 1 is still connected to level a and level B except that device 1 is not included in the devices below level a and device 1 is newly added in the devices below level B.

207. The front-end logic synthesis device judges whether target operation needs to be executed on the synthesized netlist, and when the judgment result in the step 207 is yes, the step 208-the step 209 are triggered and executed; and when the judgment result in the step 207 is negative, triggering to execute the step 210.

In this embodiment of the present invention, the target operation may include at least one of a local synthesis operation and a local cross-module optimization operation, which is not limited in this embodiment of the present invention.

As an alternative embodiment, the determining whether the target operation needs to be performed on the synthesized netlist by the front-end logic synthesis apparatus may include:

Specifically, the type of the target to be optimized is a device type and/or a module type. If the type of the target to be optimized is a device type, the front-end logic synthesis device can analyze the connection relation between the device to be optimized and the device under the target level, if the hierarchical structure of the device can be merged and simplified according to the connection relation, the local synthesis operation is determined to be executed, otherwise, only the hierarchical relation of the device needs to be changed. Similarly, if the type of the target to be optimized is a module type, the front-end logic synthesis device may analyze a connection relationship between the module to be optimized and a device under the target hierarchy, and if it is determined that the hierarchical structure of the module can be merged and simplified according to the connection relationship, it is determined that local cross-module optimization operation needs to be performed, otherwise, only the hierarchical relationship of the module needs to be changed. It should be noted that how to judge the hierarchical relationship of the devices or modules for merging and simplifying can be implemented according to the analysis result of the front-end logic synthesis device on the hierarchical structure of the synthesized netlist and the input-output relationship of the logic units.

Therefore, the optional implementation method can intelligently judge whether the target operation needs to be executed according to the type of the target to be optimized and the connection relation between the target to be optimized and the device under the target level, and the reliability and the accuracy of the judgment result are improved.

Further, the front-end logic synthesis device determines whether to execute a local synthesis operation on the synthesized netlist, and when the local synthesis operation needs to be executed on the synthesized netlist, the execution step 208 is triggered and the operation step 209 is triggered, at this time, the target operation at least comprises the local synthesis operation; when the partial synthesis operation on the synthesized netlist is not required, whether the partial cross-module optimization operation on the synthesized netlist is required or not can be further judged, when the judgment result is yes, the execution step 208 and the step 209 are triggered, at this time, the target operation only comprises the partial cross-module optimization operation, and when the judgment result is no, the execution step 210 can be directly triggered.

Further, when the partial synthesis operation needs to be performed on the synthesized netlist, before triggering the execution step 208 and the step 209, the front-end logic synthesis device may further determine whether the partial cross-module optimization operation needs to be performed on the synthesized netlist, and when the determination result is yes, the triggering execution step 208 and the step 209 are performed, and at this time, the target operation further includes the partial cross-module optimization operation; when the judgment result is negative, the

execution step

208 and 209 are triggered, and at this time, the target operation only comprises the partial comprehensive operation.

It should be noted that the front-end logic synthesis apparatus may also determine whether to perform local cross-module optimization on the synthesized netlist, and then further determine whether to perform local synthesis on the synthesized netlist. When the target operation includes both the local cross-module optimization operation and the local synthesis operation, the front-end logic synthesis device may execute the local synthesis operation first and then execute the local cross-module optimization operation, or may execute the local cross-module optimization operation first and then execute the local synthesis operation, which is not limited in the embodiment of the present invention.

It should be further noted that, when it is first determined whether to perform a local synthesis operation on the synthesized netlist, if the local synthesis operation needs to be performed, the local synthesis operation may be performed first, and then it is further determined whether to perform a local cross-module optimization operation, and if the local synthesis operation does not need to be performed, it may be further determined whether to perform the local cross-module optimization operation. If the local cross-module optimization operation needs to be executed, the local cross-module optimization operation is continuously executed and a new synthesized netlist is generated, and if the local cross-module optimization operation does not need to be executed, the new synthesized netlist can be generated according to a result obtained after the local synthesis operation is executed or the new synthesized netlist can be generated according to a result obtained after the hierarchical structure of the target to be optimized in the synthesized netlist is modified.

208. And the front-end logic synthesis device executes the target operation on the target area which needs to execute the target operation in the synthesized netlist after the hierarchical structure of the target to be optimized is modified.

209. And the front-end logic synthesis device generates a new synthesized netlist according to the synthesized netlist after modifying the hierarchical structure of the target to be optimized and executing target operation on the target region.

210. And the front-end logic synthesis device generates a new synthesized netlist according to the synthesized netlist after modifying the hierarchical structure of the target to be optimized.

After completing step 209 or step 210, the back-end processing device may continue to perform step 202.

In an optional embodiment, after the determination result in step 204 is yes, the method may further include the following operations:

the back-end processing device counts the target times and judges whether the target times reach a preset time threshold value; when the target times are judged not to reach the preset times threshold value, executing the operation of generating the hierarchical structure optimization instruction; alternatively, the first and second liquid crystal display panels may be,

and the back-end processing device counts the interactive accumulated time length, judges whether the interactive accumulated time length exceeds a preset time length threshold value or not, and executes the operation of generating the hierarchical structure optimization indication when the interactive accumulated time length exceeds the preset time length threshold value, wherein the interactive accumulated time length can be the time length from the time when the back-end processing device reads the initial synthesized netlist to the time when the judgment result of the step 204 is yes.

In yet another alternative embodiment, before the step 202 of completing and the step 203 of triggering execution, the method may further include the following operations:

the back-end processing device counts the target times and judges whether the target times reach a preset time threshold value; when the target times are judged not to reach the preset times threshold value, triggering to execute the step 203; alternatively, the first and second liquid crystal display panels may be,

and the back-end processing device counts the interactive accumulated time length, judges whether the interactive accumulated time length exceeds a preset time length threshold value or not, and triggers to execute the step 203 when the interactive accumulated time length exceeds the preset time length threshold value, wherein the interactive accumulated time length can be from the time when the back-end processing device reads the initial synthesized netlist to the time when the back-end processing device reads the latest synthesized netlist in the step 202.

Further optionally, the target times are total times of generation of the hierarchical structure optimization instruction corresponding to the back-end processing device in a time period from the first time to the current time; or the target frequency is the total receiving frequency of the synthesized netlist corresponding to the back-end processing device in the time period from the second time to the current time. The first moment is earlier than the moment when the back-end processing device generates the hierarchical structure optimization instruction corresponding to the initial synthesized netlist, the second moment is earlier than the moment when the back-end processing device receives the initial synthesized netlist, and the initial synthesized netlist is generated by the front-end logic synthesis device according to the read user design.

In the embodiment of the invention, the optimization interaction times of the back-end processing device and the front-end logic comprehensive device can be limited to a certain extent by setting the preset time threshold or the preset duration threshold, the infinite optimization is reduced, and the unnecessary waste of logic comprehensive resources is reduced. Still further optionally, when the target number of times exceeds the preset number of times threshold or the interactive accumulated duration exceeds the preset duration threshold, the back-end processing device may further perform the following operations:

the back-end processing device outputs an incomplete optimization indication, and the incomplete optimization indication is used for representing that the synthesized netlist on which the back-end processing device outputs the layout and routing result can be further optimized. Optionally, the incomplete optimization instruction may further include an initial synthesized netlist, an optimized synthesized netlist each time, and a place where the hierarchical structure of the synthesized netlist finally judged by the back-end processing device needs to be further optimized, so that a relevant operator can grasp the accuracy of the layout and routing result output by the back-end processing device, and further, the relevant operator can determine whether to adjust the user design according to the actual situation, and re-execute the steps described in the embodiment of the present invention.

In yet another alternative embodiment, after the back-end processing device generates the hierarchical optimization indication, the back-end processing device may further perform the following operations:

the back-end processing device sends an optimization confirmation request to the control device corresponding to the back-end processing device, wherein the optimization confirmation request comprises a hierarchical structure optimization instruction and is used for requesting the control device to control the corresponding output device to output the hierarchical structure optimization instruction for confirmation by an operator;

the back-end processing device receives an optimization confirmation response fed back by the control device according to the optimization confirmation request, and executes the operation of feeding back the hierarchical structure optimization instruction to the front-end logic synthesis device; wherein the optimization confirmation response is generated by the control device after receiving a confirmation message triggered by the operator for the optimization confirmation request.

Therefore, the hierarchical structure optimization instruction can be output through the output device controlled by the control device after the hierarchical structure optimization instruction is generated and confirmed by an operator, and the hierarchical structure optimization instruction is fed back to the front-end logic synthesis device after the operator confirms, so that the operator can select whether to optimize the hierarchical structure of the synthesized netlist according to actual requirements.

In yet another alternative embodiment, the front-end logic synthesis apparatus may further perform the following operations:

and when the hierarchical structure optimization instruction sent by the back-end processing device is not received, the front-end logic synthesis device synthesizes the optimized information of the synthesized netlist, and generates a synthesized netlist optimization record based on the synthesized netlist optimization information obtained through statistics.

The optimized information of the synthesized netlist comprises at least one of the total times of optimization of the synthesized netlist, the optimized instruction of the hierarchical structure corresponding to each optimization, the optimized result of the synthesized netlist, the optimized starting time corresponding to each optimization and the optimized finishing time corresponding to each optimization.

Therefore, the optional embodiment can also generate the optimization record of the synthesized netlist for the reference and the check of the operator according to the optimization process of the synthesized netlist when the hierarchical structure of the newly generated synthesized netlist does not need to be optimized, and is beneficial to realizing backtracking of the synthesized netlist.

Therefore, by means of the method and the device, the hierarchical structure optimization indication can be fed back by the back-end processing device, and the hierarchical structure of the synthesized netlist can be optimized by the front-end logic synthesis device according to the hierarchical structure optimization indication, so that the quality of front-end logic synthesis and the matching degree of the hierarchical structure in the synthesized netlist generated by the front-end logic synthesis and the actual needs of the back end are improved, and further the design time sequence is favorably improved and the power consumption is reduced. In addition, the back-end processing device can generate back-end requirements based on operation results of layout and wiring operation, timing analysis operation and the like, and further improves the matching degree of the hierarchical structure and the back-end actual requirements in the comprehensive back netlist generated by front-end logic synthesis. In addition, after the hierarchical structure of the target to be optimized is modified, whether local comprehensive operation and/or local cross-module optimization operation is needed or not can be further intelligently judged, the optimization depth and comprehensiveness of the synthesized netlist are improved, and the matching degree of the hierarchical structure in the synthesized netlist generated by front-end logic synthesis and the actual requirement of the back end is further improved. In addition, the optimization interaction times of the back-end processing device and the front-end logic comprehensive device can be limited to a certain extent by setting a preset time threshold or a preset duration threshold, the infinite optimization is reduced, and unnecessary waste of logic comprehensive resources is reduced. In addition, the operator can select whether to optimize the hierarchical structure of the synthesized netlist according to actual requirements. In addition, the method can be beneficial to realizing backtracking of the synthesized netlist.

EXAMPLE III

The embodiment of the invention discloses a hierarchical structure optimization method taking a logic comprehensive result as a guide. The method described in the present invention can be applied to a front-end logic synthesis device included in an EDA development tool, and the method for optimizing a hierarchical structure oriented by logic synthesis results can include the following operations:

the front-end logic synthesis device generates a synthesized netlist;

the front-end logic comprehensive device detects whether a hierarchical structure optimization instruction fed back by the rear-end processing device is received, and when the detection result is negative, the process can be ended; and when the detection result is yes, performing optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate a new synthesized netlist.

The synthesized netlist generated by the front-end logic synthesis device each time is provided to the back-end processing device, and the hierarchical structure optimization instruction is generated by the back-end processing device after the synthesized netlist generated by the front-end logic synthesis device is read and when the read hierarchical structure of the synthesized netlist needs to be optimized, the hierarchical structure is further judged by the back-end processing device.

Optionally, the hierarchical optimization indication may include at least a hierarchical optimization location area and/or a hierarchical optimization goal direction. The hierarchical optimization position area is used for indicating the position of the target to be optimized in the synthesized netlist, and the hierarchical optimization target direction is used for indicating the hierarchical identification of the target hierarchy to which the target to be optimized needs to move. When the hierarchical structure of the local device in the synthesized netlist needs to be optimized, the target to be optimized comprises the local device; when the hierarchical structure of the local module in the synthesized netlist needs to be optimized, the target to be optimized comprises the local module; when the hierarchical structure of the local device and the hierarchical structure of the local module need to be optimized, the target to be optimized includes the local device and the local module.

Optionally, the performing, by the front-end logic synthesis apparatus, an optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate a new synthesized netlist may include:

the front-end logic synthesis device modifies the hierarchical structure of the target to be optimized in the synthesized netlist according to the hierarchical structure optimization instruction and judges whether the target operation needs to be executed on the synthesized netlist;

and when the front-end logic synthesis device judges that the target operation does not need to be executed, generating a new synthesized netlist according to the synthesized netlist after the hierarchical structure of the target to be optimized is modified.

Further optionally, the performing, by the front-end logic synthesis apparatus, an optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate a new synthesized netlist may further include:

and the front-end logic synthesis device generates a new synthesized netlist according to the synthesized netlist after modifying the hierarchical structure of the target to be optimized and executing target operation on the target region.

Still further optionally, the determining, by the front-end logic synthesizing apparatus, whether the target operation needs to be performed on the synthesized netlist may include:

It should be noted that, in the embodiment of the present invention, for other operations executed by the front-end logic synthesis apparatus and a specific implementation manner of the executed operations, reference may be made to the detailed description of the front-end logic synthesis apparatus in the first embodiment or the second embodiment, and details of the embodiment of the present invention are not described again.

Therefore, after the front-end logic synthesis device generates the synthesized netlist, the hierarchical structure of the synthesized netlist can be optimized according to the hierarchical structure optimization instruction fed back by the back-end processing device, so that the matching degree of the logic synthesis result of the front-end logic synthesis device and the actual requirement of the back-end processing device is improved, the logic synthesis quality of the front-end logic synthesis device is improved, the layout and wiring result of the back-end processing device is improved, the time sequence design is improved, and the power consumption is reduced.

Example four

Referring to fig. 3, fig. 3 is a flowchart illustrating another method for optimizing a hierarchical structure based on logic synthesis results according to an embodiment of the present invention. Among other things, the method described in fig. 3 may be applied in a back-end processing device included in an EDA development tool. As shown in fig. 3, the method for optimizing a hierarchical structure based on logic synthesis results may include the following operations:

301. and the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device.

In the embodiment of the present invention, the synthesized netlist read by the back-end processing device may be a synthesized netlist (also referred to as an initial synthesized netlist) initially generated by the front-end logic synthesis device, or may be a new synthesized netlist generated by the front-end logic synthesis device after optimizing the hierarchical structure of the synthesized netlist generated last time, which is not limited in the embodiment of the present invention. Therefore, the embodiment of the invention can realize the multiple optimization of the hierarchical structure of the synthesized netlist generated by the front-end logic synthesis device, and is beneficial to improving the matching degree of the synthesized netlist generated by the front-end logic synthesis device and the actual requirement of the back-end processing device.

302. Judging whether the read hierarchical structure of the synthesized netlist needs to be optimized or not by the back-end processing device, and triggering to execute the step 303 when the judgment result in the step 302 is yes; when the determination result in step 302 is negative, the process may be ended.

303. The back-end processing device generates a hierarchical structure optimization instruction and feeds the hierarchical structure optimization instruction back to the front-end logic synthesis device.

In the embodiment of the present invention, the back-end processing device feeds back the hierarchical structure optimization instruction to the front-end logic synthesis device to trigger the front-end logic synthesis device to execute the following operations:

performing, by the front-end logic synthesis apparatus, an optimization operation on the hierarchical structure of the synthesized netlist newly provided to the back-end processing apparatus according to the received hierarchical structure optimization instruction to generate a new synthesized netlist, and providing the generated new synthesized netlist to the back-end processing apparatus to trigger the back-end processing apparatus to perform step 301.

Optionally, after the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device, the method may further include the following operations:

the back-end processing device executes at least one operation in the operation set on the synthesized netlist to obtain an operation result matched with the executed operation, and triggers and executes the operation for judging whether the hierarchical structure of the synthesized netlist needs to be optimized; the operation set comprises one or more combinations of a layout and routing operation, a timing analysis operation, a hierarchical relation complexity analysis operation, a critical path analysis operation, a power consumption analysis operation and a grid surface integral analysis operation.

The judging, by the back-end processing device, whether the hierarchical structure of the synthesized netlist needs to be optimized may include:

and judging whether the hierarchical structure of the synthesized netlist needs to be optimized or not by the back-end processing device according to the operation result.

Still further, the determining, by the back-end processing device, whether the hierarchical structure of the synthesized netlist needs to be optimized according to the operation result may include:

and judging whether the hierarchical structure of the local module in the synthesized netlist needs to be optimized or not by the back-end processing device according to the operation result.

Optionally, the hierarchical structure optimization instruction at least includes a hierarchical optimization position region and/or a hierarchical optimization target direction, where the hierarchical optimization position region is used to indicate a position of the target to be optimized in the synthesized netlist, and the hierarchical optimization target direction is used to indicate a hierarchical identifier of a target level to which the target to be optimized needs to be moved. When the hierarchical structure of the local device in the synthesized netlist needs to be optimized, the target to be optimized comprises the local device; when the hierarchical structure of the local module in the synthesized netlist needs to be optimized, the target to be optimized comprises the local module; when the hierarchical structure of the local device and the hierarchical structure of the local module need to be optimized, the target to be optimized includes the local device and the local module.

Optionally, after determining that the hierarchical structure of the synthesized netlist needs to be optimized, the back-end processing device may further perform the following operations:

the back-end processing device counts the target times and judges whether the target times reach a preset time threshold value;

when the target frequency is judged not to reach the preset frequency threshold value, the back-end processing device executes the operation of generating the hierarchical structure optimization instruction; alternatively, the first and second electrodes may be,

the back-end processing device counts the interactive accumulated time length and judges whether the interactive accumulated time length exceeds a preset time length threshold value or not;

and when the interactive accumulated time length is judged not to exceed the preset time length threshold value, the back-end processing device executes the operation of generating the hierarchical structure optimization indication.

Further optionally, the target times are total times of generation of the hierarchical structure optimization instruction corresponding to the back-end processing device in a time period from the first time to the current time; or the target frequency is the total receiving frequency of the synthesized netlist corresponding to the back-end processing device in a time period from a second moment to the current moment, the first moment is earlier than the moment when the back-end processing device generates the hierarchical structure optimization instruction corresponding to the initial synthesized netlist, the second moment is earlier than the moment when the back-end processing device receives the initial synthesized netlist, and the initial synthesized netlist is generated by the front-end logic synthesis device according to the read user design.

Optionally, after the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device, the back-end processing device may further perform the following operations:

the back-end processing device determines the netlist mark of the read synthesized netlist and judges the validity of the netlist mark of the read synthesized netlist;

and when the read netlist mark of the synthesized netlist is judged to be effective, the back-end processing device executes the operation of judging whether the hierarchical structure of the synthesized netlist needs to be optimized or not.

It should be noted that, in the embodiment of the present invention, for other steps executed by the back-end processing device and a specific implementation manner of executing a certain step by the back-end processing device, reference may be made to the detailed description in the first embodiment or the second embodiment, and details of the embodiment of the present invention are not described again.

Therefore, by implementing the method described in fig. 3, the back-end processing device can feed back the hierarchical structure optimization instruction according to the actual requirement, so as to optimize the hierarchical structure of the synthesized netlist generated by the front-end logic synthesis device, improve the quality of front-end logic synthesis and the matching degree between the hierarchical structure in the synthesized netlist generated by the front-end logic synthesis and the actual requirement of the back end, and further facilitate the improvement of the design timing sequence and the reduction of power consumption.

EXAMPLE five

Referring to fig. 4, fig. 4 is a schematic structural diagram of a front-end logic synthesis apparatus according to an embodiment of the present invention. As shown in fig. 4, the front-end logic synthesis apparatus may include:

and a generating module 401, configured to generate a synthesized netlist.

A detecting module 402, configured to detect whether a hierarchical structure optimization instruction fed back by the back-end processing apparatus for the synthesized netlist generated by the generating module 401 is received.

The generating module 401 is further configured to, when the detecting module 402 detects the hierarchical structure optimization instruction fed back by the back-end processing apparatus, perform an optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate a new synthesized netlist.

The synthesized netlist generated by the generation module 401 is used for providing to a back-end processing device, so that the back-end processing device determines whether the hierarchical structure of the synthesized netlist needs to be optimized, and the hierarchical structure optimization indication is generated when the back-end processing device determines that the hierarchical structure of the synthesized netlist needs to be optimized.

In an optional embodiment, the hierarchical structure optimization indication at least includes a hierarchical optimization position region and/or a hierarchical optimization target direction, the hierarchical optimization position region is used for indicating the position of the target to be optimized in the synthesized netlist, and the hierarchical optimization target direction is used for indicating the hierarchical identification of the target hierarchy to which the target to be optimized needs to move. When the hierarchical structure of the local device in the synthesized netlist needs to be optimized, the target to be optimized comprises the local device; when the hierarchical structure of the local module in the synthesized netlist needs to be optimized, the target to be optimized comprises the local module; when the hierarchical structure of the local device and the hierarchical structure of the local module need to be optimized, the target to be optimized includes the local device and the local module.

In this alternative embodiment, further optionally, the specific manner for the generation module 401 to perform the optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate the new synthesized netlist includes:

and when the target operation is judged not to be executed, generating a new synthesized netlist according to the synthesized netlist after the hierarchical structure of the target to be optimized is modified.

Wherein the target operation may comprise at least one of a local synthesis operation and a local cross-module optimization operation.

Still further optionally, the specific manner of the generating module 401 performing the optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate the new synthesized netlist may further include:

when the target operation is judged to be executed, executing the target operation on a target area which needs to be executed in the synthesized netlist after the hierarchical structure of the target to be optimized is modified;

and generating a new synthesized netlist according to the synthesized netlist after modifying the hierarchical structure of the target to be optimized and executing target operation on the target region.

Still further optionally, the specific way for the generating module 401 to determine whether the synthesized netlist needs to be subjected to the target operation is as follows:

and judging whether the target operation needs to be executed on the synthesized netlist or not according to the type of the target to be optimized and the connection relation between the target to be optimized and the device under the target level.

It should be noted that, for the explanation of the other functions of the front-end logic synthesis apparatus and the functions of the front-end logic synthesis apparatus described in fig. 4, refer to the detailed description of the steps executed by the front-end logic synthesis apparatus and the specific implementation manner of the steps executed by the front-end logic synthesis apparatus in the first embodiment or the second embodiment, and the detailed description of the embodiments of the present invention is omitted.

It can be seen that, by implementing the front-end logic synthesis apparatus described in fig. 4, the quality of front-end logic synthesis and the matching degree between the hierarchical structure in the synthesized netlist generated by the front-end logic synthesis and the actual requirement of the rear end can be improved by feeding back the hierarchical structure optimization indication by the rear-end processing apparatus and optimizing the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization indication by the front-end logic synthesis apparatus, which is further beneficial to improving the design timing and reducing the power consumption.

Example six

Referring to fig. 5, fig. 5 is a schematic structural diagram of another front-end logic synthesis apparatus according to an embodiment of the present invention. As shown in fig. 5, the front-end logic synthesis apparatus may include:

a memory 501 in which executable program code is stored;

a processor 502 coupled to a memory 501;

the processor 502 calls the executable program code stored in the memory 501 to execute the steps executed by the front-end logic synthesis apparatus in the hierarchical structure optimization method using the logic synthesis result as the guide, which is disclosed in the first to third embodiments of the present invention.

EXAMPLE seven

Referring to fig. 6, fig. 6 is a schematic structural diagram of another back-end processing device according to an embodiment of the disclosure. As shown in fig. 6, the back-end processing apparatus may include:

the reading module 601 is configured to read a synthesized netlist generated by the front-end logic synthesis apparatus.

And a judging module 602, configured to judge whether the hierarchical structure of the read synthesized netlist needs to be optimized.

And an optimization generating module 603, configured to generate a hierarchical structure optimization instruction when the determining module 602 determines that the hierarchical structure of the synthesized netlist needs to be optimized.

The communication module 604 is configured to feed back the hierarchical structure optimization instruction to the front-end logic synthesis apparatus, so as to trigger the front-end logic synthesis apparatus to perform an optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction, so as to generate a new synthesized netlist and send the new synthesized netlist to the back-end processing apparatus.

In an alternative embodiment, as shown in fig. 7, the back-end processing apparatus may further include:

an executing module 605, configured to, after the reading module 601 reads the synthesized netlist generated by the front-end logic synthesizing apparatus, execute at least one operation in the operation set on the synthesized netlist to obtain an operation result matched with the executed operation, and trigger the determining module 602 to execute the operation of determining whether the hierarchical structure of the synthesized netlist needs to be optimized. The operation set at least comprises one or more combinations of layout and wiring operation, time sequence analysis operation, hierarchical relation complexity analysis operation, critical path analysis operation, power consumption analysis operation and net surface integral analysis operation.

In this alternative embodiment, the specific way for the determining module 602 to determine whether the hierarchical structure of the synthesized netlist needs to be optimized may be:

Further optionally, the specific way for the determining module 602 to determine whether the hierarchical structure of the synthesized netlist needs to be optimized according to the operation result may be:

Still further optionally, the hierarchical optimization indication includes at least a hierarchical optimization location area and/or a hierarchical optimization goal direction. The hierarchical optimization position area is used for indicating the position of the target to be optimized in the synthesized netlist, and the hierarchical optimization target direction is used for indicating the hierarchical identification of the target hierarchy to which the target to be optimized needs to move. When the hierarchical structure of the local device in the synthesized netlist needs to be optimized, the target to be optimized comprises the local device; when the hierarchical structure of the local module in the synthesized netlist needs to be optimized, the target to be optimized comprises the local module; when the hierarchical structure of the local device and the hierarchical structure of the local module need to be optimized, the target to be optimized includes the local device and the local module.

In another alternative embodiment, as shown in fig. 7, the back-end processing apparatus may further include a statistics module 606, wherein:

a counting module 606, configured to count the target times after the determining module 602 determines that the hierarchical structure of the synthesized netlist needs to be optimized.

The determining module 602 is further configured to determine whether the target number of times reaches a preset number threshold.

The optimization generation module 306 is specifically configured to:

when the judging module 602 judges that the hierarchical structure of the synthesized netlist needs to be optimized and judges that the target times do not reach a preset time threshold, generating a hierarchical structure optimization instruction; alternatively, the first and second electrodes may be,

a statistic module 606, configured to count the interactive accumulated time length after the determining module 602 determines that the hierarchical structure of the synthesized netlist needs to be optimized.

The determining module 602 is further configured to determine whether the interactive accumulated time length exceeds a preset time length threshold.

The optimization generation module 306 is specifically configured to:

when the judging module 602 judges that the hierarchical structure of the synthesized netlist needs to be optimized and judges that the interactive accumulated time exceeds the preset time threshold, a hierarchical structure optimization instruction is generated.

Further optionally, the target times are total times of generation of the hierarchical structure optimization instruction corresponding to the back-end processing device in a time period from the first time to the current time; or the target frequency is the total receiving frequency of the synthesized netlist corresponding to the back-end processing device in a time period from the second moment to the current moment. The first moment is earlier than the moment when the back-end processing device generates the hierarchical structure optimization instruction corresponding to the initial synthesized netlist, the second moment is earlier than the moment when the back-end processing device receives the initial synthesized netlist, and the initial synthesized netlist is generated by the front-end logic synthesis device according to the read user design.

In yet another alternative embodiment, as shown in fig. 7, the back-end processing apparatus may further include:

a determining module 607, configured to determine a netlist id of the read synthesized netlist after the reading module 601 reads the synthesized netlist generated by the front-end logic synthesis apparatus.

The judging module 602 is further configured to judge validity of the netlist mark of the read synthesized netlist, and when the netlist mark of the read synthesized netlist is judged to be valid, trigger execution of the operation of judging whether the hierarchical structure of the synthesized netlist needs to be optimized.

In this optional embodiment, further optionally, the specific way for the determining module 602 to determine the validity of the netlist mark of the read synthesized netlist may be as follows:

judging whether the netlist mark of the currently read synthesized netlist is one of the netlist mark sets or not, and when the netlist mark is judged not to be one of the netlist mark sets, determining that the netlist mark of the currently read synthesized netlist is valid; when the netlist mark is judged to be one of the netlist mark sets, determining that the currently read netlist mark of the synthesized netlist is invalid; alternatively, the first and second electrodes may be,

judging whether the netlist mark of the currently read synthesized netlist is the same as the netlist mark of the synthesized netlist read last time by the back-end processing device, and when the netlist mark of the currently read synthesized netlist is different, determining that the netlist mark of the currently read synthesized netlist is valid; and when the two identical netlist are judged, determining that the netlist mark of the currently read synthesized netlist is invalid.

Therefore, by implementing the back-end processing device described in fig. 7, the hierarchical structure optimization instruction can be fed back according to the actual demand, so that the front-end logic synthesis device optimizes the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction, the quality of front-end logic synthesis and the matching degree of the hierarchical structure in the synthesized netlist generated by the front-end logic synthesis and the actual demand of the back end are improved, and further, the design timing sequence is improved and the power consumption is reduced. In addition, the back-end processing device can generate back-end requirements based on operation results of layout and wiring operation, timing analysis operation and the like, and further improves the matching degree of the hierarchical structure and the back-end actual requirements in the comprehensive back netlist generated by front-end logic synthesis. In addition, after the hierarchical structure of the target to be optimized is modified, whether local logic synthesis operation and/or local cross-module optimization operation is needed or not can be further intelligently judged, the optimization depth and comprehensiveness of the synthesized netlist are improved, and the matching degree of the hierarchical structure in the synthesized netlist generated by front-end logic synthesis and the actual requirement of the back end is further improved. In addition, the optimization interaction times of the back-end processing device and the front-end logic synthesis device can be limited to a certain extent by setting a preset time threshold or a preset duration threshold, the infinite optimization condition is reduced, and unnecessary waste of logic synthesis resources is reduced. In addition, the method for judging the effectiveness of the currently read synthesized netlist can reduce the operation of repeatedly judging whether the hierarchical structure of the synthesized netlist needs to be optimized or not caused by the fact that the processing device misreads the repeated synthesized netlist, and improves the accuracy and reliability of the optimized judgment of the read hierarchical structure of the synthesized netlist.

Example eight

Referring to fig. 8, fig. 8 is a schematic structural diagram of another back-end processing device according to an embodiment of the disclosure. As shown in fig. 8, the back-end processing apparatus may include, as shown in fig. 8:

a memory 701 in which executable program code is stored;

a processor 702 coupled to the memory 701;

the processor 702 calls the executable program code stored in the memory 701 to execute the steps executed by the back-end processing device in the hierarchical structure optimization method based on the logic synthesis result disclosed in the first embodiment, the second embodiment or the fourth embodiment of the present invention.

Example nine

Referring to fig. 9, fig. 9 is a schematic structural diagram of a hierarchical structure optimization system based on logic synthesis results according to an embodiment of the present invention. As shown in fig. 9, the system may include a front-end logic synthesis apparatus described in embodiment five and a back-end processing apparatus described in embodiment seven.

Example ten

The embodiment of the invention discloses a computer-storable medium, which stores computer instructions, and the computer instructions are used for steps executed by a front-end logic synthesis device in the hierarchical structure optimization method which takes a logic synthesis result as a guide and is disclosed in any one of the first embodiment to the third embodiment of the invention when being called.

EXAMPLE eleven

The embodiment of the invention discloses a computer-storable medium, which stores computer instructions, and the computer instructions are used for steps executed by a back-end processing device in the hierarchical structure optimization method which takes a logic comprehensive result as a guide and is disclosed in the first embodiment, the second embodiment or the fourth embodiment of the invention when being called.

The above-described embodiments of the apparatus are merely illustrative, and the modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Through the above detailed description of the embodiments, those skilled in the art will clearly understand that the embodiments may be implemented by software plus a necessary general hardware platform, and may also be implemented by hardware. Based on such understanding, the above technical solutions may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, where the storage medium includes a Read-Only Memory (ROM), a Random Access Memory (RAM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), a One-time Programmable Read-Only Memory (OTPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Compact Disc-Read-Only Memory (CD-ROM), or other disk memories, CD-ROMs, or other magnetic disks, A tape memory, or any other medium readable by a computer that can be used to carry or store data.

Finally, it should be noted that: the method, apparatus and system for optimizing a hierarchical structure based on logic synthesis results disclosed in the embodiments of the present invention are only preferred embodiments of the present invention, and are only used for illustrating the technical solutions of the present invention, rather than for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A method for logical synthesis result-oriented hierarchical structure optimization, the method comprising:

the front-end logic synthesis device generates a synthesized netlist;

the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device and judges whether the hierarchical structure of the synthesized netlist needs to be optimized; when the hierarchical structure of the synthesized netlist needs to be optimized, generating a hierarchical structure optimization instruction, and feeding the hierarchical structure optimization instruction back to the front-end logic synthesis device; the hierarchical optimization indication comprises at least a hierarchical optimization location area and/or a hierarchical optimization goal direction; the hierarchical optimization position area is used for indicating the position of an object to be optimized in the synthesized netlist, and the hierarchical optimization target direction is used for indicating the hierarchical identification of a target hierarchy to which the object to be optimized needs to move;

wherein the synthesized netlist generated by the front-end logic synthesis device is used for being provided to the back-end processing device;

and after the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device, the method further comprises:

2. The method for optimizing a hierarchical structure based on logic synthesis result as claimed in claim 1, wherein the determining, by the back-end processing device, whether the hierarchical structure of the synthesized netlist needs to be optimized according to the operation result comprises:

the back-end processing device judges whether the hierarchical structure of the local device in the synthesized netlist needs to be optimized or not according to the operation result; and/or the presence of a gas in the atmosphere,

3. The logic synthesis result-oriented hierarchical structure optimization method according to claim 1 or 2, wherein when the hierarchical structure of a local device in the synthesized netlist needs to be optimized, the target to be optimized comprises the local device; when the hierarchical structure of a local module in the synthesized netlist needs to be optimized, the target to be optimized comprises the local module; when the hierarchical structure of the local device and the hierarchical structure of the local module need to be optimized, the target to be optimized includes the local device and the local module.

4. The logic synthesis result-oriented hierarchical structure optimization method according to claim 3, wherein the front-end logic synthesis apparatus performs an optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate a new synthesized netlist, comprising:

when the target operation is judged not to be executed, the front-end logic synthesis device generates a new synthesized netlist according to the synthesized netlist after the hierarchical structure of the target to be optimized is modified;

5. The method of logic synthesis result-oriented hierarchical structure optimization according to claim 4, further comprising:

and the front-end logic synthesis device generates a new synthesized netlist according to the synthesized netlist after modifying the hierarchical structure of the target to be optimized and executing the target operation on the target area.

6. The logic synthesis result-oriented hierarchical structure optimization method according to claim 4 or 5, wherein the front-end logic synthesis device determines whether a target operation needs to be performed on the synthesized netlist, and includes:

7. The logic synthesis result-oriented hierarchical structure optimization method according to claim 1, 2, 4 or 5, wherein after determining that the hierarchical structure of the synthesized netlist needs to be optimized, the method further comprises:

and when the target times are judged not to reach the preset times threshold value, the back-end processing device executes the operation of generating the hierarchical structure optimization instruction.

8. The logic synthesis result-oriented hierarchical structure optimization method according to claim 7, wherein the target number of times is a total number of times of generation of the hierarchical structure optimization indication corresponding to the back-end processing device in a time period from a first time to a current time; or the target times are the total receiving times of the synthesized netlist corresponding to the back-end processing device in a time period from a second moment to the current moment;

9. The logic synthesis result-oriented hierarchical structure optimization method according to claim 1, 2, 4 or 5, wherein after the back-end processing device reads the synthesized netlist generated by the front-end logic synthesis device, the method further comprises:

10. A front-end logic synthesis apparatus, the front-end logic synthesis apparatus comprising:

the generating module is used for generating a synthesized netlist;

the synthesized netlist generated by the generation module is used for being provided to the back-end processing device, so that the back-end processing device executes at least one operation in an operation set on the synthesized netlist to obtain an operation result matched with the executed operation, and judges whether the hierarchical structure of the synthesized netlist needs to be optimized according to the operation result, and the hierarchical structure optimization indication is generated when the back-end processing device judges that the hierarchical structure of the synthesized netlist needs to be optimized; the hierarchical optimization indication comprises at least a hierarchical optimization location area and/or a hierarchical optimization target direction; the hierarchical optimization position area is used for indicating the position of an object to be optimized in the synthesized netlist, the hierarchical optimization target direction is used for indicating a hierarchical identification of a target hierarchy to which the object to be optimized needs to move, and the operation set comprises one or more of layout and routing operation, timing analysis operation, hierarchical relationship complexity analysis operation, critical path analysis operation, power consumption analysis operation and net surface integration analysis operation.

11. A back-end processing apparatus, characterized in that the back-end processing apparatus comprises:

the optimization generation module is used for generating a hierarchical structure optimization instruction when the judgment module judges that the hierarchical structure of the synthesized netlist needs to be optimized; the hierarchical optimization indication comprises at least a hierarchical optimization location area and/or a hierarchical optimization target direction; the hierarchical optimization position area is used for indicating the position of an object to be optimized in the synthesized netlist, and the hierarchical optimization target direction is used for indicating the hierarchical identification of a target hierarchy to which the object to be optimized needs to move;

the communication module is used for feeding the hierarchical structure optimization instruction back to the front-end logic synthesis device so as to trigger the front-end logic synthesis device to execute optimization operation on the hierarchical structure of the synthesized netlist according to the hierarchical structure optimization instruction to generate a new synthesized netlist and send the new synthesized netlist to the back-end processing device;

wherein the back-end processing apparatus further comprises:

the execution module is used for executing at least one operation in the operation set on the synthesized netlist after the reading module reads the synthesized netlist generated by the front-end logic synthesis device to obtain an operation result matched with the executed operation, and triggering the judgment module to execute the operation for judging whether the hierarchical structure of the synthesized netlist needs to be optimized; wherein the operation set at least comprises one or more of layout and wiring operation, timing analysis operation, hierarchical relationship complexity analysis operation, critical path analysis operation, power consumption analysis operation and net surface integral analysis operation;

12. A logical synthesis result-oriented hierarchical optimization system, characterized in that the system comprises a front-end logical synthesis apparatus according to claim 10 and a back-end processing apparatus according to claim 11.