CN111130346B - DC converter and digital fixed on-time controller - Google Patents
DC converter and digital fixed on-time controller Download PDFInfo
- Publication number
- CN111130346B CN111130346B CN201811297217.8A CN201811297217A CN111130346B CN 111130346 B CN111130346 B CN 111130346B CN 201811297217 A CN201811297217 A CN 201811297217A CN 111130346 B CN111130346 B CN 111130346B
- Authority
- CN
- China
- Prior art keywords
- voltage
- switching
- sensing
- valley
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
A digital fixed on-time controller suitable for a DC converter comprises a current sensing circuit, a voltage sensing circuit and a control circuit, wherein the current sensing circuit senses the stored energy of the DC converter to generate a sensing voltage; the offset cancellation circuit receives the sensing voltage and generates an offset removal sensing voltage according to the trough voltage of the sensing voltage; a comparator that compares the offset-removed sensing voltage with a reference signal; and a PWM generator for generating a switching control signal according to the comparison result of the comparator.
Description
Technical Field
The present invention relates to a direct current (DC-to-DC) converter, and more particularly, to a DC converter with output voltage offset cancellation (offset cancellation).
Background
A power converter (power converter) is an electronic circuit that converts electrical energy from one form to another. A direct current (DC-to-DC) converter is one type of power converter for converting a DC source from one voltage level to another. In a dc converter, an inductor is usually disposed between a switching circuit and an output node to store energy.
The dc converter usually uses an analog current sensing circuit to sense the inductor current, so as to control the switching of the switching circuit. For a constant on-time (COT) dc converter, a ripple-based analog control is used to compare a sensed inductor current with a reference voltage, so as to generate a control signal for controlling the switching of a switching circuit. However, this mechanism generates an output voltage offset error, thereby reducing the regulation performance of the dc converter.
Therefore, it is desirable to provide a novel dc converter to improve the output voltage offset.
Disclosure of Invention
In view of the foregoing, an objective of embodiments of the present invention is to provide a direct current (DC-to-DC) converter with output voltage offset cancellation, and particularly a digital fixed on-time controller suitable for a DC converter, which can effectively cancel the output voltage offset.
The purpose of the invention and the technical problem to be solved are realized by adopting the following technical scheme. According to the present invention, a digital fixed on-time controller for a dc converter comprises: a current sensing circuit for sensing the stored energy of the DC converter to generate a sensing voltage; an offset cancellation circuit, which receives the sensing voltage and generates an offset removal sensing voltage according to the valley voltage of the sensing voltage; a comparator that compares the offset-removed sensing voltage with a reference signal; and a PWM generator for generating a switching control signal according to the comparison result of the comparator.
The object of the present invention and the technical problems solved thereby can be further achieved by the following technical measures.
The aforementioned digital fixed on-time controller for a dc converter, wherein the current sensing circuit comprises: a high-pass filter and a low-pass filter for respectively receiving the digital output voltage and the switching control signal; and a first adder for adding the output of the high-pass filter and the output of the low-pass filter to generate the sensing voltage.
The aforementioned digital fixed on-time controller for a dc converter, wherein the offset cancellation circuit comprises: a valley detector for receiving the switching control signal and detecting the valley voltage; a second adder that subtracts the valley voltage from the sensing voltage to generate a zero valley sensing voltage; and a third adder that adds the valley zero sensing voltage and the digital output voltage to generate the offset-removed sensing voltage.
The aforementioned digital fixed on-time controller for a dc converter, wherein the current sensing circuit comprises: a high pass filter and a low pass filter for receiving the digital output voltage and the digital switching voltage, respectively; and a first adder for adding the output of the high-pass filter and the output of the low-pass filter to generate the sensing voltage.
The aforementioned digital fixed on-time controller for a dc converter, wherein the offset cancellation circuit comprises: a valley detector for receiving the digital switching voltage to detect the valley voltage; a second adder that subtracts the valley voltage from the sensing voltage to generate a zero valley sensing voltage; and a third adder that adds the valley zero sensing voltage and the digital output voltage to generate the offset-removed sensing voltage.
The purpose of the invention and the technical problem to be solved are also realized by adopting the following technical scheme. According to the present invention, a dc converter comprises: a switching circuit for generating a switching voltage; an energy storage circuit receiving the switching voltage to generate an output voltage; a first analog-to-digital converter for generating an equivalent digital output voltage of the output voltage; a digital fixed on-time controller receiving the digital output voltage to generate a switching control signal; the driver generates at least one driving signal according to the switching control signal to drive the switching circuit; wherein the digital fixed on-time controller comprises: a current sensing circuit that senses stored energy of the energy storage circuit to generate a sensing voltage; an offset cancellation circuit, which receives the sensing voltage and generates an offset removal sensing voltage according to the valley voltage of the sensing voltage; a comparator that compares the offset-removed sensing voltage with a reference signal; and a PWM generator for generating a switching control signal according to the comparison result of the comparator.
The object of the present invention and the technical problems solved thereby can be further achieved by the following technical measures.
In an embodiment of the present invention, the current sensing circuit includes: a high-pass filter and a low-pass filter for receiving the digital output voltage and the switching control signal respectively; and a first adder for adding the output of the high-pass filter and the output of the low-pass filter to generate the sensing voltage.
In an embodiment of the present invention, the offset cancellation circuit includes: a valley detector for receiving the switching control signal and detecting the valley voltage; a second adder that subtracts the valley voltage from the sensing voltage to generate a zero valley sensing voltage; and a third adder that adds the valley zero sensing voltage and the digital output voltage to generate the offset-removed sensing voltage.
The dc converter further includes a second analog-to-digital converter for generating an equivalent digital switching voltage of the switching voltage.
In an embodiment of the present invention, the current sensing circuit includes: a high-pass filter and a low-pass filter for receiving the digital output voltage and the digital switching voltage, respectively; and a first adder for adding the output of the high-pass filter and the output of the low-pass filter to generate the sensing voltage.
In an embodiment of the present invention, the offset cancellation circuit includes: a valley detector for receiving the digital switching voltage to detect the valley voltage; a second adder that subtracts the valley voltage from the sensing voltage to generate a zero valley sensing voltage; and a third adder that adds the valley zero sensing voltage and the digital output voltage to generate the offset-removed sensing voltage.
In an embodiment, the switching circuit includes a first switching device and a second switching device connected in series between a power source and ground, and the switching voltage is generated at a switching node between the first switching device and the second switching device.
In an embodiment, the first switching device comprises a pmos transistor, the second switching device comprises an nmos transistor, the first switching device is electrically connected between the power supply and the switching node, and the second switching device is electrically connected between the switching node and ground.
In an embodiment, the energy storage circuit comprises an inductor and an effective series resistor connected in series between the switching node and an output node, the output node providing the output voltage.
By the technical scheme, the direct current converter and the digital fixed conduction time controller at least have the following advantages and effects:
according to an embodiment of the present invention, a digital fixed on-time controller for a dc converter includes a current sensing circuit, an offset cancellation circuit, a comparator and a pwm generator. The current sensing circuit senses the stored energy of the DC converter to generate a sensing voltage. The offset cancellation circuit receives the sensing voltage and generates an offset removal sensing voltage according to a valley voltage of the sensing voltage. The comparator compares the offset-removed sensing voltage with a reference signal. The PWM generator generates a switching control signal according to the comparison result of the comparator.
Drawings
Fig. 1A shows a block diagram of a dc converter with output voltage offset cancellation according to a first embodiment of the present invention.
Fig. 1B shows a circuit diagram of a part of the block of fig. 1A.
FIG. 2A is a block diagram of the digital fixed on-time controller of FIG. 1A according to a first embodiment of the present invention.
Fig. 2B shows a detailed block diagram of a portion of the blocks of fig. 2A.
FIG. 2C illustrates an equivalent analog architecture of the current sensing circuit of FIG. 2B.
FIG. 3A illustrates an exemplary cross-over effective series resistor R-LAnd displays the valley voltage Vvalley。
FIG. 3B illustrates a waveform of the zero valley sensing voltage, which is at 0.5RLIL(ripple)Is located in the center of (1).
FIG. 3C illustrates the waveform of the offset-removed sensing voltage at 0.5RLIL(ripple)+ Vo center.
FIG. 3D shows signals associated with the comparator and the PWM generator of FIG. 2A according to an embodiment of the present invention.
FIG. 3E shows signals associated with the comparator and PWM generator of FIG. 2A without an offset cancellation circuit.
Fig. 4A shows a block diagram of a dc converter with output voltage offset cancellation according to a second embodiment of the present invention.
Fig. 4B shows a circuit diagram of a part of the block of fig. 4A.
FIG. 5A is a block diagram of the digital fixed on-time controller of FIG. 4A according to a second embodiment of the present invention.
Fig. 5B shows a detailed block diagram of a portion of the blocks of fig. 5A.
[ description of main element symbols ]
100: the dc converter 200: DC converter
11: the switching circuit 111: power supply
12: energy storage circuit 13: analog-to-digital converter
13A: the first analog-to-digital converter 13B: a second analog-to-digital converter
14: the driver 15: digital fixed on-time controller
151: current sensing circuit 1511: high-pass filter
1512: low-pass filter 1513: first adder
152: offset cancellation circuit 1521: wave trough detector
1522: the second adder 1523: third adder
153: the comparator 154: pulse width modulation generator
And Mp: first switching device Mn: second switching device
L: inductor RL: effective series resistor
C: capacitor RC: effective series resistor
Vx: switching Voltage/switching node Vx [ n ]: digital switching voltage
Vo: output Voltage/output node Vo [ n ]: digital output voltage
S: switching control signal Vin: input voltage
IL: inductor current Vref: reference signal
Vvalley: trough voltage RLIL(ripple): ripple voltage
RLIL(DC)+ Vo: direct voltage
Detailed Description
Fig. 1A shows a block diagram of a direct current (DC-to-DC) converter 100 with output voltage offset cancellation according to a first embodiment of the present invention, and fig. 1B shows a circuit diagram of a portion of the blocks of fig. 1A.
In the present embodiment, the dc converter 100 may include a switching circuit 11 for generating a switching voltage Vx. The switching circuit 11 may include a first switching device Mp (e.g., a P-type metal oxide semiconductor (PMOS) transistor) and a second switching device Mn (e.g., an N-type metal oxide semiconductor (NMOS) transistor) connected in series between the power source 111 and ground. The power supply 111 provides an input voltage Vin. The switching voltage Vx is located at a switching node Vx between the first switching device Mp and the second switching device Mn. The first switching device Mp is electrically connected between the power source 111 and the switching node Vx, and the second switching device Mn is electrically connected between the switching node Vx and ground. In this specification, the same symbol (e.g., Vx) may be used to denote a node and the voltage of the node.
The dc converter 100 of the present embodiment may include an energy storage circuit 12 receiving a switching voltage Vx to generate a regulated output voltage Vo for providing to a load. Wherein the energy storage circuit 12 may comprise an inductor L and an effective series resistor RLConnected in series between the switching node Vx and the output node Vo; and a capacitor C and an effective series resistor RCAnd is connected in series between the output node Vo and ground.
The dc converter 100 of the present embodiment may include an analog-to-digital converter (ADC)13 for generating an equivalent digital output voltage Vo [ n ] of the (analog) output voltage Vo. According to one of the features of the present embodiment, the dc converter 100 may include a driver 14 (e.g., an amplifier) generating a driving signal to drive the switching circuit 11. The driver 14 generates a driving signal to drive the first switching device Mp, and generates an inverted driving signal to drive the second switching device Mn.
According to one feature of this embodiment, the DC converter 100 may include a digital constant on-time (DCOT) controller 15 that receives the digital output voltage Vo [ n ]]To generate a switching control signal S which is fed to the driver 14. In thatIn this embodiment, the digital fixed on-time controller 15 stores the energy (e.g. the inductor current I flowing through the inductor L) according to the stored energy of the energy storage circuit 12L) To generate a fixed on-time (COT) switching control signal.
Fig. 2A shows a block diagram of the digital fixed on-time controller 15 of fig. 1A according to a first embodiment of the present invention, and fig. 2B shows a detailed block diagram of a part of the blocks of fig. 2A.
In the present embodiment, the digital fixed on-time controller 15 may comprise a (digital) current sensing circuit 151, which senses the stored energy (e.g. the inductor current I) of the energy storage circuit 12L) To generate a sense voltage representative of the voltage across the effective series resistor RLThe voltage of (c). The current sensing circuit 151 may comprise a (digital) High Pass Filter (HPF)1511 and a (digital) Low Pass Filter (LPF)1512 for receiving the digital output voltage Vo [ n ]]And a switching control signal S. The digital fixed on-time controller 15 may include a first adder 1513 that adds the output of a High Pass Filter (HPF)1511 to the output of a Low Pass Filter (LPF)1512 to generate a sense voltage. Fig. 2C illustrates an equivalent analog architecture of the current sensing circuit 151 of fig. 2B. For details of the design of the High Pass Filter (HPF)1511 and the Low Pass Filter (LPF)1512, reference is made to a single crystal Digital Ripple-Based Adaptive-Off-Time DC-DC Converter With Digital Inductor Current sensing (a single Digital Ripple-Based Adaptive-Off-Time DC-DC Converter With Digital Inductor Current Sensor) proposed by m.p. chan et al, which is published in the institute of electrical and electronics engineers Solid State Circuits (IEEE Journal of Solid-State Circuits), volume 49, No. 8, pages 1837-1847, and october 2014, the contents of which are considered as part of this specification.
The digital constant on-time controller 15 of the present embodiment may comprise an offset cancellation (offset cancellation) circuit 152, which receives the sensing voltage (of the current sensing circuit 151) and the digital output voltage Vo [ n ]]The offset-removed sensing voltage is generated according to the switching control signal S. Offset cancellation circuit 152 may include a valley detector 1521 that detects a valley (or minimum) value of the sensed voltage (from current sensing circuit 151). FIG. 3A illustrates spanning an effective series connectionResistor R-LAnd displays the valley voltage Vvalley. The sensing voltage may comprise a ripple voltage RLIL(ripple)At its center, the average voltage is RLIL(DC)+Vo。
The offset cancellation circuit 152 of the present embodiment may include a second adder 1522 that subtracts the valley voltage V from the sense voltage (from the current sensing circuit 151)valleyTo generate a zero-valley (zero-valley) sense voltage. FIG. 3B illustrates a waveform of zero valley sensing voltage with an average voltage of 0.5R at its centerLIL(ripple)。
The offset cancellation circuit 152 of the present embodiment may further include a third adder 1523 for adding the zero valley sensing voltage and the digital output voltage Vo [ n ]]Adding to generate an offset-removed sense voltage. FIG. 3C illustrates a waveform of the offset-removed sensing voltage, the average voltage of the center of which is 0.5RLIL(ripple)+Vo。
In the present embodiment, the digital fixed on-time controller 15 may include a comparator 153 that compares the offset-removed sensing voltage with the reference signal Vref. A first input node (e.g., a positive (+) input node) of the comparator 153 receives the offset-removed sensing voltage (from the offset canceling circuit 152), and a second input node (e.g., a negative (-) input node) receives the reference signal Vref.
The digital fixed on-time controller 15 of the present embodiment may include a Pulse Width Modulation (PWM) generator 154 for generating the switching control signal S according to the comparison result of the comparator 153. Fig. 3D shows signals related to the comparator 153 and the pwm generator 154 of fig. 2A according to an embodiment of the invention. The pwm generator 154 generates a pulse having a predetermined on-time (of the first switching device Mp) whenever the offset-removed sensing voltage is smaller than the reference signal Vref. In detail, when the offset removal sensing voltage is smaller than the reference signal Vref, the switching control signal S is activated (e.g., S is equal to 1), and the first switching device Mp is turned on (for a predetermined period) but the second switching device Mn is turned off. On the other hand, when the switching control signal S is inactive (e.g., S is equal to 0), the first switching device Mp is turned off but the second switching device Mn is turned on. To facilitate comparisonFig. 3E shows signals associated with the comparator 153 and the pwm generator 154 of fig. 2A without using the offset cancellation circuit 152 (i.e., the sensing voltage is directly coupled to the comparator 153). Notably, the operations associated with FIG. 3E are due to RLIL(DC)This causes an offset error of the output voltage. In contrast, since the offset cancellation circuit 152 is used in the present embodiment, the sensing voltage is shifted to 0.5R by shifting the DC level of the sensing voltageLIL(ripple)+ Vo (as shown in fig. 3A to 3C), so that output voltage offset can be avoided.
Fig. 4A shows a block diagram of a direct current (DC-to-DC) converter 200 with output voltage offset cancellation according to a second embodiment of the present invention, and fig. 4B shows a circuit diagram of a portion of the blocks of fig. 4A. Fig. 5A shows a block diagram of the digital fixed on-time controller 15 of fig. 4A according to a second embodiment of the present invention, and fig. 5B shows a detailed block diagram of a part of the blocks of fig. 5A.
The second embodiment is similar to the first embodiment, and the differences will be explained below. In the second embodiment, the first analog-to-digital converter 13A generates an equivalent digital output voltage Vo [ n ] of the (analog) output voltage Vo, and the second analog-to-digital converter 13B generates an equivalent digital switching voltage Vx [ n ] of the (analog) switching voltage Vx. Thereby, the digital fixed on-time controller 15 of the second embodiment generates the switching control signal S according to the digital output voltage Vo [ n ] and the digital switching voltage Vx [ n ], but only according to the digital output voltage Vo [ n ] in the first embodiment. The Low Pass Filter (LPF)1512 and the valley detector 1521 of the offset cancellation circuit 152 of the current sensing circuit 151 of the second embodiment are implemented according to the digital switching voltage Vx [ n ], but are implemented according to the switching control signal S in the first embodiment.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (13)
1. A digital fixed on-time controller for a dc converter, comprising:
a current sensing circuit for sensing the stored energy of the DC converter to generate a sensing voltage;
an offset cancellation circuit, which receives the sensing voltage and generates an offset removal sensing voltage according to the valley voltage of the sensing voltage;
a comparator that compares the offset-removed sensing voltage with a reference signal; and
a PWM generator for generating a switching control signal according to a comparison result of the comparator;
wherein the reference signal is independent of the sense voltage generated by the current sense circuit.
2. The digital fixed on-time controller of claim 1, wherein the current sensing circuit comprises:
a high-pass filter and a low-pass filter for respectively receiving the digital output voltage and the switching control signal; and
the first adder adds the output of the high-pass filter and the output of the low-pass filter to generate the sensing voltage.
3. The digital fixed on-time controller of claim 2, wherein the offset cancellation circuit comprises:
a valley detector for receiving the switching control signal and detecting the valley voltage;
a second adder that subtracts the valley voltage from the sensing voltage to generate a zero valley sensing voltage; and
a third adder that adds the valley zero sense voltage to the digital output voltage to generate the offset-removed sense voltage.
4. The digital fixed on-time controller of claim 1, wherein the current sensing circuit comprises:
a high pass filter and a low pass filter for receiving the digital output voltage and the digital switching voltage, respectively; and
the first adder adds the output of the high-pass filter and the output of the low-pass filter to generate the sensing voltage.
5. The digital fixed on-time controller of claim 4, wherein the offset cancellation circuit comprises:
a valley detector for receiving the digital switching voltage to detect the valley voltage;
a second adder that subtracts the valley voltage from the sensing voltage to generate a zero valley sensing voltage; and
a third adder that adds the valley zero sense voltage to the digital output voltage to generate the offset-removed sense voltage.
6. A dc converter, comprising:
a switching circuit for generating a switching voltage;
an energy storage circuit receiving the switching voltage to generate an output voltage;
a first analog-to-digital converter for generating an equivalent digital output voltage of the output voltage;
a digital fixed on-time controller receiving the digital output voltage to generate a switching control signal; and
a driver for generating at least one driving signal to drive the switching circuit according to the switching control signal;
wherein the digital fixed on-time controller comprises:
a current sensing circuit that senses stored energy of the energy storage circuit to generate a sensing voltage;
an offset cancellation circuit, which receives the sensing voltage and generates an offset removal sensing voltage according to the valley voltage of the sensing voltage;
a comparator that compares the offset-removed sensing voltage with a reference signal; and
a PWM generator for generating a switching control signal according to a comparison result of the comparator;
wherein the reference signal is independent of the sense voltage generated by the current sense circuit.
7. The DC converter of claim 6, wherein the current sensing circuit comprises:
a high-pass filter and a low-pass filter for receiving the digital output voltage and the switching control signal respectively; and
the first adder adds the output of the high-pass filter and the output of the low-pass filter to generate the sensing voltage.
8. The DC converter of claim 7, wherein the offset cancellation circuit comprises:
a valley detector for receiving the switching control signal and detecting the valley voltage;
a second adder that subtracts the valley voltage from the sensing voltage to generate a zero valley sensing voltage; and
a third adder that adds the valley zero sense voltage to the digital output voltage to generate the offset-removed sense voltage.
9. The DC converter of claim 6, further comprising a second analog-to-digital converter for generating an equivalent digital switching voltage of the switching voltage, wherein the current sensing circuit comprises:
a high-pass filter and a low-pass filter for receiving the digital output voltage and the digital switching voltage, respectively; and
the first adder adds the output of the high-pass filter and the output of the low-pass filter to generate the sensing voltage.
10. The dc converter of claim 9, wherein the offset cancellation circuit comprises:
a valley detector for receiving the digital switching voltage to detect the valley voltage;
a second adder that subtracts the valley voltage from the sensing voltage to generate a zero valley sensing voltage; and
a third adder that adds the valley zero sense voltage to the digital output voltage to generate the offset-removed sense voltage.
11. The dc converter of claim 6, wherein: the switching circuit comprises a first switching device and a second switching device which are connected in series between a power supply and the ground, and the switching voltage is generated at a switching node between the first switching device and the second switching device.
12. The dc converter of claim 11, wherein: wherein the first switching device comprises a PMOS transistor, the second switching device comprises an NMOS transistor, the first switching device is electrically connected between the power supply and the switching node, and the second switching device is electrically connected between the switching node and ground.
13. The dc converter of claim 11, wherein: wherein the energy storage circuit comprises an inductor and an effective series resistor connected in series between the switching node and an output node, the output node providing the output voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811297217.8A CN111130346B (en) | 2018-11-01 | 2018-11-01 | DC converter and digital fixed on-time controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811297217.8A CN111130346B (en) | 2018-11-01 | 2018-11-01 | DC converter and digital fixed on-time controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111130346A CN111130346A (en) | 2020-05-08 |
| CN111130346B true CN111130346B (en) | 2020-11-20 |
Family
ID=70494945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811297217.8A Active CN111130346B (en) | 2018-11-01 | 2018-11-01 | DC converter and digital fixed on-time controller |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111130346B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1623269A (en) * | 2002-01-29 | 2005-06-01 | 英特赛尔美国股份有限公司 | Synthetic ripple regulator |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7800352B2 (en) * | 2007-05-16 | 2010-09-21 | Intersil Americas Inc. | Controller having comp node voltage shift cancellation for improved discontinuous conduction mode (DCM) regulator performance and related methods |
| TWI411213B (en) * | 2011-02-24 | 2013-10-01 | Richtek Technology Corp | Control circuit and method for a ripple regulator |
| US9201438B2 (en) * | 2012-11-15 | 2015-12-01 | Micrel, Inc. | Buck DC-DC converter with accuracy enhancement |
| CN103151926B (en) * | 2013-04-08 | 2015-12-09 | 成都芯源***有限公司 | Load regulation compensation circuit and switch type voltage conversion circuit |
| CN104135151B (en) * | 2013-05-02 | 2016-12-28 | 登丰微电子股份有限公司 | DC-DC switching controller |
| TWI595735B (en) * | 2015-03-24 | 2017-08-11 | 立錡科技股份有限公司 | Current regulator circuit capable of reducing current ripple and method of reducing current ripple |
| US9941792B2 (en) * | 2016-04-01 | 2018-04-10 | Nxp B.V. | DC offset correction for inductor current ripple based, constant-on-time DC-DC converters |
| CN107659151B (en) * | 2017-04-24 | 2023-07-07 | 深圳市华芯邦科技有限公司 | Buck load current detection circuit and method without external sampling resistor |
-
2018
- 2018-11-01 CN CN201811297217.8A patent/CN111130346B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1623269A (en) * | 2002-01-29 | 2005-06-01 | 英特赛尔美国股份有限公司 | Synthetic ripple regulator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111130346A (en) | 2020-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3361615B1 (en) | Switching regulator and control device therefor | |
| TWI496402B (en) | Current-mode buck converter and electronic system using the same | |
| JP5788748B2 (en) | DC / DC converter control circuit and DC-DC converter | |
| JP6285235B2 (en) | Control circuit for digital control power supply circuit, control method, digital control power supply circuit using the same, electronic device and base station | |
| JP5556404B2 (en) | Switching power supply | |
| JP4312000B2 (en) | Buck-boost DC-DC converter | |
| US10581325B1 (en) | Power converter with slope compensation | |
| JP5808990B2 (en) | DC / DC converter control circuit and DC-DC converter | |
| US20090153114A1 (en) | DC-DC converters with transient response control | |
| US8502516B2 (en) | Voltage adjustment module and power supply device | |
| US20130187624A1 (en) | Semiconductor integrated circuit device and dc-dc converter | |
| JP2012039710A (en) | Switching power supply device | |
| CN109643957B (en) | Switching power supply device and semiconductor device | |
| JP2007174744A (en) | Charge pump circuit and power supply device | |
| US9722587B2 (en) | Power supply circuit | |
| EP3311477B1 (en) | Power supplier, power supply system, and voltage adjustment method | |
| JP5029056B2 (en) | Detection circuit and power supply system | |
| US8174249B2 (en) | Voltage boosting/lowering circuit | |
| WO2009035013A1 (en) | Constant current supply type of switching regulator | |
| US10291121B1 (en) | DC-to-DC converter and a digital constant on-time controller thereof | |
| US10153695B2 (en) | Feedback scheme for non-isolated power supply | |
| US20130328540A1 (en) | Buck switching regulator and control circuit thereof | |
| CN111130346B (en) | DC converter and digital fixed on-time controller | |
| TWI689163B (en) | Dc-to-dc converter and a digital constant on-time controller thereof | |
| US10811966B1 (en) | Digital constant on-time controller adaptable to a DC-to-DC converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |