CN111128915A - Wafer level packaging chip and method - Google Patents

Wafer level packaging chip and method Download PDF

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Publication number
CN111128915A
CN111128915A CN201911367662.1A CN201911367662A CN111128915A CN 111128915 A CN111128915 A CN 111128915A CN 201911367662 A CN201911367662 A CN 201911367662A CN 111128915 A CN111128915 A CN 111128915A
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wafer
layer
silicon substrate
tsv hole
level packaging
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杨佩佩
金科
李永智
赖芳奇
吕军
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Suzhou Keyang Photoelectric Science & Technology Co ltd
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Suzhou Keyang Photoelectric Science & Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to the technical field of wafer level packaging, in particular to a wafer level packaging chip and a method. The substrate is thinned, and the metal in the TSV hole is connected with the back metal of the silicon substrate, so that wafer-level packaging of a small-size ultrathin chip can be realized, and the heat dissipation requirement is met; the packaging resistance of the grounding circuit is reduced, the inductance effect is reduced, the chip performance is improved, the number of connecting wires of grounding welding pads is reduced, the use of noble metal is reduced, the packaging area is reduced, and the cost is effectively reduced; the seed layer and the metal back gold layer are manufactured on the patterned adhesion promotion layer, so that the problem of insufficient binding force such as bubbling and layering can be avoided, the reliability is improved, and the heat dissipation problem is solved.

Description

Wafer level packaging chip and method
Technical Field
The invention relates to the technical field of wafer level packaging, in particular to a wafer level packaging chip and a method.
Background
When the existing chip is packaged, the back surface of the chip is provided with a plastic packaging material layer, so that the chip is not favorable for heat dissipation and the thickness after packaging is increased, meanwhile, the ground welding pads and the signal welding pads are connected in an electrical performance manner by a gold wire (wire bonding) method, the number of common ground welding connecting wires is large, a large amount of noble metals are consumed, a larger area of ground welding pads are required to be arranged on a packaging substrate, the packaging area is increased, and the cost is high. Meanwhile, most of the back gold material is copper, so that oxidation is easy to occur, time limitation and environmental limitation are provided for subsequent processing, and once oxidation is performed, the reliability of the product is seriously influenced.
Disclosure of Invention
The invention aims to provide a wafer level packaging chip and a method, which can realize wafer level packaging of small-size ultrathin chips, reduce the number of connecting wires of grounding welding pads, effectively reduce the cost and improve the reliability.
In order to solve the technical problems, the technical scheme adopted by the invention for solving the technical problems is as follows:
a wafer level packaging method comprises the following specific steps:
s1: manufacturing an integrated circuit on a silicon substrate to form a wafer, temporarily bonding the wafer and glass together, and thinning the silicon substrate;
s2: arranging an adhesion promoting layer with a graphical structure on a wafer silicon substrate, and exposing part of the surface of the wafer;
s3: forming a TSV hole in the silicon substrate, and enabling the bottom of the TSV hole to partially or completely leak out of a grounding welding pad on the integrated circuit;
s4, manufacturing a seed layer on the back of the wafer and the inner wall of the TSV hole, and depositing a metal back gold layer on the seed layer;
and S5, removing the bonding between the wafer and the glass to obtain a packaged wafer, and cutting the packaged wafer into single chips.
Preferably, in step S1, the wafer and the glass are temporarily bonded by the temporary bonding material.
Preferably, in step S1, the wafer is thinned to a thickness of 50-200 μm by one or more of a mechanical polishing method, a mechanochemical polishing method, a plasma dry etching method or a wet etching method.
Preferably, in step S2, the adhesion promoting layer is made of any one of an organic material and a silicon dioxide material, and the adhesion promoting layer provided on the wafer is formed in a square, circular or irregular polygonal shape so as to expose a part of the surface of the wafer.
Preferably, step S3 includes:
s31: removing the wafer above the grounding welding pad to form a TSV hole, wherein the TSV hole is in a trapezoid shape, and the width of an upper opening of the TSV hole is larger than that of a lower opening;
s32: and removing the inner insulating layer above the grounding welding pad, so that the bottom of the TSV hole is partially or completely exposed out of the grounding welding pad.
Preferably, step S4 specifically includes:
s41: depositing a seed layer on the back of the wafer and the inner wall of the TSV hole in a magnetron sputtering mode, wherein the thickness of the seed layer is 0.05-3 mu m;
s42: and depositing conductive metal on the surface of the seed layer by adopting an electroplating mode or a chemical plating mode to form a back gold layer.
The invention also comprises a wafer level packaging chip which comprises a wafer, wherein the wafer comprises a silicon substrate and an integrated circuit, the integrated circuit is arranged on the silicon substrate, the integrated circuit comprises an internal insulating layer, a grounding welding pad and a signal welding pad, the internal insulating layer is arranged on the silicon substrate, the grounding welding pad and the signal welding pad are arranged on the internal insulating layer, an adhesion increasing layer is arranged on the silicon substrate, a TSV hole is formed in the wafer, the grounding welding pad is partially or completely leaked from the bottom of the TSV hole, seed layers are arranged on the back surface of the silicon substrate and the inner wall of the TSV hole, and a back gold layer is arranged on the seed layers.
Preferably, the thickness of the silicon substrate is 50-200 μm; the thickness of the tackifying layer is 0.14-20 μm.
Preferably, the shape of the adhesion promotion layer is square, round or irregular polygon.
Preferably, the TSV hole is in a trapezoid structure, the width of the upper opening is greater than that of the lower opening, and the shape of the upper opening can be circular, square or polygonal.
The invention has the beneficial effects that:
the substrate is thinned, and the metal in the TSV hole is connected with the back metal of the silicon substrate, so that wafer-level packaging of a small-size ultrathin chip can be realized, and the heat dissipation requirement is met; the packaging resistance of the grounding circuit is reduced, the inductance effect is reduced, the chip performance is improved, the number of connecting wires of grounding welding pads is reduced, the use of noble metal is reduced, the packaging area is reduced, and the cost is effectively reduced; the seed layer and the metal back gold layer are manufactured on the patterned adhesion promotion layer, so that the problem of insufficient binding force such as bubbling and layering can be avoided, the reliability is improved, and the heat dissipation problem is solved.
Drawings
Fig. 1-10 are schematic flow charts of a wafer level packaging method according to the present invention.
Fig. 11 is a schematic view of a wafer level package chip structure according to the present invention.
The reference numbers in the figures illustrate: 101. glass; 102. a wafer; 102-1, a silicon substrate; 102-2, an inner insulating layer; 102-3, a ground pad; 102-4, signal pads; 103. a temporary bonding material; 104. an adhesion promoting layer; 105. TSV holes; 106. a seed layer; 107. a back gold layer; 111. a single chip;
Detailed Description
The present invention is further described below in conjunction with the following figures and specific examples so that those skilled in the art may better understand the present invention and practice it, but the examples are not intended to limit the present invention.
Referring to fig. 1-10, a wafer level packaging method includes the following specific steps:
s1: manufacturing an integrated circuit on a silicon substrate 102-1 to form a wafer 102, temporarily bonding the wafer 102 and glass 101 together, and thinning the silicon substrate 102-1;
s2: arranging an adhesion promoting layer 104 with a graphical structure on a wafer silicon substrate, and exposing a part of the surface of the wafer 102;
s3: forming a TSV hole 105 in the silicon substrate 102-1, and enabling the bottom of the TSV hole 105 to partially or completely leak out of a grounding welding pad 102-3 on the integrated circuit;
s4, manufacturing a seed layer 106 on the back of the wafer 102 and the inner wall of the TSV hole 105, and depositing a metal back gold layer 107 on the seed layer 106;
s5, the wafer 102 and the glass 101 are removed from the bonding to obtain a packaged wafer 102, and the packaged wafer 102 is cut into individual chips 111.
Specifically, the wafer 102 includes a silicon substrate 102-1 and an integrated circuit, the integrated circuit is disposed on the silicon substrate 102-1, the integrated circuit includes an internal insulating layer 102-2, a ground pad 102-3, and a signal pad 102-4, the internal insulating layer 102-2 is disposed on the silicon substrate 102-1, the ground pad 102-3 and the signal pad 102-4 are disposed on the internal insulating layer 102-2, an adhesion-promoting layer 104 is disposed on the silicon substrate 102-1, a TSV hole 105 is disposed on the wafer 102, a part or all of the bottom of the TSV hole 105 leaks out of the ground pad 102-3, a seed layer 106 is disposed on the back surface of the silicon substrate 102-1 and on the inner wall of the TSV hole 105, and a back gold layer 107 is disposed on the seed layer 106.
Thinning treatment is carried out on the substrate, metal in the TSV hole 105 and the back gold of the silicon substrate 102-1 are connected together, wafer 102-level packaging of a small-size ultrathin chip can be achieved, and meanwhile the heat dissipation requirement is met; the packaging resistance of the grounding circuit is reduced, the inductance effect is reduced, the chip performance is improved, the number of connecting wires of the grounding welding pads 102-3 is reduced, the use of noble metal is reduced, the packaging area is reduced, and the cost is effectively reduced; the seed layer and the metal back gold layer are manufactured on the patterned adhesion promotion layer, so that the problem of insufficient binding force such as bubbling and layering can be avoided, the reliability is improved, and the heat dissipation problem is solved.
In step S1, the wafer 102 and the glass 101 are temporarily bonded by the temporary bonding material 103.
In step S1, the wafer 102 is thinned to a thickness of 50-200 μm by one or more of a mechanical polishing method, a mechanochemical polishing method, a plasma dry etching method, or a wet etching method.
The size of the glass 101 is the same as that of the wafer 102, the thickness of the glass 101 is 0.3-1.5mm, the temporary bonding function is that the wafer 102 is thinned to be within 50-200 μm by the subsequent process, the glass 101 plays a supporting role, and the wafer 102 is prevented from being broken when the TSV 105 and the back metal layer 107 are processed subsequently.
The wafer 102 is thinned by one or more of a mechanical grinding mode, a mechanical chemical grinding and polishing mode, a plasma dry etching mode or a wet etching mode, so that the packaged chip can be ultrathin, specifically, the invention can adopt a diamond grinding wheel to carry out mechanical grinding and processing mode, or a mechanical chemical grinding and polishing mode, or a plasma dry etching mode, or a fluorine-containing liquid medicine to carry out wet etching mode, and the thickness of the invention can be adjusted within the range of 50-200 mu m or 20-350 mu m according to the specific application requirement.
According to the invention, the diamond grinding wheel is preferably adopted to mechanically grind the wafer 102, then the plasma dry etching method is used for removing the micro-damage layer on the surface of the wafer 102, the mechanical grinding processing is fast, but stress and the micro-damage layer are generated on the silicon surface, then the plasma dry etching method is used for removing the micro-damage layer, the surface stress is released, and the warping problem of the wafer 102 is solved.
In step S2, the adhesion promoting layer 104 is made of any one of an organic material or a silicon dioxide material, and the adhesion promoting layer 104 disposed on the wafer 102 is formed to have a square, circular or irregular polygon shape for exposing a portion of the surface of the wafer 102.
The adhesion promoting layer 104 is a patterned structure, i.e., there is adhesion promoting layer 104 in a part of the region, and there is no adhesion promoting layer 104 in a part of the region.
When the adhesion promoting layer 104 is made of organic material, the adhesion promoting layer 104 is coated by a semiconductor, and the thickness of the adhesion promoting layer 104 is controlled to be 0.2-20 μm; when the adhesive layer is made of silicon dioxide material, a layer of silicon dioxide material with the thickness of 0.1-5 μm is manufactured on the silicon substrate 102-1 by adopting physical vapor chemical deposition (PECVD).
The preferred scheme of the present invention is that the adhesion promoting layer 104 is an organic material, and the organic material is required to have characteristics of low thermal resistance, stable heat resistance, stable chemical resistance, low coefficient of thermal expansion of the material, etc.
The patterned pattern may be square, circular, irregular polygonal, or other irregular patterns, but it is necessary that a portion of the wafer 102 has silicon exposed from the silicon substrate 102-1.
The patterned structure may be formed by semiconductor lithography, which includes first applying a layer of photoresist to the adhesion-promoting layer 104, patterning the photoresist after photolithography, and finally removing the adhesion-promoting layer 104 by dry etching. Depending on the material properties of the adhesion promoting layer 104, the present invention may be implemented with patterned structures or laser processing methods.
Step S3 includes:
s31: removing the wafer 102 above the grounding welding pad 102-3 to form a TSV hole 105, wherein the TSV hole 105 is in a trapezoid shape, and the width of an upper opening of the TSV hole 105 is larger than that of a lower opening;
specifically, the silicon substrate 102-1 above the ground pad 102-3 is selectively removed to expose the internal insulating layer 102-2 on the ground pad 102-3, and the silicon substrate on the signal pad 102-4 and other positions is not removed; the TSV profile of the TSV hole 105 is in a trapezoid shape in a cross section view, the width of the upper opening is larger than that of the lower opening, the shape of the upper opening of the TSV hole 105 can be circular, square or polygonal in a top view, and the implementation of a subsequent back-gold process can be facilitated by the adoption of the trapezoid-shaped TSV hole 105.
Removing the silicon substrate 102-1 above the grounding welding PAD 102-3, etching away redundant silicon by adopting a photoetching process and a dry etching process, and leaking a bottom PAD; when the photoetching process is adopted, firstly, photoetching materials with photosensitive characteristics are covered on the silicon surface of the silicon substrate 102-1, then a mask plate with a special pattern (the shape of an upper opening hole) is used for carrying out photosensitive treatment under light with a specific wavelength, then a chemical agent is used for developing to manufacture a photoresist pattern, and the part which is not covered by the photoresist can be etched and reacted by active fluorine ions to be removed, so that the aim of removing silicon is fulfilled.
The invention can also adopt a wet etching process to replace a dry etching process, and after the silicon etching is finished, the photoresist on the protective layer on the surface needs to be removed, and then the silicon surface of the silicon substrate 102-1 is cleaned.
S32: the inner insulating layer 102-2 above the ground pad 102-3 is removed such that the bottom of the TSV hole 105 partially or completely leaks out of the ground pad 102-3.
The inner insulating layer 102-2 is made of silicon dioxide or silicon nitride, the inner insulating layer 102-2 can be removed by etching the semiconductor dielectric layer, and the above process is also a plasma dry etching method, which uses special gas to react only with silicon dioxide or silicon nitride, and uses a silicon inert method to remove the reaction.
Step S4 specifically includes:
s41: depositing a seed layer 106 on the back of the wafer 102 and the inner wall of the TSV hole 105 in a magnetron sputtering mode, wherein the thickness of the seed layer 106 is 0.05-3 mu m;
the seed layer 106 serves two purposes, one to enhance the metal-to-substrate bond and one to provide for the subsequent deposition of a back gold layer 107. The seed layer 106 metal may be Ti/Cu, TiW/Cu, or Cr/Cu. The preferred metal of the seed layer 106 in the invention is an environment-friendly and low-cost Ti/Cu structure, wherein the thickness of Ti is 0.05-0.5um, the thickness of Cu is 0.5-3um, and the adjustment can be specifically carried out according to the actual depth of the TSV hole 105 and the angles of two side edges of the trapezoid.
S42: and depositing a conductive metal on the surface of the seed layer 106 by adopting an electroplating way or an electroless plating way to form a back gold layer 107.
The surface of the seed layer 106 preferred in the invention is deposited with copper, nickel and gold in sequence to form a back gold layer 107, wherein the thickness of copper is 2-20um, the thickness of nickel is 2-5um, and the thickness of gold is 0.05-1um, the conductive metal is metal with low connection resistance, the thicker the copper plating layer is, the better the conductive metal is, and the conductive metal can also be other metal or alloy material with excellent conductivity such as pd, Sn, Ag, etc. The preferable scheme of the embodiment is conductive metal copper, nickel and gold.
The back gold layer 107 is arranged on the seed layer 106, so that the problem that the titanium-nickel-silver back gold is easy to bubble and delaminate and the like is solved, the product is invalid, the problems that the back gold is not enough in binding force with the silicon substrate 102-1 and easy to bubble and delaminate are effectively solved by a warrior, the back gold material is corrosion-resistant and is not limited by the use environment and time, and the reliability is improved.
In step S5, because there are multiple temporary bonding methods, and each method corresponds to a different temporary bonding material 103, the detachment bonding between the wafer 102 and the glass 101 according to the present invention can be performed by any one of a laser method, a UV light method, a chemical method, a mechanical method, or a thermal slip movement method, and each detachment bonding method also corresponds to a corresponding temporary bonding method, and a preferred embodiment of the present invention is to adopt a laser detachment bonding method or a UV light detachment bonding method for detachment bonding between the wafer 102 and the glass 101.
The wafer 102 after wafer 102 level packaging is cut into individual chips 111, which may be processed by a metal blade or laser cutting method on the packaged wafer 102.
Referring to fig. 11, the present invention further includes a wafer 102 level package chip, including a wafer 102, where the wafer 102 includes a silicon substrate 102-1 and an integrated circuit, the integrated circuit is disposed on the silicon substrate 102-1, the integrated circuit includes an internal insulating layer 102-2, a ground pad 102-3, and a signal pad 102-4, the internal insulating layer 102-2 is disposed on the silicon substrate 102-1, the ground pad 102-3 and the signal pad 102-4 are disposed on the internal insulating layer 102-2, an adhesion promoting layer 104 is disposed on the silicon substrate 102-1, a TSV hole 105 is disposed on the wafer 102, a bottom of the TSV hole 105 partially or completely leaks out of the ground pad 102-3, a seed layer 106 is disposed on a back surface of the silicon substrate 102-1 and an inner wall of the TSV hole 105, a back gold layer 107 is disposed on the seed layer 106.
The wafer 102 level back gold packaging structure with the TSV structure is small in size and good in heat dissipation.
The thickness of the silicon substrate 102-1 is 50-200 μm; the thickness of the adhesion promoting layer 104 is 0.14-20 μm.
The adhesion promotion layer 104 is square, round or irregular polygon.
The TSV hole 105 is in a trapezoid structure, the width of the upper opening of the TSV hole is larger than that of the lower opening of the TSV hole, and the shape of the upper opening of the TSV hole can be circular, square or polygonal, so that metal deposition on the bottom and the side wall of the TSV hole 105(TSV hole) is facilitated.
All the ground pads 102-3 on the chip are connected together through the metal in the TSV holes 105 (TSVs) and the back gold on the back surface, and then connected to the ground pads 102-3 on the substrate through the conductive adhesive, which has the following advantages:
1. the packaging resistance is small, the influence of inductance is low, large current can be resisted, and the product performance is favorably improved.
2. The number of the ground pads 102-3 on the package substrate can be reduced, and the package area can be reduced.
3. The grounding welding pad 102-3 does not need to be provided with a gold wire, and the electrical connection is directly connected to the substrate grounding welding pad 102-3 through TSV, back gold and conductive adhesive, so that the cost is low.
4. The back gold is a structure of titanium, copper, nickel and gold, and the whole surface is covered by the back nickel and gold, so the back gold layer 107 is very stable, resistant to environmental corrosion and high in reliability.
5. In general, the thicker the back gold layer 107 is, the greater the stress is, and the more likely the problem of delamination of the back gold layer 107 occurs. According to the scheme, the adhesion promotion layer 104 with a patterned structure is arranged between the back gold layer 107 and the silicon substrate 102-1, so that the bonding force of the back gold can be enhanced. Because of the patterned structure, part of the back gold is directly contacted with the silicon, and the heat dissipation requirement is not influenced.
6. The processing method for the set of wafers 102 uses the conventional semiconductor technology, is mature and stable, and is more suitable for batch production.
The above-mentioned embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. The equivalent substitution or change made by the technical personnel in the technical field on the basis of the invention is all within the protection scope of the invention. The protection scope of the invention is subject to the claims.

Claims (10)

1. A wafer level packaging method is characterized by comprising the following specific steps:
s1: manufacturing an integrated circuit on a silicon substrate to form a wafer, temporarily bonding the wafer and glass together, and thinning the silicon substrate;
s2: arranging an adhesion promoting layer with a graphical structure on a wafer silicon substrate, and exposing part of the surface of the wafer;
s3: forming a TSV hole in the silicon substrate, and enabling the bottom of the TSV hole to partially or completely leak out of a grounding welding pad on the integrated circuit;
s4, manufacturing a seed layer on the back of the wafer and the inner wall of the TSV hole, and depositing a metal back gold layer on the seed layer;
and S5, removing the bonding between the wafer and the glass to obtain a packaged wafer, and cutting the packaged wafer into single chips.
2. The wafer-level packaging method of claim 1, wherein in step S1, the wafer and the glass are temporarily bonded by a temporary bonding material.
3. The wafer-level packaging method of claim 1, wherein in step S1, the wafer is thinned to a thickness of 50-200 μm by one or more of mechanical grinding, mechanical chemical grinding and polishing, plasma dry etching or wet etching.
4. The wafer level packaging method of claim 1, wherein in step S2, the adhesion promoting layer is made of any one of an organic material or a silicon dioxide material, and the adhesion promoting layer disposed on the wafer is shaped into a square, a circle or an irregular polygon to expose a portion of the wafer surface.
5. The wafer-level packaging method of claim 1, wherein the step S3 includes:
s31: removing the wafer above the grounding welding pad to form a TSV hole, wherein the TSV hole is in a trapezoid shape, and the width of an upper opening of the TSV hole is larger than that of a lower opening;
s32: and removing the inner insulating layer above the grounding welding pad, so that the bottom of the TSV hole is partially or completely exposed out of the grounding welding pad.
6. The wafer-level packaging method of claim 1, wherein the step S4 specifically includes:
s41: depositing a seed layer on the back of the wafer and the inner wall of the TSV hole in a magnetron sputtering mode, wherein the thickness of the seed layer is 0.05-3 mu m;
s42: and depositing conductive metal on the surface of the seed layer by adopting an electroplating mode or a chemical plating mode to form a back gold layer.
7. The utility model provides a wafer level encapsulation chip, its characterized in that, includes the wafer, the wafer includes silicon substrate and integrated circuit, integrated circuit sets up on the silicon substrate, integrated circuit includes internal insulation layer, ground pad, signal weld pad, internal insulation layer sets up on the silicon substrate, ground pad, signal weld pad set up on the internal insulation layer, be provided with the adhesion promotion layer on the silicon substrate, be provided with the TSV hole on the wafer, the ground pad is leaked to TSV hole bottom part or whole, be provided with the seed layer on the silicon substrate back and the TSV downthehole wall, be provided with the back of the body gold layer on the seed layer.
8. The wafer level package chip of claim 7, wherein the silicon substrate has a thickness of 50-200 μ ι η; the thickness of the tackifying layer is 0.14-20 μm.
9. The wafer level package chip of claim 7, wherein the adhesion promoting layer has a shape of a square, a circle, or an irregular polygon.
10. The wafer level package chip as claimed in claim 7, wherein the TSV has a trapezoid structure, the width of the upper opening is larger than that of the lower opening, and the shape of the upper opening can be circular, square or polygonal.
CN201911367662.1A 2019-12-26 2019-12-26 Wafer level packaging chip and method Pending CN111128915A (en)

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CN112420802A (en) * 2020-12-02 2021-02-26 深圳市芯视佳半导体科技有限公司 Preparation method of silicon-based OLED micro-display convenient for heat dissipation
CN112626472A (en) * 2020-10-26 2021-04-09 威科赛乐微电子股份有限公司 Preparation method of VCSEL array chip P-surface connecting metal
CN113078055A (en) * 2021-03-23 2021-07-06 浙江集迈科微电子有限公司 Irregular wafer interconnection structure and interconnection process

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112626472A (en) * 2020-10-26 2021-04-09 威科赛乐微电子股份有限公司 Preparation method of VCSEL array chip P-surface connecting metal
CN112420802A (en) * 2020-12-02 2021-02-26 深圳市芯视佳半导体科技有限公司 Preparation method of silicon-based OLED micro-display convenient for heat dissipation
CN113078055A (en) * 2021-03-23 2021-07-06 浙江集迈科微电子有限公司 Irregular wafer interconnection structure and interconnection process
CN113078055B (en) * 2021-03-23 2024-04-23 浙江集迈科微电子有限公司 Irregular wafer interconnection structure and interconnection process

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