CN111128890A - 金属栅极形成方法及其形成结构 - Google Patents

金属栅极形成方法及其形成结构 Download PDF

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CN111128890A
CN111128890A CN201910816297.1A CN201910816297A CN111128890A CN 111128890 A CN111128890 A CN 111128890A CN 201910816297 A CN201910816297 A CN 201910816297A CN 111128890 A CN111128890 A CN 111128890A
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layer
trench
barrier layer
dielectric layer
work function
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李宜静
郑雅云
林浩宇
陈奕升
许家铭
柯志欣
幸仁·万
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明实施例涉及金属栅极形成方法及其形成结构。本揭露提供一种形成半导体结构的方法，其包括：提供衬底；在所述衬底中形成第一对源极/漏极区；在所述衬底上方放置层间介电质层，所述层间介电质层具有介于所述第一对源极/漏极区之间的第一沟槽；在所述第一沟槽中沉积介电质层；在所述介电质层上方沉积障壁层；从所述第一沟槽移除所述障壁层以曝光所述介电质层；在所述第一沟槽中的所述介电质层上方沉积功函数层；及在所述第一沟槽中的所述功函数层上方沉积导电层。

Description

金属栅极形成方法及其形成结构
技术领域
本发明实施例涉及金属栅极形成方法及其形成结构。
背景技术
随着技术演进，半导体装置的设计及制造鉴于其等更小尺寸、增强功能及更复杂电路而变得更加复杂。因此，不断需要修改制造半导体装置及其结构的方法以便改良装置稳健性并且降低成本及处理时间。据此，特定地关注于改良晶体管中的金属栅极(MG)电极的性能。一种形成MG电极的工艺称为后栅极工艺，而另一形成工艺称为先栅极工艺。后栅极工艺允许在形成栅极之后执行减少数目个后续工艺，包括高温操作。
发明内容
本发明的实施例涉及一种形成半导体结构的方法，其包含：提供衬底；在所述衬底中形成第一对源极/漏极区；在所述衬底上方放置层间介电质层，所述层间介电质层具有所述第一对源极/漏极区之间的第一沟槽；在所述第一沟槽中沉积介电质层；在所述介电质层上方沉积障壁层；从所述第一沟槽移除所述障壁层以曝光所述介电质层；在所述第一沟槽中的所述介电质层上方沉积功函数层；及在所述第一沟槽中的所述功函数层上方沉积导电层。
本发明的实施例涉及一种形成半导体结构的方法，其包含：在衬底中形成第一对源极/漏极区及第二对源极/漏极区；在所述衬底上方沉积层间介电质层，所述层间介电质层具有所述第一对源极/漏极区之间的第一沟槽及所述第二对源极/漏极区之间的第二沟槽；在所述第一沟槽及所述第二沟槽中分别沉积栅极介电质层；在所述第一沟槽及所述第二沟槽中的所述栅极介电质层上方沉积障壁层；在所述第一沟槽及所述第二沟槽中沉积功函数层；从所述第一沟槽减小所述障壁层的厚度，同时使障壁堆叠在所述第二沟槽中保持完整；及在所述第一沟槽及所述第二沟槽中的所述功函数层上方沉积导电层。
本发明的实施例涉及一种半导体结构，其包含：衬底；第一对源极/漏极区及第二对源极/漏极区，其等在所述衬底中；第一栅极堆叠及第二栅极堆叠，其等分别在所述衬底上方所述第一对源极/漏极区之间及所述第二对源极/漏极区之间，各栅极堆叠包含：栅极介电质层，其在所述衬底上方；功函数层，其由所述栅极介电质层环绕；及导电层，其由所述功函数层环绕，其中所述第一栅极堆叠进一步包括在所述栅极介电质层与所述功函数层之间不存在于所述第二栅极堆叠中的障壁层。
附图说明
当结合附图阅读时，从下文详细描述最好地理解本揭露的方面。应注意，根据标准行业实践，各种构件不一定按比例绘制。事实上，为清楚论述起见，可任意增大或减小各种构件的尺寸。
图1A到1T为展示根据一些实施例的制造半导体装置的方法的中间阶段的示意性剖面图。
图2为根据一些实施例的半导体装置的栅极堆叠的放大示意性剖面图。
图3为展示根据一些实施例的相对于栅极填充比的装置性能的示意图。
具体实施方式
下文揭露提供用于实施所提供标的物的不同特征的不同实施例或实例。下文描述组件及布置的特定实例以简化本揭露。当然，此等仅仅为实例且并非意欲于限制性。例如，在下文描述中第一构件形成于第二构件上方或上可包括其中第一构件及第二构件经形成为直接接触的实施例，且也可包括其中额外构件可经形成于第一构件与第二构件之间使得第一构件及第二构件可不直接接触的实施例。另外，本揭露可在各项实例中重复元件符号及/或字母。此重复出于简化及清楚的目的且本身不规定所论述的各项实施例及/或配置之间的关系。
此外，为便于描述，空间相对术语(例如“在…下面”、“在…下方”、“下”、“在…上方”、“上”及类似者)可在本文中用来描述一个元件或构件与另一(其它)元件或构件的关系，如图中所绘示。空间相对术语意欲于涵盖除图中所描绘的定向以外的使用或操作中装置的不同定向。设备可以其它方式定向(旋转90度或按其它定向)且据此可同样解释本文中所使用的空间相对描述词。
尽管阐述本揭露的广范畴的数值范围及参数为近似值，但尽可能精确地报告特定实施例中所阐述的数值。然而，任何数值固有地含有必定由各自测试测量中通常发现的偏差引起的特定误差。此外，如本文中所使用，术语“约”、“大体”或“大体上”通常意谓着在给定值或范围的10％、5％、1％或0.5％内。替代地，当所属领域的一般技术人员考量时，术语“约”、“大体”或“大体上”意谓着在均值的可接受标准误差内。除在操作/工作实例中以外或除非另有明确指定，否则本文中所揭露的所有数值范围、量、值及百分比(例如材料数量、持续时间、温度、操作条件、量比及类似者)应被理解为在所有情况下被术语“约”、“大体”或“大体上”修饰。据此，除非指示为相反，否则本揭露及随附发明权利要求书中所阐述的数值参数为可根据需要更改的近似值。至少，各数值参数至少应鉴于所报告有效数字的数目且通过应用普通舍入技术来解释。范围在本文中可被表示为从一个端点到另一端点或在两个端点之间。除非另有指定，否则本文中所揭露的所有范围包括端点。
本揭露大体上涉及半导体装置领域，且更特定而言涉及金属栅极的制造方法及所得半导体结构。
随着技术朝向先进节点及其它节点进展，形成金属栅极(MG)电极的任务变得更具挑战性。例如，归因于MG中沟槽的纵横比增加，填充能力降级。此外，愈来愈难以在N型晶体管与P型晶体管之间寻求各种MG电极的阈值电压的平衡。另外，例如在N型晶体管中对低阈值电压的更严格要求使MG电极的工艺控制更加复杂。再者，一些MG电极中的较高栅极电阻可为非所要的。现有方法已采用一或多个层(例如，障壁层)，以减小MG电极的泄漏电流来改良装置可靠性。然而，增厚障壁层可使功函数层的调谐更低效，从而导致更高阈值电压。增厚障壁层还将限制可用于MG电极的填充金属的空间，由此增加MG电极电阻。在一些实例中，障壁层可具有不均匀厚度，例如，底部角隅周围的障壁层的厚度大于底部中心处的障壁层的厚度。可能导致MG电极的性能降低。
在本揭露中，提出一种MG电极形成方案以改良MG电极的性能。基于不同晶体管中的不同目标阈值电压，在一些操作之后减少或移除已形成的选定MG电极中的障壁层，使得可在各种晶体管的最终MG电极中达成不同障壁层厚度。根据要求，可用更高设计及制造灵活性有效地改良不同晶体管之间的阈值电压控制。可达成MG电极的良好填充性能及角隅轮廓控制。此外，获得用于MG电极中(尤其在MG的底部周围)的填充材料的扩大填充区域，由此降低MG电阻。另外，提供额外热处理以减少或消除归因于一些MG电极中的薄化障壁层的泄漏问题。
图1A到1T为展示根据一些实施例的制造半导体装置100的方法的中间阶段的示意性剖面图。在实施例中，半导体装置100包括一或多个金属氧化物半导体(MOS)场效晶体管(FET)。尽管出于阐释性目的展示平面FET装置，但其它装置配置也为可能的，例如鳍型FET(FINFET)、全环绕式(GAA)FET及类似者。参考图1A，提供衬底202。在实施例中，衬底202为半导体衬底，例如硅衬底。衬底202的其它实例可包括其它元素半导体，例如锗。替代地，衬底202可包括化合物半导体，例如碳化硅、砷化镓、砷化铟或磷化铟。取决于设计要求，衬底202可包括不同掺杂剂类型，例如P型衬底或N型衬底，且可包括各种掺杂配置。此外，衬底202可包括外延层(epi层)或可包括绝缘体上覆硅(SOI)结构。
可在衬底202上形成一或多个隔离结构204。隔离结构204可利用隔离技术，例如硅局部氧化(LOCOS)或浅沟槽隔离(STI)。在本实施例中，隔离结构204包括STI。隔离结构204可包含氧化硅、氮化硅、氮氧化硅、氟化物掺杂的硅酸盐玻璃(FSG)、低K介电质材料、其它合适材料或其等组合。形成隔离结构204的例示性操作可包括：通过光刻操作图案化衬底202；使用例如干式蚀刻、湿式蚀刻或等离子蚀刻操作在衬底202中蚀刻沟槽；及在沟槽中沉积介电质材料。
隔离结构204用来界定第一FET装置262A及第二FET装置262B的主动区203。主动区203可包括各种掺杂配置，例如掺杂有P型或N型掺杂剂的配置。例如，主动区203可掺杂有P型掺杂剂(例如硼或BF2)或N型掺杂剂(例如磷或砷)。主动区203可充当经配置用于N型MOS(NMOS)晶体管或P型MOS(PMOS)晶体管的区。在实施例中，针对不同类型的MOS晶体管，在隔离结构204之间的主动区203中形成掺杂井205。掺杂井205的掺杂剂类型可相同或不同于衬底202。在主动区203中形成NMOS装置(例如，FET装置262B)的实施例中，可透过将P型杂质(其可为硼、铟或类似者)布植到衬底202中来形成P型掺杂井205。在主动区203中形成PMOS装置(例如，FET装置262A)的其它实施例中，可透过将N型杂质(其可为磷、砷、锑或类似者)布植到衬底202中来形成N型掺杂井205。在一些实施例中，掺杂井205不存在于主动区203中。在图1A的阐释性实施例中，FET装置262A及262B可具有相同类型或不同类型。
参考图1B，在衬底202上方形成两个虚设栅极结构201。在本实施例中，各虚设栅极结构201由介电质层206及虚设栅极电极208组成。介电质层206可包含氧化硅、氮氧化硅、高k介电质材料或其等组合。在一些实施例中，虚设栅极电极208包括单层或多层结构。在本实施例中，虚设栅极电极208包括多晶硅。可通过以毯覆方式在衬底202上方沉积介电质层206及虚设栅极电极208的材料来形成虚设栅极结构201。沉积步骤可包括物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)或其它合适方法。在沉积材料上方形成光致抗蚀剂(未展示)且图案化光致抗蚀剂。执行蚀刻操作以将图案化光致抗蚀剂的特征转印到下伏层以便形成虚设栅极结构201。在实施例中，虚设栅极结构201包括额外介电质层或导电层，例如硬掩模层、界面层、覆盖层或其等组合。
参考图1C，在虚设栅极结构201的各者的两侧上各自掺杂井205中形成轻度掺杂源极/漏极(LDD)区212。在实施例中，在隔离结构204与虚设栅极结构201之间形成LDD区212。可通过布植操作(例如离子布植步骤)在衬底202中形成LDD区212。LDD区212可包括与各自掺杂井205相反的掺杂剂类型。在实施例中，LDD区212可掺杂有P型掺杂剂，例如硼或BF2；N型掺杂剂，例如磷或砷；或其等组合。在实施例中，LDD区212与虚设栅极结构201的侧壁对准。
在形成LDD区212之后，在虚设栅极结构201的各侧上形成间隔件210。栅极间隔件210可包含介电质材料，例如氮化硅、氧化硅、碳化硅、氮氧化硅或其等组合。在实施例中，间隔件210包含多层结构。可使用沉积操作(例如PVD、CVD或ALD)或蚀刻操作形成间隔件210。蚀刻操作可为各向异性蚀刻。
可在隔离结构204与间隔件210之间的各自掺杂井205中形成源极/漏极(S/D)区214。S/D区214可掺杂有P型掺杂剂，例如硼或BF2；N型掺杂剂，例如磷或砷；或其等组合。S/D区214可包括相同于LDD区212的掺杂剂类型的掺杂剂类型，同时具有大于LDD区212的掺杂浓度。在实施例中，使用离子布植步骤形成S/D区214且布植轮廓与间隔件210的外侧壁大体上对准。在一些实施例中，可使用硅化操作在S/D区214上形成一或多个接触构件(例如，硅化物区，未单独展示)。在一些实施例中，可通过外延生长形成S/D区214。在一些实施例中，S/D区214可具有高于衬底202的表面的凸起表面。
在衬底202上方且环绕虚设栅极结构201及间隔件21形成蚀刻停止层(ESL)216，如图1D中所绘示。ESL 216可包括氮化硅、氧化硅、氮氧化硅或其它合适材料。可使用任何合适操作形成ESL 216，例如PVD、CVD或ALD。在本实施例中，ESL 216为包括氮化硅的接触蚀刻停止层(CESL)。
仍参考图1D，随后在ESL 216上方形成层间(或层级间)介电质(ILD)层218。ILD层218可填充虚设栅极结构201之间的间隙且环绕ESL层216。ILD层218可包含介电质材料且通过任何合适沉积操作形成。介电质材料可包含氧化硅、氮化硅、氮氧化硅、旋涂玻璃(SOG)、掺氟硅玻璃(FSG)、聚酰亚胺或其它合适介电质材料。在一些实施例中，ILD层218可包括高密度等离子(HDP)介电质材料(例如，HDP氧化物)及/或高纵横比工艺(HARP)介电质材料(例如，HARP氧化物)。
图1E绘示执行平坦化操作以移除ILD层218及ESL层216的多余部分的结果。平坦化操作可包括化学机械抛光(CMP)操作或机械研磨。据此曝光虚设栅极电极208的顶表面。在实施例中，通过平坦化操作使ILD层218、ESL层216及虚设栅极电极208的顶表面平整。
随后，分别形成用于各自FET装置262A及262B的第一金属栅极堆叠260A及第二金属栅极堆叠260B以代替对应虚设栅极结构201。最初，从各自虚设栅极结构201移除各虚设栅极电极208，如图1F中所展示。因此，例示性第一沟槽209A及例示性第二沟槽209B经形成为由间隔件210界定且由ESL 216及ILD层218环绕。可在蚀刻操作(例如湿式蚀刻、干式蚀刻或其等组合)中移除虚设栅极电极208。在实施例中，于虚设栅极电极移除操作之后，介电质层206被保留于沟槽209A及209B中。在替代实施例中，于虚设栅极电极208的蚀刻期间移除介电质层206。在实施例中，虚设栅极电极208的湿式蚀刻操作包括曝光于含氢氧化物的溶液(例如，氢氧化铵)、去离子水或其它合适蚀刻剂溶液。
图1G绘示在衬底202上方形成栅极介电质层220。在ILD层218、ESL 216及间隔件210上方且在沟槽209A及209B的侧壁及底部上保形地形成栅极介电质层220。栅极介电质层220可为由高k介电质材料形成，例如氧化铪(HfO2)、氧化铪硅(HfSiO)、氮氧化铪硅(HfSiON)、氧化钽铪(HfTaO)、氧化铪钛(HfTiO)、氧化铪锆(HfZrO)、金属氧化物、金属氮化物、金属硅酸盐、过渡金属氧化物、过渡金属氮化物、过渡金属硅酸盐、金属氮氧化物、金属铝酸盐、硅酸锆、铝酸锆、氧化锆、氧化钛、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)合金、其它合适高k介电质材料，或其等的组合。替代地，栅极介电质层220可包括氮化硅、氮氧化硅，或氧化硅。在本实施例中，栅极介电质层220包括高k材料连同介电质层206作为氧化硅层。可使用PVD、CVD或其它合适的沉积方法来形成栅极介电质层220。在其中通过图1F的蚀刻操作预先移除栅极介电质层206的实施例中，栅极介电质层220的形成还可包括在形成栅极介电质层220的高k介电质材料之前于沟槽209的底部中沉积界面层，所述界面层可由氧化硅、氮化硅或类似者形成。
如下般描述对应金属栅极堆叠260A及260B的MG电极的形成。在栅极介电质层220上方沉积第一障壁层222，如图1H中所绘示。第一障壁层222包含选自TiN、TiCN、TaN、TaCN、WN、WCN、TaSiN及TiSiN的群组的材料。在实施例中，第一障壁层222具有多层或堆叠式结构。在实施例中，在栅极介电质层220的侧壁及底部上保形地沉积第一障壁层222。可使用PVD、CVD或其它合适沉积方法形成第一障壁层222。第一障壁层222为半导体装置100的MG电极提供各种功能。例如，第一障壁层222可用作防止上覆层中的金属原子扩散到下伏构件中的扩散障壁层。此外，第一障壁层222的配置(例如其轮廓及厚度)可影响最终半导体装置100的阈值电压。在实施例中，采用第一障壁层222作为下伏层的保护层，使得随后执行的处理不会不利地影响下伏构件。
参考图1I，执行第一处理240。在实施例中，第一处理240为退火操作，其中在高温下处理衬底202或除衬底202以外的半导体装置100的层/构件。在实施例中，退火操作在约摄氏750度与约摄氏900度之间执行且在其它实施例中在约摄氏400度与约摄氏800度之间执行。退火可具有介于10ms与约80ms之间的持续时间。作为退火操作的第一处理240可用来增强栅极介电质层220的材料性质。在实施例中，第一处理240为蚀刻操作，其中蚀刻半导体装置100的一部分。在实施例中，第一处理240为清洁步骤。在其中第一处理240作为蚀刻或清洁操作的条件下，可保护下伏于第一障壁层222的材料(例如栅极介电质层220)使之免受归因于第一处理240所致的不利影响。在实施例中，第一障壁层222被视为用于第一处理240的蚀刻停止层。在实施例中，第一障壁层222与栅极介电质层220之间的蚀刻选择性大于约10，或在其它实施例中大于约5。
在第一障壁层222及栅极介电质层220上方沉积第二障壁层224，如图1J中所绘示。第二障壁层224包含选自TiN、TiCN、TaN、TaCN、WN、WCN、TaSiN及TiSiN的群组的材料。在实施例中，第二障壁层224具有多层或堆叠式结构。在实施例中，在第一沟槽209A及第二沟槽209B的侧壁及底部上保形地沉积第二障壁层224。可使用PVD、CVD或其它合适沉积方法形成第二障壁层224。类似于第一障壁层222，第二障壁层224为半导体装置100的MG电极提供各种功能。例如，第二障壁层224可用作防止上覆层中的金属原子扩散到下伏构件中的扩散障壁层。此外，第二障壁层224的配置(例如其轮廓及厚度)可影响最终半导体装置100的阈值电压。在实施例中，采用第二障壁层224作为下伏层的保护层，使得一些处理不会不利地影响下伏构件。在实施例中，第一障壁层222及第二障壁层224具有不同材料组合物及/或厚度。
参考图1K，执行第二处理250。在实施例中，第二处理250为退火操作，其中在高温下处理衬底202或除衬底202以外的半导体装置100的层/构件。在实施例中，退火操作在约摄氏750度与约摄氏900度之间执行且在其它实施例中在约摄氏400度与约摄氏800度之间执行。在实施例中，退火操作在约摄氏800度与约摄氏950度之间执行。退火可具有介于10ms与约80ms之间的持续时间。作为退火操作的第二处理250可用来增强栅极介电质层220的材料性质。退火操作可用来增强栅极介电质层220或图1K的结构的其它部分的材料性质。在实施例中，第二处理250为蚀刻操作，其中蚀刻半导体装置100的部分。在实施例中，第二处理250为清洁步骤。在其中第二处理250作为蚀刻或清洁操作的条件下，可保护下伏于第二障壁层224的材料(例如栅极介电质层220)使之免受归因于第二处理250的损坏。在实施例中，第二障壁层224被视为用于第二处理250的蚀刻停止层。在实施例中，第二障壁层224与栅极介电质层220之间的蚀刻选择性大于约10，或在其它实施例中大于约5。
图1L展示在第二障壁层224上方沉积功函数层225。功函数层225保形地形成于第二障壁层的水平表面上方且到沟槽209A及209B中。在实施例中，第一P型FET装置262A的功函数层225可包括由例如TiN、W、Ta、Ni、Pt、Ru、Mo、Al、WN、其等组合或类似者的材料组成的一或多个层。在替代实施例中，第二N型FET装置262B的功函数层225可包括由例如Ti、Ag、Al、TiAlMo、Ta、TaN、TiAlC、TiAlN、TaC、TaCN、TiAl、TaSiN、Mn、Zr、其等组合或类似者的材料组成的一或多个层。在一些实施例中，功函数层225可存在于第一P型FET装置262A及第二N型FET装置262B两者中，尽管不同类型的FET装置中的层厚度可为各种各样的。可使用PVD、CVD、ALD或其它合适沉积方法形成功函数层225。
图1M到1Q展示功函数层225、第一障壁层222及第二障壁层224上的选择性蚀刻操作的不同方案。在图1M中所展示的实施例中，透过选择性蚀刻操作从第二N型FET装置262B移除一定厚度的功函数层225。同时，第一P型FET装置262A的第一沟槽209A周围的功函数层225、第一障壁层222及第二障壁层224保持完整。例示性选择性蚀刻操作可包括提供图案化光致抗蚀剂层(未展示)或掩模层以曝光第二沟槽209B，同时保持覆盖第一沟槽209A。随后执行蚀刻步骤以用图案化光致抗蚀剂作为蚀刻掩模来移除功函数层225的部分。可通过湿式蚀刻、干式蚀刻或其等组合执行选择性蚀刻操作。例如，包含HCl、NH4OH、H2SO4及H2O2的至少一者的蚀刻剂可用于湿式蚀刻操作中。蚀刻剂在一些实施例中包含H2O2及HCl，在一些其它实施例中包含NH4OH及H2O2，且在一些其它实施例中包含H2SO4及H2O2。在实施例中，基于Cl的气体可用于干式蚀刻操作中。干式蚀刻操作的持续时间可介于约20秒与约80秒之间。可在蚀刻操作之后剥离光致抗蚀剂或掩模层。在实施例中，可例如透过不同蚀刻时间控制功函数层225的移除厚度，使得根据设计要求仅移除功函数层225的特定厚度。在一些实施例中，蚀刻操作移除沟槽209B外部的功函数层225，同时在沟槽209B内留下具有预定厚度的功函数层225的剩余部分225R。
图1N展示对另一第二N型FET装置262C的蚀刻操作的另一实施例，其中完全移除功函数层225。图1N中还展示第二FET装置262C的各自沟槽209C。据此，归因于蚀刻操作，曝光第二FET装置262C周围的第二障壁层224。同时，使第一P型FET装置262A的第一沟槽209A周围的功函数层225、第一障壁层222及第二障壁层224保持完整。
图1O展示对另一第二N型FET装置262D的蚀刻操作的进一步实施例，其中蚀刻功函数层225及一定厚度的第二障壁层224，从而留下残余第二障壁层224R。图1O中还展示第二FET装置262D的各自沟槽209D。第二FET装置262D周围的第二障壁层224仍覆盖第一障壁层222。同时，使第一P型FET装置262A的第一沟槽209A周围的功函数层225、第一障壁层222及第二障壁层224保持完整。在一些实施例中，蚀刻操作移除沟槽209D外部的功函数层225及第二障壁层224，同时仅在沟槽209D内留下一定厚度的第二障壁层224。
图1P展示对另一第二N型FET装置262E的蚀刻操作的又一实施例，其中完全移除功函数层225及第二障壁层224，同时还蚀刻一定厚度的第一障壁层222。图1P中还展示第二FET装置262E的各自沟槽209E。据此，归因于蚀刻操作，曝光第二FET装置262E周围的第一障壁层222。同时，使第一P型FET装置262A的第一沟槽209A周围的功函数层225、第一障壁层222及第二障壁层224保持完整。
图1Q展示对另一第二N型FET装置262F的蚀刻操作的又一实施例，其中完全移除功函数层225、第二障壁层224及第一障壁层222。图1Q中还展示第二FET装置262E的各自沟槽209F。据此曝光第二FET装置262E的栅极介电质层220。在一些实施例中，仅蚀刻一定厚度的第一障壁层222，且因此通过薄化第一障壁层222覆盖栅极介电质层220。在一些实施例中，蚀刻操作移除沟槽209E外部的第一障壁层222，同时在沟槽209E内仅留下一定厚度的第一障壁层222。同时，使第一P型FET装置262A的第一沟槽209A周围的功函数层225、第一障壁层222及第二障壁层224保持完整。
在实施例中，图1M到1Q中所展示的各种第二N型FET装置262B到262F的两者或更多者可连同第一P型FET装置262A同时存在于半导体装置100中。图1M到1Q中所绘示的蚀刻操作可通过用相同蚀刻剂移除功函数层225、第一障壁层及第二障壁层224的一或多个的单个蚀刻步骤来执行。替代地，可执行多个蚀刻步骤以使用不同蚀刻方法、不同蚀刻剂气体或配方、或使用不同蚀刻室蚀刻功函数层225、第一障壁层及第二障壁层224。
沟槽209A及209B到209F中的功函数层225、第一障壁层222及第二障壁层224上的不同蚀刻布置实现衬底202中的MOSFET装置(尤其NMOS晶体管装置)的各种MG电极中的不同电压阈值。透过通过控制功函数层225、第一障壁层222及第二障壁层224的厚度来获得薄化或移除的复合结构的蚀刻操作，可将FET装置262B到262F的阈值电压制成彼此不同。具体而言，透过移除障壁层，可针对FET装置(例如，装置209F)达成相对低阈值电压。因此制造的FET装置因此可有益于半导体装置的高速性能。
参考图1R，在第二FET装置209F的栅极介电质层220上方选择性地沉积功函数层226。图1R中展示包括FET装置262A及262F的例示性半导体装置100。因此，在栅极介电质层220上直接形成功函数层226。另外，如果功函数层225、第一障壁层222及第二障壁层224保留于各自沟槽中，那么可在此等层的最顶层上形成功函数层226。在一些实施例中，还在第一P型FET装置262A的功函数层225上形成功函数层226。功函数层226可由一或多个层形成且可包含选自TiN、TaN、WN、Ti、Ag、Al、TiAlMo、Ta、TiAlC、TiAlN、TaC、TaCN、TiAl、TaSiN、Mn、Zr、其等组合或类似者的群组的材料。在本实施例中，功函数层226包含用于N型FET装置的Al或AlTi。在实施例中，功函数层226中的Al与Ti的原子比介于约1与5之间。
一旦沉积功函数层226，随后便形成黏著剂层228。黏著剂层228经形成于功函数层225及226的表面上方且到沟槽209A及209F中。黏著剂层228可包括Ti、TiN、Ta、TaN或其等组合。可使用PVD、CVD、溅镀、电镀或其它合适方法形成功函数层226及黏著剂层228。
在黏著剂层228上方沉积导电层230，如图1S中所绘示。导电层230也填充由黏著剂层228环绕的沟槽209A及209F中的空间。在实施例中，导电层230可包括铜、钴、铝、钨或其它合适材料。可使用CVD、PVD、电镀或其它合适工艺沉积导电层230。由于第二FET装置262F的沟槽209F具有厚度小于第一FET装置262A的沟槽209A的障壁层222及224以及功函数层225，因此可达成沟槽209F的更大填充能力。
参考图1T，在用导电层230填充沟槽209A及209F之后，执行平坦化操作(例如，CMP或机械研磨操作)以使栅极介电质层220、第一障壁层222、第二障壁层224、功函数层225及226、黏著剂层228及导电层230平整。在实施例中，透过平坦化操作来曝光ILD层218的上表面。因此，形成第一金属栅极堆叠260A及第二金属栅极堆叠260F，使得P型FET装置262A的第一金属栅极堆叠260A包含介电质层206、栅极介电质层220、第一障壁层222、第二障壁层224、功函数层225及226、黏著层228及导电层230，而N型FET装置262F的第二金属栅极堆叠260F则包含介电质层206、栅极介电质层220、功函数层226、黏著剂层228及导电层230。在替代实施例中，其它第二金属栅极堆叠(例如透过图1M到1Q的一者中的蚀刻操作形成的第二金属栅极堆叠)包括第一障壁层222、第二障壁层224及功函数层225中的一或多个。
第二金属栅极堆叠260F中的导电层230具有大于第一金属栅极堆叠260A中的导电层230的宽度的宽度。此意谓归因于在填充导电层230之前移除第一障壁层222及/或第二障壁层224，在第二金属栅极堆叠260B中获得良好MG填充能力。此外，归因于从俯视图角度的较大导电面积，第二金属栅极堆叠260F的金属栅极电阻低于第一金属栅极堆叠260A的金属栅极电阻。在一些实施例中，归因于较低填充金属量及较高电阻，第一金属栅极堆叠260A的所得阈值电压大于第二金属栅极堆叠260B的阈值电压。在实施例中，于形成金属栅极堆叠260A及260B之后执行包括互连处理的后续工艺。
如先前所描述，透过选择性地蚀刻障壁层222及/或224来解决金属栅极堆叠中的导电层的填充能力的问题。填充能力可为由从导电层230的俯视图角度的面积或从剖面视图的宽度粗略指示。图2展示根据一些实施例的半导体装置100的第二金属栅极堆叠260F的放大示意性剖面图。在实施例中，从衬底202的表面202A测量的第二金属栅极堆叠260F的高度H1(或等效地，栅极介电质层220及介电质层206的高度总和)介于约10nm与约30nm之间。在实施例中，第二沟槽209F的宽度L(参见图1Q)或大体上FET装置262F的沟道区的长度L介于约6nm与约240nm之间。导电层230包括具有宽度W2的顶表面及具有宽度W3的底表面。由于从第二金属栅极堆叠260F移除障壁层222及224，故留下更大空间用于填充导电层230。在实施例中，归因于悬垂效应，黏著剂层228的侧壁可在其顶表面周围包括大于中间或底部部分的厚度。因此，导电层230的底部宽度W3可大于顶部宽度W2。在实施例中，导电层230在导电层230的底表面周围具有最大宽度W1。在实施例中，最大宽度W1介于约1nm与约10nm之间。在实施例中，宽度W2等于或小于约5nm且大于0nm。在实施例中，宽度W2与最大宽度W1之间的比等于或小于约30％且大于0％。在实施例中，最大宽度W1是从表面202A测量的介于约3nm与约10nm之间的高度H2。在实施例中，高度H2与高度H1之间的比介于约10％与约30％之间。
图3为展示根据一些实施例的相对于栅极填充能力的第二金属栅极堆叠260F的装置性能的示意图。所述图表绘示相对于导电层230的不同宽度的栅极电阻值的模拟结果。如先前所论述，导电层230的更大面积或宽度对应于由导电层230提供的更佳导电性能。因此，导电层230的更大宽度可能导致金属栅极堆叠230B的栅极电阻降低。如图3的图表中所展示，x轴表示最大宽度W1与沟道长度L之间的比，且y轴表示正规化到参考栅极电阻的栅极电阻值，其中最大宽度W1近似零。模拟结果表明，当W1/L的比增加到约15％时，正规化栅极电阻显著降低到其最高值的40％。此外，当W1/L的比增加到约35％时，正规化栅极电阻降低到20％。从前述内容可清楚地明白，扩展宽度W1可有效地降低金属栅极的电阻。也可预期装置优点，例如半导体装置100的较低阈值电压或较高装置速度。
根据实施例，一种形成半导体结构的方法包括：提供衬底；在所述衬底中形成第一对源极/漏极区；在所述衬底上方放置层间介电质层，所述层间介电质层具有所述第一对源极/漏极区之间的第一沟槽；在所述第一沟槽中沉积介电质层；在所述介电质层上方沉积障壁层；从所述第一沟槽移除所述障壁层以曝光所述介电质层；在所述第一沟槽中的所述介电质层上方沉积功函数层；及在所述第一沟槽中的所述功函数层上方沉积导电层。
根据实施例，一种形成半导体结构的方法包括：在衬底中形成第一对源极/漏极区及第二对源极/漏极区；在所述衬底上方沉积层间介电质层，所述层间介电质层具有所述第一对源极/漏极区之间的第一沟槽及所述第二对源极/漏极区之间的第二沟槽；在所述第一沟槽及所述第二沟槽中分别沉积栅极介电质层；在所述第一沟槽及所述第二沟槽中沉积功函数层；在所述第一沟槽及所述第二沟槽中的所述栅极介电质层上方沉积障壁层；从所述第一沟槽减小障壁堆叠的厚度，同时使所述障壁堆叠在所述第二沟槽中保持完整；及在所述第一沟槽及所述第二沟槽中的所述功函数层上方沉积导电层。
根据实施例，一种半导体结构包括衬底以及在所述衬底中的第一对源极/漏极区及第二对源极/漏极区。所述半导体结构还包括分别在所述衬底上方所述第一对源极/漏极区之间及所述第二对源极/漏极区之间的第一栅极堆叠及第二栅极堆叠。各栅极堆叠包括：栅极介电质层，其在所述衬底上方；功函数层，其由所述栅极介电质层环绕；及导电层，其由所述功函数层环绕。所述第一栅极堆叠进一步包括在所述栅极介电质层与所述功函数层之间不存在于所述第二栅极堆叠的障壁层。
前述内容概述若干实施例的特征，使得所属领域的一般技术人员可更好地理解本揭露的方面。所属领域的一般技术人员应明白，其等可容易使用本揭露作为设计或修改用于实行本文中所介绍的实施例的相同目的及/或达成相同优点的其它工艺及结构的基础。所属领域的一般技术人员还应认知，此等等效构造不背离本揭露的精神及范畴，且其等可在不背离本揭露的精神及范畴的情况下在本文中作出各种改变、置换及更改。
符号说明
100 半导体装置
201 虚设栅极结构
202 衬底
202A 表面
203 主动区
204 隔离结构
205 掺杂井
206 介电质层
208 虚设栅极电极
209A 第一沟槽
209B 第二沟槽
209C 沟槽
209D 沟槽
209E 沟槽
209F 沟槽
210 栅极间隔件
212 轻度掺杂源极/漏极(LDD)区
214 源极/漏极(S/D)区
216 蚀刻停止层(ESL)
218 层间(或层级间)介电质(ILD)层
220 栅极介电质层
222 第一障壁层
224 第二障壁层
224R 残余第二障壁层
225 功函数层
225R 剩余部分
226 功函数层
228 黏著剂层
230 导电层
240 第一处理
250 第二处理
260A 第一金属栅极堆叠
260B 第二金属栅极堆叠
260F 第二金属栅极堆叠
262A 第一P型场效晶体管(FET)装置
262B 第二N型场效晶体管(FET)装置
262C 第二N型场效晶体管(FET)装置
262D 第二N型场效晶体管(FET)装置
262E 第二N型场效晶体管(FET)装置
262F 第二N型场效晶体管(FET)装置
H1 高度
H2 高度
L 长度
W1 最大宽度
W2 顶部宽度
W3 底部宽度

Claims (1)

1.一种形成半导体结构的方法，其包含：
提供衬底；
在所述衬底中形成第一对源极/漏极区；
在所述衬底上方放置层间介电质层，所述层间介电质层具有介于所述第一对源极/漏极区之间的第一沟槽；
在所述第一沟槽中沉积介电质层；
在所述介电质层上方沉积障壁层；
从所述第一沟槽移除所述障壁层以曝光所述介电质层；
在所述第一沟槽中的所述介电质层上方沉积功函数层；及
在所述第一沟槽中的所述功函数层上方沉积导电层。
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