CN111128860A - 集成电路结构的形成方法 - Google Patents

集成电路结构的形成方法 Download PDF

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CN111128860A
CN111128860A CN201911050734.XA CN201911050734A CN111128860A CN 111128860 A CN111128860 A CN 111128860A CN 201911050734 A CN201911050734 A CN 201911050734A CN 111128860 A CN111128860 A CN 111128860A
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hard mask
opening
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mask layer
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CN111128860B (zh
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王鹏
黄玉莲
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种集成电路结构的形成方法，包括：形成第一硬遮罩层和于第一硬遮罩层上方的第二硬遮罩层，以及形成三层(tri‑layer)包括：底层、中间层、图案化上层。此方法还包括：蚀刻中间层，以将在图案化上层中的开口延伸进入中间层，其中开口在中间层中具有第一部分，且第一部分具有第一顶宽度和小于第一顶宽度的第一底宽度；蚀刻底层，以将开口延伸进入底层；以及蚀刻第二硬遮罩层，以将开口延伸进入第二硬遮罩层。在第二硬遮罩层中的开口具有第二部分，且第二部分具有第二顶宽度和小于第二顶宽度的第二底宽度。

Description

集成电路结构的形成方法
技术领域
本发明实施例涉及半导体元件的形成方法，特别涉及收缩开口宽度的方法。
背景技术
在集成电路的制造中，使用源极/漏极接触插塞来连接至源极和漏极区和晶体管的栅极。一般连接源极/漏极接触插塞至源极/漏极硅化物区，其形成工艺包括在层间介电质中形成接触开口，沉积金属层，并使其延伸进入接触开口，接着进行退火以使金属层和源极/漏极区的硅/锗进行反应。接着在剩余的接触开口中形成源极/漏极接触插塞。
发明内容
一种集成电路结构的形成方法，包括：形成第一硬遮罩层；形成第二硬遮罩层于第一硬遮罩层上方；形成三层(tri-layer)，三层包括：底层于第二硬遮罩层上方，中间层于底层上方，以及图案化上层于中间层上方；用图案化上层作为蚀刻遮罩来蚀刻中间层，以将在图案化上层中的开口延伸进入中间层，其中开口具有在中间层中的第一部分，且第一部分具有第一顶宽度和小于第一顶宽度的第一底宽度；蚀刻底层，以将开口延伸进入底层，其中在底层中的开口的一部分实质上具有垂直侧壁；以及蚀刻第二硬遮罩层，以将开口延伸进入第二硬遮罩层，其中在第二硬遮罩层中的开口具有第二部分，且第二部分具有第二顶宽度和小于第二顶宽度的第二底宽度。
一种集成电路结构的形成方法，包括：形成层间介电质于晶体管的源极/漏极区上方；形成第一硬遮罩层于层间介电质上方；形成三层于第一硬遮罩层上方，包括：形成底层于第一硬遮罩层上方，形成中间层于底层上方，以及形成上层于中间层上方，其中上层具有开口；用上层作为蚀刻遮罩，以蚀刻中间层和底层，其中开口延伸进入中间层和底层，其中开口的宽度从在中间层的顶面层级的第一顶宽度收缩至在底层的底面层级的第一底宽度，且底层实质上具有垂直侧壁；蚀刻第一硬遮罩层，其中开口延伸进入第一硬遮罩层，其中开口的宽度从第一底宽度收缩至在第一硬遮罩层的底面层级的第二底宽度；以及使用第一硬遮罩层作为蚀刻遮罩的一部分来蚀刻层间介电质，以将开口延伸进入层间介电质。
一种集成电路结构的形成方法，包括：形成第一硬遮罩层于层间介电质上方；形成第二硬遮罩层于第一硬遮罩层上方；形成三层，三层包括：底层于第二硬遮罩层上方，中间层于底层上方，以及图案化上层于中间层上方，其中在图案化上层中形成开口；以及将开口延伸进入中间层、底层、第二硬遮罩层、和第一硬遮罩层，其中在第二硬遮罩层中的开口的第一部分具有第一顶宽度和小于第一顶宽度的第一底宽度，以及在第一硬遮罩层中的开口的部分具有顶宽度和与顶宽度相等的底宽度。
附图说明
以下将配合附图详述本公开的各面向。应注意的是，依据在业界的标准做法，各种特征并未按照比例绘制。事实上，可任意地放大或缩小元件的尺寸，以清楚地表现出本公开的特征。
图1至8、9A、9B、10A、10B、11、12、13A、13B、14A、14B、15A、15B、16A、16B、16C、17A、17B、17C、18A、18B、和18C是根据一些实施例示出了鳍式场效晶体管(Fin Field-EffectTransistors,FinFETs)形成的中间阶段的透视图、俯视图、和剖面图。
图19是根据一些实施例示出了形成鳍式场效晶体管的工艺流程。
附图标记说明：
10～晶圆
20～基底
22～(浅沟槽)隔离区
22A～顶面
24～半导体条
24’～凸出鳍
30～虚置栅极堆叠
32～虚置栅极介电质
34～虚置栅极电极
36～硬遮罩层
38～栅极间隔物
40～凹槽
42～外延区(源极/漏极区)
43～气隙
46～接触蚀刻停止层
47～蚀刻停止层
48～层间介电质
49～(第二)层间介电质
52～(替换)栅极介电质
54～金属栅极电极
56～替换栅极堆叠
58～硬遮罩
60～硬遮罩层
62～硬遮罩层
64～蚀刻遮罩
64A～蚀刻遮罩
64B～蚀刻遮罩
66～部分
68～区域
70～底层
72～中间层
74～上层
76/76A/76B/76C/76D/76’～开口
80～底层
82～中间层
84～上层
86～开口
90～源极/漏极硅化物区
92～源极/漏极接触插塞
92A～接触插塞
92B～接触插塞
94～晶体管
94A～晶体管
94B～晶体管
200～工艺流程
202/204/206/208/210/212/214/216/218/220/222/224～工艺
T1～厚度
T2～厚度
W1～(第一)顶宽度
W2～(第一)底宽度
W3～(第二)顶宽度
W4～(第二)底宽度
α1～倾斜角度
α2～倾斜角度
【生物材料寄存】无
具体实施方式
以下公开提供了许多的实施例或范例，用于实施本发明实施例的不同部件。组件和配置的具体范例描述如下，以简化本发明实施例。当然，这些仅仅是范例，并非用以限定本发明实施例。举例来说，叙述中提及第一部件形成于第二部件之上，可包括形成第一和第二部件直接接触的实施例，也可包括额外的部件形成于第一和第二部件之间，使得第一和第二部件不直接接触的实施例。另外，本发明实施例可在各种范例中重复元件符号及/或字母。这样重复是为了简化和清楚的目的，其本身并非主导所讨论各种实施例及/或配置之间的关系。
再者，此处可使用空间上相关的用语，如“在…之下”、“下方的”、“低于”、“在…上方”、“上方的”和类似用语可用于此，以便描述如图所示一元件或部件和其他元件或部件之间的关系。这些空间用语企图包括使用或操作中的装置的不同方位。当装置被转至其他方位(旋转90°或其他方位)，则在此所使用的空间相对描述可同样依旋转后的方位来解读。
根据一些实施例，提供包括源极/漏极接触插塞的晶体管及其形成方式。根据一些实施例，示出了形成晶体管的中间阶段。讨论一些实施例的一些变化。综观不同视图和示出的实施例，使用类似元件符号来标示类似的元件。根据本发明的一些实施例，讨论了一种减少源极/漏极接触开口宽度的方法，使其宽度小于微影工艺的极限。通过减少在用来形成接触开口的蚀刻遮罩中的对应开口尺寸，以收缩接触开口的宽度。
根据一些实施例，使用鳍式场效晶体管(Fin Field-Effect Transistors,FinFETs)的形成作为一个范例，以解释本发明实施例的概念。平面状晶体管也可采取本发明实施例的概念。再者，根据一些实施例，可使用形成开口的方法，来形成源极/漏极接触开口以外的开口。举例来说，可采用本发明实施例的方法，以形成栅极接触开口、穿硅通孔(through-silicon vias)、金属走线、和介电层中(如在低k介电层中)的导孔。
图1至8、9A、9B、10A、10B、11、12、13A、13B、14A、14B、15A、15B、16A、16B、16C、17A、17B、17C、18A、18B、和18C是根据本发明的一些实施例，在鳍式场效晶体管和源极/漏极接触插塞的形成中，示出了中间阶段的剖面图、俯视图、和透视图。在工艺流程200中，如在图19中，示出了形成工艺。
图1示出了在晶圆10上形成的初始结构的透视图，其晶圆包括基底20。基底20可是半导体基底，其可是硅基底、锗化硅基底、或以其他半导体材料形成的基底。可以P型或N型杂质掺杂基底20。可形成隔离区22，如浅沟槽隔离(shallow trench isolation,STI)区，以从基底20的顶面延伸进入基底20。介于相邻浅沟槽隔离区22之间的部分基底20被称为半导体条(semiconductor strip)24。根据一些实施例，半导体条24的顶面和浅沟槽隔离区22的顶面实质上可与彼此齐平。根据本发明的一些实施例，半导体条24是原先基底20的部分，故半导体条24的材料与基底20的材料相同。根据本发明的替代实施例，半导体条24为替换条，其形成是通过蚀刻介于浅沟槽隔离区22之间的部分基底20以形成凹槽，并在凹槽中进行外延以再成长另一个半导体材料。于是，半导体条24是以不同于基底20的半导体材料所形成。根据一些实施例，半导体条24是以锗化硅、碳化硅、或一III-V族化合物半导体材料所形成。
浅沟槽隔离区22可包括衬氧化物(未绘出)，其可是通过基底20表面层的热氧化形成的热氧化物。衬氧化物也可是沉积的硅氧化物层，使用，例如原子层沉积、高密度等离子体化学气相沉积、或化学气相沉积来形成。浅沟槽隔离区22也包括于衬氧化物上方的介电材料，其中可使用流动性化学气相沉积、旋转涂布、或其他类似方法来形成其介电材料。
参考图2，凹蚀浅沟槽隔离区22，使半导体条24的顶部凸出高于浅沟槽隔离区22剩余部分的顶面22A，以形成凸出鳍24’。个别工艺示出于图19的工艺流程200中的工艺202。可使用干蚀刻工艺来进行蚀刻，其中使用HF3和NH3作为蚀刻气体。在蚀刻工艺期间，可产生等离子体。也可包括氩。根据本发明的替代实施例，使用湿蚀刻工艺来进行浅沟槽隔离区22的凹蚀。举例来说，蚀刻化学品可包括HF。
在上方示出的实施例中，可通过任何适合方法图案化鳍。举例来说，可使用一或多光微影工艺来图案化鳍，包括双重图案化(double-patterning)或多重图案化(multi-patterning)工艺。总体而言，双重图案化或多重图案化工艺结合光微影和自我对准工艺，允许创造出具有节距的图案，其节距小于，例如，另外使用单一直接光微影工艺可获得的节距。举例来说，在一实施例中，使用光微影工艺于基底上形成并图案化牺牲层。使用自我对准工艺，沿着图案化的牺牲层，来形成间隔物。接着，移除牺牲层，则可使用剩余的间隔物，或芯轴(mandrels)，来图案化鳍。
参考图3，形成虚置栅极堆叠30，以延伸在(凸出)鳍24’的顶面和侧壁上。个别工艺示出于图19的工艺流程200中的工艺204。虚置栅极堆叠30可包括虚置栅极介电质32和于虚置栅极介电质32上方的虚置栅极电极34。可使用，例如，多晶硅或非晶硅来形成虚置栅极电极34，且也可使用其他材料。各别虚置栅极堆叠30也可包括于对应虚置栅极电极34上方的一个(或复数个)硬遮罩层36。可以硅氮化物、硅氧化物、硅碳氮化物、或类似材料、或其复合层，来形成硬遮罩层36。虚置栅极堆叠30可横跨单一或复数个凸出鳍24’及/或浅沟槽隔离区22。虚置栅极堆叠30也具有长度方向，其垂直于凸出鳍24’的长度方向。
接着，在虚置栅极堆叠30的侧壁上形成栅极间隔物38。个别工艺也示出于图19的工艺流程200中的工艺204。根据本发明的一些实施例，以介电材料，如硅氮化物、硅碳氮化物、或其他类似材料，来形成栅极间隔物38，并可具有单层结构或包括复数个介电层的多层结构。
接着，可进行蚀刻工艺，以蚀刻凸出鳍24’没有被虚置栅极堆叠30和栅极间隔物38覆盖的部分，所得的结构示出于图4。凹蚀可是异向性(anisotropic)，故鳍24’于虚置栅极堆叠30和栅极间隔物38正下方的部分被保护着，没有被蚀刻。根据一些实施例，凹蚀的半导体条24的顶面可低于浅沟槽隔离区22的顶面22A。相应地在浅沟槽隔离区22之间形成凹槽40。凹槽40置于虚置栅极堆叠30的两侧上。
接着，通过选择性地在凹槽40中成长半导体材料，来形成外延区(源极/漏极区)42，所得的结构在图5中。个别工艺示出于图19的工艺流程200中的工艺206。根据一些实施例，外延区42包括锗化硅、硅、碳化硅、或其他类似材料。根据所得的鳍式场效晶体管是P型鳍式场效晶体管或是N型鳍式场效晶体管，可随着外延的进行，原位(in-situ)掺杂P型或N型杂质。举例来说，当所得的鳍式场效晶体管是P型鳍式场效晶体管时，可成长SiGeB、GeB、或其他类似材料。相反地，当所得的鳍式场效晶体管是N型鳍式场效晶体管时，可成长SiP、SiCP、或其他类似材料。根据本发明的替代实施例，以III-V族化合物半导体，如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、其组合、或其复合层，来形成外延区42。在外延区42填充凹槽40之后，外延区42开始水平地扩张，并可形成晶面。也可形成气隙43。
在外延步骤之后，还可将P型或N型杂质布植至外延区42，以形成源极和漏极区，其也使用元件符号42标示。根据本发明的替代实施例，当在外延期间，以P型或N型杂质原位掺杂外延区42时，则略过布植步骤。
图6示出了在接触蚀刻停止层46和层间介电质48的形成之后的结构的透视图。个别工艺示出于图19的工艺流程200中的工艺208。可以硅氧化物、硅氮化物、硅碳氮化物、或其他类似材料，且可使用化学气相沉积、原子层沉积、或其他类似方法，来形成接触蚀刻停止层46。层间介电质48可包括介电材料，其形成是使用，例如，流动性化学气相沉积、旋转涂布、化学气相沉积、或其他沉积方法。可以含氧介电材料形成层间介电质48，其可是氧化硅为基础的氧化物，如四乙氧基硅烷氧化物(tetra ethyl ortho silicate oxide)、等离子体促进化学气相沉积氧化物(SiO2)、磷硅酸玻璃、硼硅酸玻璃、硼掺杂磷硅酸玻璃、或其他类似材料。可进行平坦化工艺，如化学机械抛光工艺或机械研磨工艺，来使层间介电质48、虚置栅极堆叠30、和栅极间隔物38的顶面彼此齐平。
接着，以替换栅极堆叠56来取代虚置栅极堆叠30，虚置栅极堆叠30包括硬遮罩层36、虚置栅极电极34、和虚置栅极介电质32。个别工艺示出于图19的工艺流程200中的工艺210。替换栅极堆叠56包括金属栅极54和栅极介电质52，如图7所示。当形成替换栅极堆叠56时，首先以一个或复数个蚀刻步骤移除硬遮罩层36、虚置栅极电极34、和虚置栅极介电质32，如图7所示，所得的沟槽/开口是形成在栅极间隔物38之间。凸出的半导体鳍24’的顶面和侧壁露出于所得的沟槽。
接着，形成(替换)栅极介电层52，其延伸进入在栅极间隔物38之间的沟槽。根据本发明的一些实施例，各栅极介电层52包括界面层作为其下部，来接触对应凸出鳍24’的露出面。界面层可包括氧化物层，如硅氧化物层，其通过凸出鳍24’的热氧化、化学氧化工艺、或沉积工艺来形成。栅极介电层52也可包括形成于界面层上方的高k介电层。高k介电层可包括高k介电材料，如铪氧化物、镧氧化物、铝氧化物、锆氧化物、硅氮化物、或其他类似材料。高k介电材料的介电常数(k值)高于3.9，且可高于约7.0。形成高k介电层作为顺应层，并延伸于凸出鳍24’的侧壁上和栅极间隔物38的侧壁上。根据本发明的一些实施例，使用原子层沉积或化学气相沉积来形成高k介电层。
进一步参考图7，于栅极介电质52上方形成栅极电极54，栅极电极54包括导电次层(sub-layers)。虽然次层之间是有可能可以彼此区别的，但次层没有被分开示出。可使用顺应性沉积方法，如原子层沉积或化学气相沉积，来进行次层的沉积。
堆叠的导电次层可包括扩散阻障层和于扩散阻障层上方的一(或多个)功函数层(work-function layer)。可以TiN来形成扩散阻障层，TiN可(或可不)被硅掺杂。功函数层决定了栅极的技术效果，且包括以不同材料形成的至少一层，或复数个层。功函数层的材料的选择是根据个别鳍式场效晶体管是N型鳍式场效晶体管或是P型鳍式场效晶体管。举例来说，当鳍式场效晶体管是N型鳍式场效晶体管时，功函数层可包括TaN层和于TaN层上方的TiAl层。当鳍式场效晶体管是P型鳍式场效晶体管时，功函数层可包括TaN层、于TaN层上方的TiN层、和于TiN层上方的TiAl层。在功函数层的沉积之后，形成阻障层，其可为另一TiN层。
形成沉积的栅极介电层和导电层作为顺应层来延伸进入沟槽，且包括于层间介电质48上方的一些部分。接着，沉积金属材料来填充在栅极间隔物38之间的剩余沟槽。举例来说，可以钨或钴，来形成金属材料。在后续的步骤中，进行平坦化步骤，如化学机械抛光工艺或机械研磨工艺，来移除于层间介电质48上方的部分栅极介电层、导电次层、和金属材料。如此一来，形成金属栅极电极54和栅极介电质52。栅极电极54和栅极介电质52统称为替换栅极堆叠56。在此时，替换栅极堆叠56、栅极间隔物38、接触蚀刻停止层46、和层间介电质48的顶面实质上可为共面性。
根据一些实施例，图7也示出了硬遮罩58的形成。个别工艺也示出于图19的工艺流程200中的工艺210。硬遮罩58的形成可包括：进行蚀刻步骤来凹蚀栅极堆叠56，让凹槽在栅极间隔物38之间形成；以介电材料填充凹槽；然后进行平坦化工艺，如化学机械抛光工艺或机械研磨工艺，来移除介电材料的多余部分。可以硅氮化物、硅氧氮化物、硅氧碳氮化物、或其他类似材料来形成硬遮罩58。
接着，参考图8，于层间介电质48上方沉积蚀刻停止层47和第二层间介电质49。个别工艺示出于图19的工艺流程200中的工艺212。根据一些实施例，蚀刻停止层47是以，例如硅碳化物、硅氮化物、硅氧化物、或其他类似材料所形成的介电层。层间介电质49形成的材料可选自，和用来形成层间介电质48的候选材料相同的族群。
接着，参考图8，于层间介电质49上方形成硬遮罩层60和62。个别工艺示出于图19的工艺流程200中的工艺214。根据本发明的一些实施例，硬遮罩层60是含金属硬遮罩层，其可以钛氮化物、钨碳化物、或其他类似材料来形成。硬遮罩层60可具有介于约
Figure BDA0002255268340000101
和
Figure BDA0002255268340000102
之间的厚度。硬遮罩层62可是氧化物层，其可是在低温下沉积的低温氧化物层，例如，低于约100℃。硬遮罩层62可具有介于约
Figure BDA0002255268340000103
和
Figure BDA0002255268340000104
之间的厚度T1。
于硬遮罩层62上方形成蚀刻遮罩64A和64B。个别工艺示出于图19的工艺流程200中的工艺216。蚀刻遮罩64A和64B也个别地和统一地被称为蚀刻遮罩64。蚀刻遮罩64的厚度可介于约
Figure BDA0002255268340000105
和
Figure BDA0002255268340000106
之间。可以非晶硅形成蚀刻遮罩64，也可使用具有和下方层60和62充足的蚀刻选择比的其他材料。蚀刻遮罩64A和64B的形成可包括沉积毯覆层(blanketlayer)，然后图案化其毯覆层。可使用化学气相沉积、原子层沉积、或其他类似方法来沉积硬遮罩层60、62、和其他形成蚀刻遮罩64的对应层。
图9A示出了晶圆10一部分的俯视图。图8所示的结构示出了晶圆10的部分66，如图9A所示。在图9A中，根据一些实施例，示出了栅极堆叠56、硬遮罩58、和栅极间隔物38作为平行条(parallel strips)。可在被标记为68的区域中，和在栅极间隔物38之间，形成源极和漏极区42(未绘出)。蚀刻遮罩64A和64B可位在交替的行中。蚀刻遮罩64A和64B可具有不同的长度，其有些比图9所示的较长。举例来说，一些蚀刻遮罩64可延伸横跨三个或更多个栅极堆叠。图9B示出了在图9A中所示的结构的剖面图，其中剖面图是从在图9A中含B-B线段的垂直平面所获得。在后续图示中的后续剖面图，其图号具有字母“B”者，除非另外指明，也是从在对应俯视图中与含B-B线段的垂直平面相同的平面所获得。
第10A、10B、11、12、13A/13B、和14A/14B图示出了第一图案形成工艺，用来形成在硬遮罩层62中的一些接触插塞的图案。个别工艺示出于图19的工艺流程200中的工艺218。于是，在全文中，硬遮罩层62被称作为图案保留层(pattern-reservation layer)。参考图10B，形成三层(tri-layer)，其包括底层70、中间层72、和上层74，来覆盖蚀刻遮罩64。在微影工艺中图案化上层74，以形成开口76。图10A示出了上层74和开口76的俯视图。开口76形成与蚀刻遮罩64B的一些部分相交的条状物。根据一些实施例，开口76具有与Y方向平行的长度方向，而个别开口76可横跨复数个蚀刻遮罩64B的中间部分。
根据一些实施例，以光阻形成上层74，而可以光阻或其他以SixOyCz为基础的材料来形成底层70(图10B)。可以，例如含硅材料，如硅氧氮化物(SiON)或其他类似材料，来形成中间层72。中间层72的厚度T2可介于约
Figure BDA0002255268340000111
和
Figure BDA0002255268340000112
之间。
参考图11，使用图案化的上层74作为蚀刻遮罩来蚀刻中间层72，让开口76延伸进入中间层72。开口76在中间层72中的部分被称为开口76A。根据一些实施例，使用异向性蚀刻方法来进行蚀刻。蚀刻方法可选自反应式离子蚀刻，其可使用电感式耦合等离子体、电容式耦合等离子体、或其他类似方法来执行。工艺气体可包括蚀刻气体和聚合物形成气体。根据一些实施例，蚀刻气体可包括含氟气体，如CF4、NF3、或其组合。聚合物形成气体可包括碳和氟气体，如CHF3、CH2F2、CH3F、C4F6、C4F8、或其组合。工艺气体的压力可介于约5mTorr和200mTorr之间。在蚀刻期间的晶圆10的温度可介于约0℃和50℃之间。在蚀刻工艺中，氟与SixOyCz和聚合物形成气体(如CHF3、CH2F2、CH3F、C4F6、及/或C4F8，其被离子化且***为C3F+、C2F+、CF+3、CF+2、CF+、C4F-等)反应，以便产生聚合物CxFyHz作为在个别开口76A的侧壁上的保护层。
调整蚀刻工艺的条件，如工艺气体的种类和流速，让开口76A的侧壁倾斜。举例来说，当导入更多聚合物形成气体时，开口76A的侧壁更加倾斜，且反之亦然，由于形成的聚合物保护中间层72的侧壁，随着蚀刻的进行，造成开口的尺寸越来越小。开口76A侧壁的倾斜角度α1可小于约89°，且可介于约85°和30°之间。通过提供合适的流速比例，其为聚合物形成气体的流速比蚀刻气体的流速，可从而达到合适的倾斜角度α1。如此一来，开口76A的底宽度W2小于个别开口76A的顶宽度W1。通过聚合物形成气体和蚀刻气体的比例来影响倾斜角度α1。举例来说，加入更多聚合物形成气体，倾斜角度α1变得更小。加入更少的聚合物形成气体，倾斜角度α1变得更大，并可最终大于90°，若没有加入聚合物形成气体。期望底宽度W2小于顶宽度W1，让后续形成的接触开口(图17B)的宽度减少至小于宽度W1。举例来说，在上层74中的开口76的最小宽度被微影工艺的能力所限制。于是，期望的宽度差(W1-W2)足够显著(例如约大于12nm)，让后续形成的接触开口可显著地具有较小的宽度。然而，宽度差(W1-W2)不能太大(例如约大于20nm)，由于如此会导致工艺的困难，和可能地良率流失，基于图案负载效应(pattern-loading effect)。根据本发明的一些实施例，宽度差(W1-W2)是介于约12nm和20nm之间。根据一些实施例，宽度差(W1-W2)的调整是通过调整流速的流速比例FRPF1/FREG1，其中FRPF1是聚合物形成气体的流速，而FREG1是蚀刻气体的流速。根据一些实施例，流速比例FRPF1/FREG1是介于约0.5和3.0之间。又由于开口76A的侧壁是倾斜的，也可通过选择中间层72的合适厚度T2，来调整宽度差(W1-W2)。
图12示出了底层70的蚀刻，让开口76更延伸进入底层70。开口76在底层70中的部分被称为开口76B。硬遮罩层62因而露出。蚀刻遮罩64B也露出于开口76/76B。开口76B实质上可具有垂直侧壁。根据一些实施例，底层70包括CxHyOz。个别蚀刻气体可包括氧气，而聚合物形成气体可包括SO2。氧原子与硫原子反应，以形成含硫副产品，其充当为在开口76B侧壁上的侧壁保护层。通过选择合适的流速比例，其为聚合物形成气体的流速比蚀刻气体的流速，可达到垂直侧壁。
接着，参考图13A和13B，使用剩余的三层作为蚀刻遮罩，来蚀刻硬遮罩层62，且开口76延伸进入硬遮罩层62。开口76在硬遮罩层62中的部分也被称为开口76C。使用图案化的中间层72(若有剩余)和底层70作为蚀刻遮罩，来蚀刻硬遮罩层62。如图13A所示，当蚀刻硬遮罩层62时，蚀刻遮罩64B充当部分蚀刻遮罩，让开口76C被限制在蚀刻遮罩64B的露出部分之间。根据一些实施例，使用异向性蚀刻方法来进行蚀刻。蚀刻方法可选自反应式离子蚀刻(如电感式耦合等离子体或电容式耦合等离子体)、或其他类似方法。工艺气体可包括蚀刻气和聚合物形成气体。根据一些实施例，例如当硬遮罩层62包括硅氧化物时，蚀刻气体可包括含氟气体，如CF4、NF3、或其组合。聚合物形成气体可包括CHF3、CH2F2、CH3F、C4F6、C4F8、或其组合。工艺气体的压力可介于约5mTorr和200mTorr之间。在蚀刻期间的晶圆10的温度可介于约0℃和50℃之间。
也调整蚀刻工艺的条件，如工艺气体的种类和流速，让开口76C的侧壁倾斜。开口76C侧壁的倾斜角度α2可小于约89°，且可介于约85°和30°之间。通过选择合适的流速比例，其为聚合物形成气体的流速比蚀刻气体的流速，可达到所欲的倾斜角度α2。如此一来，开口76C的底宽度W4小于个别开口76C的顶宽度W3，其中宽度W3可与宽度W2(图11)接近。期望底宽度W4小于顶宽度W3，让后续形成的接触开口(图17B)的宽度比宽度W3更加减小。宽度差(W1-W2)(图11)和(W3-W4)(图13B)一起贡献于所得的接触开口的尺寸的整体收缩，无须使宽度差(W1-W2)和(W3-W4)中任意一个够大来导致工艺问题。于是，(W3-W4)没有太大也没有太小。根据本发明的一些实施例，宽度差(W3-W4)约介于12nm和20nm之间。根据一些实施例，宽度差(W3-W4)的调整是通过调整流速的流速比例FRPF2/FREG2，其中FRPF2是聚合物形成气体的流速，而FREG2是蚀刻气体的流速。根据一些实施例，流速比例FRPF2/FREG2是介于约0.5和3.0之间。此外，通过选择硬遮罩层62的合适厚度T1，来调整宽度差(W3-W4)。
在硬遮罩层62的蚀刻之后，移除中间层72，且例如在灰化工艺中，移除剩余的底层70，其使用臭氧或化学溶液，包括NH4OH、H2O2、和H2O(有时被称为标准清洁1(StandardClean 1,SC1)溶液)来进行。图14A和14B各别示出了所得的结构的俯视图和剖面图。
也如图14A和14B所示，一起使用硬遮罩64B和硬遮罩层62作为蚀刻遮罩来蚀刻硬遮罩层60，让开口76更延伸进入硬遮罩层60。开口76在底层70中的部分被称为开口76D。层间介电质49因而露出。开口76D实质上可具有垂直侧壁。根据一些实施例，调整蚀刻硬遮罩层60的蚀刻条件，让开口76D的侧壁为垂直的。
硬遮罩60的蚀刻方法可选自反应式离子蚀刻，如电感式耦合等离子体、电容式耦合等离子体、或其他类似方法。工艺气体可包括蚀刻气体和聚合物形成气体。根据一些实施例，例如，当硬遮罩层60包括钨碳化物，蚀刻气体可包括含氟气体，如CF4、NF3、或其组合。聚合物形成气体可包括Cl2、O2、或其组合。工艺气体的压力可介于约5mTorr和200mTorr之间。通过选择合适的流动比例，其为聚合物形成气体的流速比蚀刻气体的流速，可达到垂直侧壁。在蚀刻期间的晶圆10的温度可介于约0℃和50℃之间。
根据一些实施例，以容易调整聚合物形成的材料，来形成中间层72(图11)和硬遮罩层62(图13B)。于是，主要是在硬遮罩层62和中间层72中达到开口的收缩。以较不容易调整聚合物形成的材料，来形成底层70(图12)和硬遮罩层60(图14B)。于是，将在底层70和硬遮罩层60中的开口侧壁做为垂直的，来改善工艺控制。
图10A/10B至14A/14B示出了，在用来图案化硬遮罩层62和60的双重图案化工艺中的第一图案化工艺。图15A、15B、16A、和16B示出了，在用来图案化硬遮罩层62和60的双重图案化工艺中的第二图案化工艺。个别工艺示出于图19的工艺流程200中的工艺220。参考图15B，形成三层，包括底层80、中间层82、和上层84。底层80、中间层82、和上层84的材料和厚度基本上可各别与底层70、中间层72、和上层74(图10B)相同。图案化上层84，以形成开口86。如图15A和15B所示，部分蚀刻遮罩64A在开口86的正下方。第二图案化工艺的细节与第一图案化工艺的细节相似，如图11、12、13A、13B、14A、和14B所示，故不在此赘述。所得的结构如图16A、16B、和16C所示。在后续图示中的后续剖面图，其图号具有字母“C”者，除非另外指明，也是从在对应俯视图中与含C-C线段的垂直平面相同的平面所取得。如图16C所示，开口76’延伸进入硬遮罩层62和60。开口76’基本上具有相同宽度，其可等同于开口76的宽度W4。
如图16B所示，使用硬遮罩层62来保留在双重图案化工艺的两个图案化工艺中所形成的图案。再者，如图16A所示，使用蚀刻遮罩64来将长开口76和76’切割至较短的开口，因而将长源极/漏极接触插塞92(图18A和18B)切割至较短的接触插塞。
图11和15B示出，在上层74(图11)中的开口76和在上层84(图15B)中的开口86的宽度为W1。宽度W1可是能使用各别微影工艺(包括曝光工艺和显影工艺)达到的最小宽度。通过如图11、12、13A/13B、和14A/14B所示的工艺，减少开口76(和76’)的宽度至W4(图16B)。根据一些实施例，宽度差(W1-W4)可介于约29nm和37nm之间。若在单一层中，如中间层72(图11)和82(图15B)，达到宽度的收缩，可能有工艺问题，由于达到如此巨大宽度差异可导致显著的图案负载效应。根据本发明的一些实施例，收缩量是由两个以上的层共享，如在三层中的中间层和硬遮罩层62。工艺因此更加容易，并减少导致工艺问题的可能性。根据本发明的一些实施例，共享收缩量的两个层的各别层可分摊约总收缩量的1/3和2/3之间，让两个层都不会负担太大的收缩量。
接着，使用图案化的硬遮罩层62和60作为蚀刻遮罩，来蚀刻于下方的层间介电质49、蚀刻停止层47、层间介电质48、和接触蚀刻停止层46。个别工艺示出于图19的工艺流程200中的工艺222。所得的结构示出在图17A、17B、和17C中，其中在这些层46至49中的部分开口76和76’是源极/漏极接触开口。根据本发明的一些实施例，蚀刻遮罩64也充当作为部分蚀刻遮罩。在其他实施例中，在蚀刻这些层46至49之前，移除蚀刻遮罩64。蚀刻遮罩64的移除可是等向性(isotropic)或异向性，且可使用湿蚀刻或干蚀刻来进行。根据本发明的一些实施例，蚀刻工艺是干蚀刻工艺，其进行是使用CF4、SO2、HBr-Cl2-O2混合物、或HBr-Cl2-O2-CF2混合物等。或者，蚀刻工艺是湿蚀刻工艺，其进行是使用KOH、四甲铵氢氧化物(tetramethylammonium hydroxide)、CH3COOH、NH4OH、H2O2、异丙醇(isopropanol,IPA)、或例如HF、HNO3、和H2O的溶液。
图18A、18B、和18C示出了在源极/漏极硅化物区90和接触插塞92的形成中的俯视图和剖面图。个别工艺示出于图19的工艺流程200中的工艺224。根据一些实施例，沉积顺应金属层(未绘出)，以延伸进入接触开口76和76’(图17A和17B)。可以，例如钛，来形成金属层。接者，进行退火工艺，让金属层位在接触开口76和76’底部的部分与源极和漏极区42反应，来形成源极/漏极硅化物区90。在退火工艺之后，留下金属层的侧壁部分。根据一些实施例，可在退火工艺之前，在金属层上形成额外的导电氮化物层(未绘出)，如钛氮化物。然后以金属材料填充剩余的接触开口，其金属材料可以钨、钴、铜、铝、或其合金来形成。然后进行平坦化工艺，如化学机械抛光工艺，将所得的接触插塞92(包括92A和92B)的顶面齐平，其插塞包括金属层和金属材料。如图18A所示，接触插塞92A和92B被蚀刻遮罩64(图10A)切短，其遮罩定义了接触插塞92A和92B的一些末端部分。
参考图18A，示意地标记复数个晶体管94(包括94A和94B)，其中标注了源极/漏极区42和各别的栅极堆叠56。接触插塞92(如92A)可充当作为互连一些晶体管的源极/漏极区42和邻近晶体管的源极/漏极区42的互连结构。
本发明的实施例具有一些有利的特征。由于开口的收缩，接触插塞有利地具有小宽度。通过在复合层中收缩开口的尺寸，所得的开口可具有的宽度，其显著地小于微影工艺最小宽度。本发明实施例的收缩方法导致减少工艺问题的可能性，由于在各层中的收缩量没有过度。
根据本发明的一些实施例，一种方法包括形成第一硬遮罩层；于第一硬遮罩层上方形成第二硬遮罩层；形成三层，其三层包括：于第二硬遮罩层上方的底层，于底层上方的中间层，于中间层上方的图案化上层；使用图案化上层作为蚀刻遮罩，来蚀刻中间层，以将在图案化上层中的开口延伸进入中间层，其中在中间层中的开口具有第一部分，而第一部分具有第一顶宽度和小于第一顶宽度的第一底宽度；蚀刻底层，以将开口延伸进入底层；以及蚀刻第二硬遮罩层，以将开口延伸进入第二硬遮罩层，其中在第二硬遮罩层中的开口具有第二部分，而第二部分具有第二顶宽度和小于第二顶宽度的第二底宽度。在一实施例中，此方法还包括蚀刻第一硬遮罩层，以将开口延伸进入第一硬遮罩层，其中开口在第一硬遮罩层中的一部分实质上具有垂直和笔直侧壁；以及蚀刻于第一硬遮罩层下方的下方层，以将开口延伸进入下方层。在一实施例中，此方法还包括填充导电材料进入下方层，以形成接触插塞。在一实施例中，此方法还包括在形成接触插塞之后，移除第一硬遮罩层和第二硬遮罩层的剩余部分。在一实施例中，此方法还包括在形成三层之前，于第二硬遮罩层上方形成图案化蚀刻遮罩，其中当蚀刻第二硬遮罩层，以将开口延伸进入第二硬遮罩层时，蚀刻遮罩将开口分离成两个部分。在一实施例中，第一顶宽度和第一底宽度具有第一差值，第二顶宽度和第二底宽度具有第二差值，而第一顶宽度和第二底宽度具有第三差值，且第一差值约在第三差值的1/3和2/3之间。在一实施例中，开口在底层中的一部分实质上具有垂直和笔直侧壁。
根据本发明的一些实施例，一种方法包括于晶体管的源极/漏极区上方形成层间介电质；于层间介电质上方形成第一硬遮罩层；于第一硬遮罩层上方形成三层，包括于第一硬遮罩层上方形成底层，于底层上方形成中间层，于中间层上方形成上层，其中上层具有一开口；使用上层作为蚀刻遮罩来蚀刻中间层和底层，其中开口延伸进入中间层和底层，其中开口的宽度从在中间层顶面层级的第一顶宽度收缩至在底层底面层级的第一底宽度；蚀刻第一硬遮罩层，其中开口延伸进入第一硬遮罩层，其中开口的宽度从第一底宽度收缩至在第一硬遮罩层底面层级的第二底宽度；以及使用第一硬遮罩层作为蚀刻遮罩的一部分来蚀刻层间介电质，以将开口延伸进入层间介电质。在一实施例中，此方法还包括在层间介电质中形成接触插塞，其中电性耦合接触插塞至源极/漏极区。在一实施例中，此方法还包括于层间介电质上方形成第二硬遮罩层，其中第二硬遮罩层是在第一硬遮罩层下方；以及在蚀刻层间介电质之前，蚀刻第二硬遮罩层，其中开口延伸进入第二硬遮罩层，且开口在第二硬遮罩层中的一部分实质上具有垂直侧壁。在一实施例中，中间层包括硅氧氮化物，且使用工艺气体来蚀刻中间层，其气体包括：含氟气体选自CF4、NF3、和其组合所组成的族群；以及聚合物形成气体选自CHF3、CH2F2、CH3F、C4F6、C4F8、和其组合所组成的族群。在一实施例中，此方法还包括在形成三层前，于第一硬遮罩层上方形成图案化蚀刻遮罩，其中当蚀刻第一硬遮罩层，以将开口延伸进入第一硬遮罩层时，图案化的蚀刻遮罩将开口分离成两部分。在一实施例中，形成图案化的蚀刻遮罩包括形成硅层。在一实施例中，第一顶宽度和第一底宽度之间的差值约在第一顶宽度和第二底宽度之间的差值的1/3和2/3之间。
根据本发明的一些实施例，一种方法包括于层间介电质上方形成第一硬遮罩层；于第一硬遮罩层上方形成第二硬遮罩层；形成三层，其三层包括：于第二硬遮罩层上方的底层，于底层上方的中间层，以及于中间层上方的图案化上层，其中在图案化上层中形成开口，且开口具有顶宽度；以及将开口延伸进入中间层、底层、第二硬遮罩层、和第一硬遮罩层，其中开口在第二硬遮罩层中的一部分具有第一顶宽度和小于第一顶宽度的第一底宽度，以及开口在第一硬遮罩层中的一部分具有顶宽度和与顶宽度相等的底宽度。在一实施例中，此方法还包括使用第一硬遮罩层和第二硬遮罩层之一作为蚀刻遮罩，来蚀刻下方层。在一实施例中，第一底宽度比第一顶宽度小约12nm和20nm之间的差值。在一实施例中，开口在中间层中的一部分具有第二顶宽度和小于第二顶宽度的第二底宽度，且第一顶宽度比第一底宽度大第一差值，第二顶宽度比第二底宽度大第二差值，且第一差值是第一差值和第二差值的总和的约1/3和2/3之间。
以上概述数个实施例的部件，以便在本发明实施例所属技术领域中技术人员可以更加理解本发明实施例的观点。在本发明实施例所属技术领域中技术人员应理解，他们能轻易地以本发明实施例为基础，设计或修改其他工艺和结构，以达到与在此介绍的实施例相同的目的及/或优势。在本发明实施例所属技术领域中技术人员也应理解，此类等效的结构并无悖离本发明实施例的构思与范围，且他们能在不违背本发明实施例的构思和范围下，做各式各样的改变、取代和替换。

Claims (10)

1.一种集成电路结构的形成方法，包括：
形成一第一硬遮罩层；
形成一第二硬遮罩层于该第一硬遮罩层上方；
形成一三层，该三层包括：
一底层于该第二硬遮罩层上方；
一中间层于该底层上方；以及
一图案化上层于该中间层上方；
用该图案化上层作为一蚀刻遮罩来蚀刻该中间层，以将在该图案化上层中的一开口延伸进入该中间层，其中该开口具有在该中间层中的一第一部分，且该第一部分具有一第一顶宽度和小于该第一顶宽度的一第一底宽度；
蚀刻该底层，以将该开口延伸进入该底层，其中在该底层中的该开口的一部分实质上具有垂直侧壁；以及
蚀刻该第二硬遮罩层，以将该开口延伸进入该第二硬遮罩层，其中在该第二硬遮罩层中的该开口具有一第二部分，且该第二部分具有一第二顶宽度和小于该第二顶宽度的一第二底宽度。
2.如权利要求1所述的集成电路结构的形成方法，还包括：
蚀刻该第一硬遮罩层，以将该开口延伸进入该第一硬遮罩层，其中在该第一硬遮罩层中的该开口的一部分实质上具有垂直侧壁；以及
蚀刻在该第一硬遮罩层下方的一下方层，以将该开口延伸进入该下方层。
3.如权利要求1所述的集成电路结构的形成方法，还包括在形成该三层前，于该第二硬遮罩层上方形成一图案化蚀刻遮罩，其中当蚀刻该第二硬遮罩层，以将该开口延伸进入该第二硬遮罩层时，该蚀刻遮罩将该开口分离成两部分。
4.如权利要求1所述的集成电路结构的形成方法，其中该第一顶宽度和该第一底宽度具有一第一差值，该第二顶宽度和该第二底宽度具有一第二差值，且该第一顶宽度和该第二底宽度具有一第三差值，且该第一差值是约在该第三差值的1/3和2/3之间。
5.如权利要求1所述的集成电路结构的形成方法，其中该开口的该第一部分的侧壁比该实质上垂直侧壁较为倾斜。
6.一种集成电路结构的形成方法，包括：
形成一层间介电质于一晶体管的一源极/漏极区上方；
形成一第一硬遮罩层于该层间介电质上方；
形成一三层于该第一硬遮罩层上方，包括：
形成一底层于该第一硬遮罩层上方；
形成一中间层于该底层上方；以及
形成一上层于该中间层上方，其中该上层具有一开口；
用该上层作为一蚀刻遮罩，以蚀刻该中间层和该底层，其中该开口延伸进入该中间层和该底层，其中该开口的宽度从在该中间层的一顶面层级的一第一顶宽度收缩至在该底层的一底面层级的一第一底宽度，且该底层实质上具有垂直侧壁；
蚀刻该第一硬遮罩层，其中该开口延伸进入该第一硬遮罩层，其中该开口的宽度从该第一底宽度收缩至在该第一硬遮罩层的一底面层级的一第二底宽度；以及
使用该第一硬遮罩层作为一蚀刻遮罩的一部分来蚀刻该层间介电质，以将该开口延伸进入该层间介电质。
7.如权利要求6所述的集成电路结构的形成方法，其中该第一硬遮罩层具有在约15nm和60nm之间的厚度，且在该第一硬遮罩层中的该开口的一部分具有小于约89°的倾斜角度。
8.如权利要求6所述的集成电路结构的形成方法，其中该中间层包括氮氧化硅，且蚀刻该中间层所使用的一工艺气体包括：
一含氟气体，选自CF4、NF3、及其组合所组成的族群；以及
一聚合物形成气体，选自CHF3、CH2F2、CH3F、C4F6、C4F8、及其组合所组成的族群。
9.一种集成电路结构的形成方法，包括：
形成一第一硬遮罩层于一层间介电质上方；
形成一第二硬遮罩层于该第一硬遮罩层上方；
形成一三层，该三层包括：
一底层于该第二硬遮罩层上方；
一中间层于该底层上方；以及
一图案化上层于该中间层上方，其中在该图案化上层中形成一开口；以及
将该开口延伸进入该中间层、该底层、该第二硬遮罩层、和该第一硬遮罩层，其中在该第二硬遮罩层中的该开口的一第一部分具有一第一顶宽度和小于该第一顶宽度的一第一底宽度，以及在该第一硬遮罩层中的该开口的一部分具有一顶宽度和与该顶宽度相等的一底宽度。
10.如权利要求9所述的集成电路结构的形成方法，其中在该中间层中的该开口的一第二部分具有一第二顶宽度和小于该第二顶宽度的一第二底宽度，且该第一顶宽度比该第一底宽度大一第一差值，该第二顶宽度比该第二底宽度大一第二差值，且该第一差值是该第一差值和该第二差值的总和的约1/3和2/3之间。
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