CN111125790A - SRAM PUF integrated circuit - Google Patents
SRAM PUF integrated circuit Download PDFInfo
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- CN111125790A CN111125790A CN201811283656.3A CN201811283656A CN111125790A CN 111125790 A CN111125790 A CN 111125790A CN 201811283656 A CN201811283656 A CN 201811283656A CN 111125790 A CN111125790 A CN 111125790A
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- 238000000034 method Methods 0.000 claims abstract description 19
- 230000008569 process Effects 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000012545 processing Methods 0.000 abstract description 6
- 230000004044 response Effects 0.000 description 4
- 238000000342 Monte Carlo simulation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- OUXCBPLFCPMLQZ-WOPPDYDQSA-N 4-amino-1-[(2r,3s,4s,5r)-4-hydroxy-5-(hydroxymethyl)-3-methyloxolan-2-yl]-5-iodopyrimidin-2-one Chemical compound C[C@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C(=O)N=C(N)C(I)=C1 OUXCBPLFCPMLQZ-WOPPDYDQSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009024 positive feedback mechanism Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Static Random-Access Memory (AREA)
Abstract
According to one aspect of the invention, an SRAM PUF integrated circuit is disclosed, which comprises only a single type of transistor, only NMOS transistors or only PMOS transistors. All transistors are processed by the same process flow, so that the transistors in the circuit are prevented from being formed by different processing process flows, and the PUF circuit depending on random difference in the processing and manufacturing processes has better stability.
Description
Technical Field
This patent relates to the integrated circuit field, especially relates to a SRAM PUF integrated circuit.
Background
A PUF (Physical Unclonable Function) is an integrated circuit security protection technology, and has the characteristics of simple principle and structure, low power consumption, Physical Unclonable and unpredictable properties, and the like.
The core idea of PUFs is the extraction of "random differences", or "process differences", that exist in physical objects. In reality, each physical object introduces some random differences (variations) inside the physical object due to the limitations of the manufacturing process during the manufacturing process. PUFs are capable of extracting and characterizing random differences that exist in a physical object, thereby generating unique identification or verification information (response) based on the physical object, with characteristics of tamper resistance, unclonability, unpredictability, and the like.
PUF circuits are divided into delay-type PUFs and memory-type PUFs. Delay-type PUFs work by measuring random differences between comparison gates/transistors or between connection lines, or by measuring random differences in signal transmission delay. Storage-like PUFs are implemented using random differences in certain electrical characteristics (mainly current) of symmetric silicon devices, device mismatches also referred to as "bistable memory elements", which are generally simpler in structure but with higher requirements on symmetry.
The PUF should have uniqueness and reliability. Uniqueness refers to the magnitude of the difference between responses generated by multiple PUF entities (chips) that are structurally identical under the same stimulus. Reliability refers to the probability of bit jumps occurring in the responses generated by the same PUF chip under different stimuli under the same test conditions.
An SRAM (Static Random Access Memory) PUF is one type of Memory PUF, and has the advantages of simple structure and low power consumption. Conventional SRAM PUFs are formed end-to-end using inverters. When the SRAM unit is powered on, the circuit enters one of two stable working states from a metastable state, and the selected state of each SRAM unit is random and stable when the circuit enters the stable state from the metastable state.
The traditional SRAM PUF circuit has the stability problem: in the current branch of the traditional SRAM PUF, an n tube and a p tube exist at the same time. Since n-tubes and p-tubes are formed by different process steps when processing integrated circuits, the idea of a PUF is to extract "processing differences" that exist in the physical object, which leads to a certain probability of errors in the SRAM PUF. Specifically, the temperature characteristics and the voltage-current characteristics of the n-tube and the p-tube are different, which causes different results of the same SRAM PUF under different temperatures, voltages and currents with a certain probability. That is, the probability of bit jump occurring in the response generated by the same PUF chip under the same excitation test condition is increased, and the reliability is deteriorated.
Therefore, the invention provides the SRAM PUF integrated circuit with high reliability.
Disclosure of Invention
According to one aspect of the invention, an SRAM PUF integrated circuit is disclosed that includes only a single type of transistor.
According to another aspect of the invention, only the NMOS transistor is included in the integrated circuit of the invention.
According to another aspect of the invention, only PMOS tubes are included in the integrated circuit of the invention.
According to another aspect of the invention, the integrated circuit of the invention comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; the grid electrode of the first NMOS tube, the drain electrode of the third NMOS tube, the source electrode of the fourth NMOS tube, the grid electrode of the fifth NMOS tube and the grid electrode of the eighth NMOS tube are electrically connected to form a first connecting point; the drain electrode of the first NMOS tube, the source electrode of the second NMOS tube, the grid electrode of the third NMOS tube, the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube are electrically connected to form a second connection point; the grid electrode of the second NMOS tube, the drain electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube are electrically connected to form a third connection point; a grid electrode of the fourth NMOS tube, a drain electrode of the seventh NMOS tube and a source electrode of the eighth NMOS tube are electrically connected to form a fourth connection point; the drain electrode of the second NMOS tube, the drain electrode of the fourth NMOS tube, the drain electrode of the sixth NMOS tube and the drain electrode of the eighth NMOS tube are connected with a power supply; the source electrode of the first NMOS tube, the source electrode of the third NMOS tube, the source electrode of the fifth NMOS tube and the source electrode of the seventh NMOS tube are grounded.
According to another aspect of the invention, the integrated circuit of the invention comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor and an eighth PMOS transistor; a grid electrode of the second PMOS tube, a source electrode of the third PMOS tube, a drain electrode of the fourth PMOS tube, a grid electrode of the sixth PMOS tube and a grid electrode of the seventh PMOS tube are electrically connected to form a first connecting point; the source electrode of the first PMOS tube, the drain electrode of the second PMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the eighth PMOS tube are electrically connected to form a second connection point; the grid electrode of the first PMOS tube, the source electrode of the fifth PMOS tube and the drain electrode of the sixth PMOS tube are electrically connected to form a third connection point; a grid electrode of the third PMOS tube, a source electrode of the seventh PMOS tube and a drain electrode of the eighth PMOS tube are electrically connected to form a fourth connection point; the source electrode of the second PMOS tube, the source electrode of the fourth PMOS tube, the source electrode of the sixth PMOS tube and the source electrode of the eighth PMOS tube are connected with a power supply; the drain electrode of the first PMOS tube, the drain electrode of the third PMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the seventh PMOS tube are grounded.
The PUF circuit has the advantages that the full NMOS transistor or the full PMOS transistor is used for realizing the SRAM PUF circuit, all transistors in the circuit are completed in the same process step, the transistors in the circuit are prevented from being formed by different processing process steps, and the PUF circuit depending on random difference in the processing and manufacturing processes has better stability, so that the PUF circuit has advancement.
Drawings
FIG. 1 is a schematic diagram of an all NMOS transistor SRAM PUF circuit according to one embodiment of the present invention;
FIG. 2 is a schematic diagram of a full PMOS transistor SRAM PUF circuit according to another embodiment of the present invention;
FIG. 3 is a voltage diagram illustrating a power-up process of the full NMOS transistor circuit of FIG. 1;
fig. 4 is a graph of monte carlo simulation results of the all NMOS transistor circuit of fig. 1.
Detailed Description
Embodiments of the present invention are described in more detail below with reference to the accompanying drawings of the invention.
The method has two forms of a full NMOS transistor circuit and a full PMOS transistor circuit:
referring to fig. 1, an SRAM PUF circuit formed from 8 NMOS tubes is shown, according to a particular embodiment of the present invention.
In fig. 1, 8 NMOS transistors of the SRAM PUF circuit are denoted by N1-N8; six nodes of the circuit are represented by a1-a 6: wherein the a5 node is power VDD, the a6 node is ground GND, the a1 and a2 are a pair of nodes of opposite voltage, and the a3 and a4 are another pair of nodes of opposite voltage.
When the voltage of a1 is 0, a2 is VDD-Vthn, a3 is 0, and a4 is VDD-Vthn, whereas when the voltage of a1 is VDD-Vthn, a2 is 0, a3 is VDD-Vthn, and a4 is 0. Where Vthn denotes the NMOS transistor threshold voltage absolute value.
The full NMOS transistor circuit is of a symmetrical structure, and the connection mode of transistors is as follows: the source of the N1 tube is connected with a6, the grid is connected with a1, and the drain is connected with a 2; the source of the N2 tube is connected with a2, the grid is connected with a3, and the drain is connected with a 5; the source of the N3 tube is connected with a6, the grid is connected with a2, and the drain is connected with a 1; the source of the N4 tube is connected with a1, the grid is connected with a4, and the drain is connected with a 5; the source of the N5 tube is connected with a6, the grid is connected with a1, and the drain is connected with a 3; the source of the N6 tube is connected with a3, the grid is connected with a2, and the drain is connected with a 5; the source of the N7 tube is connected with a6, the grid is connected with a2, and the drain is connected with a 4; the N8 tube is connected with a source a4, a gate a1 and a drain a 5.
That is, the gate of the N1 transistor, the drain of the N3 transistor, the source of the N4 transistor, the gate of the N5 transistor, and the gate of the N8 transistor are electrically connected to form a node a 1; the drain of the N1 tube, the source of the N2 tube, the gate of the N3 tube, the gate of the N6 tube and the gate of the N7 tube are electrically connected to form a node a 2; the grid electrode of the N2 tube, the drain electrode of the N5 tube and the source electrode of the N6 tube are electrically connected to form a node a 3; the grid electrode of the N4 tube, the drain electrode of the N7 tube and the source electrode of the N8 tube are electrically connected to form a node a 4; the drain electrode of the N2 tube, the drain electrode of the N4 tube, the drain electrode of the N6 tube and the drain electrode of the N8 tube are connected with a power supply VDD, namely a connection node a 5; the source electrode of the N1 tube, the source electrode of the N3 tube, the source electrode of the N5 tube and the source electrode of the N7 tube are grounded, namely, the node a6 is connected.
Referring to fig. 2, fig. 2 shows an SRAM PUF circuit formed from 8 PMOS pipes according to another embodiment of the present invention.
In FIG. 2, 8 PMOS transistors of the circuit are represented by P1-P8; six nodes of the circuit are represented by b1-b 6: where the b5 node is power VDD, the b6 node is ground GND, b1 and b2 are a pair of nodes of opposite voltage, and b3 and b4 are another pair of nodes of opposite voltage.
When the voltage of b1 is VDD, b2 is Vthp, a3 is VDD, and a4 is Vthp, whereas when the voltage of b1 is Vthp, b2 is VDD, a3 is Vthp, and a4 is VDD. Here Vthp represents the PMOS transistor threshold voltage absolute value.
The full PMOS tube circuit is of a symmetrical structure, and the connection mode of the transistors is as follows: the source of the P1 tube is connected with b2, the grid is connected with b3, and the drain is connected with b 6; the source of the P2 tube is connected with b5, the grid is connected with b1, and the drain is connected with b 2; the source of the P3 tube is connected with b1, the grid is connected with b4, and the drain is connected with b 6; the source of the P4 tube is connected with b5, the grid is connected with b2, and the drain is connected with b 1; the source of the P5 tube is connected with b3, the grid is connected with b2, and the drain is connected with b 6; the source of the P6 tube is connected with b5, the grid is connected with b1, and the drain is connected with b 3; the source of the P7 tube is connected with b4, the grid is connected with b1, and the drain is connected with b 6; the P8 tube is connected with the source b5, the gate b2 and the drain b 4.
That is, the gate of the P2 transistor, the source of the P3 transistor, the drain of the P4 transistor, the gate of the P6 transistor, and the gate of the P7 transistor are electrically connected to form a connection point a 1; the source electrode of the P1 tube, the drain electrode of the P2 tube, the grid electrode of the P4 tube, the grid electrode of the P5 tube and the grid electrode of the P8 tube are electrically connected to form a connection point a 2; the grid electrode of the P1 tube, the source electrode of the P5 tube and the drain electrode of the P6 tube are electrically connected to form a connection point a 3; the grid electrode of the P3 tube, the source electrode of the P7 tube and the drain electrode of the P8 tube are electrically connected to form a connection point a 4; the source electrode of the P2 tube, the source electrode of the P4 tube, the source electrode of the P6 tube and the source electrode of the P8 tube are connected with a power supply VDD, namely a connection point b 5; the drain electrode of the P1 tube, the drain electrode of the P3 tube, the drain electrode of the P5 tube and the drain electrode of the P7 tube are grounded, namely, a connection point b 6.
The circuit working principle of the invention is as follows:
the working principle of the single type of transistor SRAM PUF circuit is as follows: the circuit has two stable working states, when the circuit VDD is electrified, the circuit enters one of the two stable working states from a metastable state stage of the circuit, and the selected state of each unit is random and stable when the circuit enters the stable state from the metastable state.
The full NMOS transistor circuit is analyzed firstly, two stable states of the full NMOS transistor circuit are SN1 and SN2, and the full NMOS transistor circuit enters one of the two stable states due to process random errors after being electrified.
One stable state SN1 of the all-NMOS transistor circuit is:
1) because of process variations during the manufacturing process, the voltage at the a1 node is higher than the voltage at the a2 node when VDD is powered up.
2) Resulting in the turning on of the N1, N5, and N8 transistors and the turning off of the N3, N7, and N6 transistors.
3) N8 is on, N7 is off, so that the a4 node is high; n5 is open and N6 is closed, leaving the a3 node low.
4) The a4 node is high, turning N4 on while N3 is off, making the a1 node higher; the a3 node is low, turning N2 off, while N1 is on, making the a2 node lower. Positive feedback is achieved.
5) The positive feedback causes the voltage at node a1 above node a2 to be amplified very quickly and the circuit quickly reaches a steady state where the voltage at a1 is high and the voltage at a2 is low.
Another steady state SN2 for an all-NMOS transistor circuit is:
1) because of process variations during the manufacturing process, the voltage at the a2 node is higher than the voltage at the a1 node when VDD is powered up.
2) Resulting in the turning off of the N1, N5, and N8 transistors and the turning on of the N3, N7, and N6 transistors.
3) N8 is off, N7 is on, leaving the a4 node low; n5 is off and N6 is on, leaving the a3 node high.
4) The a4 node is low, turning off N4 while N3 is on, making the a1 node lower; the a3 node is high, turning N2 on, while N1 is off, making the a2 node higher. Positive feedback is achieved.
5) The positive feedback causes the voltage at node a2 above node a1 to be amplified very quickly and the circuit quickly reaches a steady state where the voltage at a2 is high and the voltage at a1 is low.
Because there is a threshold loss in using n-pipe to transmit high level, the high level is VDD-Vthn; the low level is 0.
Now analyzing the full PMOS transistor circuit, the two stable states of the full PMOS transistor circuit are SP1 and SP2, and the circuit will enter one of the two stable states due to the random process error after being powered on.
One steady state SP1 of the all PMOS transistor circuit is:
1) because of process variations during the manufacturing process, the b1 node voltage is higher than the b2 node voltage when VDD is powered up.
2) Resulting in the P2, P6, and P7 transistors turning off and the P4, N5, and N8 transistors turning on.
3) P8 is open and P7 is closed, leaving the b4 node high; p5 is open and P6 is closed, leaving the b3 node low.
4) The b4 node is high, causing P3 to be off while P4 is on, causing the b1 node to be higher; the b3 node is low, causing P1 to turn on, while P2 turns off, causing the b2 node to be at a lower voltage. Positive feedback is achieved.
5) The positive feedback causes the voltage at node b1 above node b2 to be amplified very quickly and the circuit quickly reaches a steady state where the b1 voltage is high and the b2 voltage is low.
One steady state SP2 of the all PMOS transistor circuit is:
1) because of process variations during the manufacturing process, the b2 node voltage is higher than the b1 node voltage when VDD is powered up.
2) Resulting in the P2, P6, and P7 transistors turning on and the P4, N5, and N8 transistors turning off.
3) P8 is off and P7 is on, leaving the b4 node low; p5 is off and P6 is on, leaving the b3 node high.
4) The b4 node is low, causing P3 to turn on while P4 turns off, causing the b1 node to go lower; the b3 node is high, causing P1 to be off, while P2 is on, causing the b2 node to be higher in voltage. Positive feedback is achieved.
5) The positive feedback causes the voltage at node b2 above node b1 to be amplified very quickly and the circuit quickly reaches a steady state where the b2 voltage is high and the b1 voltage is low.
Because there is a threshold loss in using the PMOS transistor to transmit the low level, the low level is Vthp; the high level is VDD.
The circuit realized according to the principle of the invention has obvious difference between the generated high voltage and the generated low voltage and can be identified.
According to one embodiment of the present invention, an SMIC 0.13um process is used to fabricate an integrated circuit. The circuit structure adopts an all-NMOS tube SRAM PUF circuit as shown in figure 1.
Fig. 3 is a simulation result of an all NMOS transistor SRAM PUF circuit, where curve c1 is the voltage of the a1 node, curve c2 is the voltage of the a2 node, and curve c3 is the voltage of the VDD a5 node. As can be seen from fig. 2, the VDD voltage rises from 0V to 1V, and the curve c1 and the curve c2 also rise, and because of the slight difference between the voltages of the curve c1 and the curve c2 caused by the process difference, the difference is amplified by the positive feedback mechanism, and finally the curve c1 and the curve c2 will be separated, where the curve c1 is finally a low voltage and the curve c2 is finally a high voltage. The low voltage value is 0V, and the high voltage value is about 0.7V.
Fig. 4 shows the result of the monte carlo simulation of the all-NMOS transistor circuit shown in fig. 1, wherein the monte carlo simulation parameter is the end-of-voltage value of the curve c 1. A total of 1024 simulations were performed. In fig. 4, the horizontal axis represents voltage and the vertical axis represents frequency, and fig. 4 counts the frequency at which the voltage end value of the curve c1 falls within the voltage range shown in the horizontal axis. As can be seen from FIG. 4, the end-of-voltage value of curve c1 falls approximately half of the voltage range at voltage 0 and half of the voltage range at 0.5V-1V. It can be seen that the two voltages of curve c1 are clearly different from each other.
In summary, this embodiment proves that the reflected power of the uhf RFID tag can be enhanced by using the method of the present invention.
The above-described embodiments are merely examples of the present invention, and although the embodiments of the present invention and the accompanying drawings are disclosed for illustrative purposes, those skilled in the art will understand that: various substitutions, changes and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the disclosure of the embodiment and the drawings.
Claims (8)
1. An SRAM PUF integrated circuit, comprising only a single type of transistor.
2. The SRAM PUF integrated circuit of claim 1, wherein only NMOS transistors are included in the SRAM PUF integrated circuit.
3. The SRAM PUF integrated circuit of claim 1, wherein only PMOS transistors are included in the SRAM PUF integrated circuit.
4. The SRAM PUF integrated circuit of any one of claims 1-3, wherein the SRAM PUF integrated circuit is in a symmetric structure.
5. The SRAM PUF integrated circuit of claim 2, wherein the SRAM PUF integrated circuit comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; the grid electrode of the first NMOS tube, the drain electrode of the third NMOS tube, the source electrode of the fourth NMOS tube, the grid electrode of the fifth NMOS tube and the grid electrode of the eighth NMOS tube are electrically connected to form a first connecting point; the drain electrode of the first NMOS tube, the source electrode of the second NMOS tube, the grid electrode of the third NMOS tube, the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube are electrically connected to form a second connection point; the grid electrode of the second NMOS tube, the drain electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube are electrically connected to form a third connection point; a grid electrode of the fourth NMOS tube, a drain electrode of the seventh NMOS tube and a source electrode of the eighth NMOS tube are electrically connected to form a fourth connection point; the drain electrode of the second NMOS tube, the drain electrode of the fourth NMOS tube, the drain electrode of the sixth NMOS tube and the drain electrode of the eighth NMOS tube are connected with a power supply; the source electrode of the first NMOS tube, the source electrode of the third NMOS tube, the source electrode of the fifth NMOS tube and the source electrode of the seventh NMOS tube are grounded.
6. The SRAM PUF integrated circuit of claim 2 or 5, wherein NMOS transistors used in the SRAM PUF integrated circuit are processed by the same process flow.
7. The SRAM PUF integrated circuit of claim 3, wherein the SRAM PUF integrated circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor; a grid electrode of the second PMOS tube, a source electrode of the third PMOS tube, a drain electrode of the fourth PMOS tube, a grid electrode of the sixth PMOS tube and a grid electrode of the seventh PMOS tube are electrically connected to form a first connecting point; the source electrode of the first PMOS tube, the drain electrode of the second PMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the eighth PMOS tube are electrically connected to form a second connection point; the grid electrode of the first PMOS tube, the source electrode of the fifth PMOS tube and the drain electrode of the sixth PMOS tube are electrically connected to form a third connection point; a grid electrode of the third PMOS tube, a source electrode of the seventh PMOS tube and a drain electrode of the eighth PMOS tube are electrically connected to form a fourth connection point; the source electrode of the second PMOS tube, the source electrode of the fourth PMOS tube, the source electrode of the sixth PMOS tube and the source electrode of the eighth PMOS tube are connected with a power supply; the drain electrode of the first PMOS tube, the drain electrode of the third PMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the seventh PMOS tube are grounded.
8. The SRAM PUF integrated circuit of claim 3 or 7, wherein NMOS transistors used in the SRAM PUF integrated circuit are processed by the same process flow.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102710251A (en) * | 2012-05-28 | 2012-10-03 | 宁波大学 | Physical unclonable functions (PUF) circuit unit |
| US20150028847A1 (en) * | 2013-07-29 | 2015-01-29 | Nxp B.V. | Puf method using and circuit having an array of bipolar transistors |
| CN105336362A (en) * | 2015-12-10 | 2016-02-17 | 中北大学 | Radiation hardened static random access memory |
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- 2018-10-31 CN CN201811283656.3A patent/CN111125790B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102710251A (en) * | 2012-05-28 | 2012-10-03 | 宁波大学 | Physical unclonable functions (PUF) circuit unit |
| US20150028847A1 (en) * | 2013-07-29 | 2015-01-29 | Nxp B.V. | Puf method using and circuit having an array of bipolar transistors |
| CN105336362A (en) * | 2015-12-10 | 2016-02-17 | 中北大学 | Radiation hardened static random access memory |
Non-Patent Citations (1)
| Title |
|---|
| 魏欣;孙;: "一种基于增强型NMOS反相器的低错误率只读PUF" * |
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