CN111124780B - UPI Link speed reduction test method, system, terminal and storage medium - Google Patents
UPI Link speed reduction test method, system, terminal and storage medium Download PDFInfo
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- 238000004088 simulation Methods 0.000 claims abstract 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The invention provides a UPI Link simulation deceleration test method, a system, a terminal and a storage medium, comprising the following steps: injecting UPI DataLane Failover error into the appointed UPI port, and simultaneously recording the speed limit value of the error port by the BIOS; checking whether a web reported error log and a UPI speed reduction related log appear, and restarting the system if the web reported error log and the UPI speed reduction related log appear; capturing PCIE bus corresponding to a UPI port with wrong injection through an lspci command, and acquiring a UPI Link speed value of the corresponding PCIE bus; and comparing whether the UPI Link speed value is consistent with the speed limit value of the speed limit value recorded by the BIOS, and if so, passing the test. The invention injects the UPI DataLane Failover error into the UPI Port to cause the channel to break down, thereby achieving the purpose of reducing the speed of the UPI Link and verifying whether the working mechanism of the UPI Link is normal at the moment.
Description
Technical Field
The invention relates to the technical field of servers, in particular to a UPI Link speed reduction testing method, a UPI Link speed reduction testing system, a UPI Link speed reduction testing terminal and a UPI Link speed reduction testing storage medium.
Background
With the rapid development of computer technology, the server gradually becomes a high-performance computer in the network platform, and the application and the technological progress of the server are developed continuously, so that the performance of the server is required to be upgraded continuously. In the server work, the UPI is a bus linked by the CPUs, and the high transmission rate can be achieved only if the UPI has enough bandwidth and strong flexibility, so that a data communication loading module between the CPUs is stronger. The invention discloses a UPI Link function test method and a UPI Link function test system, which are used for improving a UPI Link function test mechanism and further improving the performance of a server on the basis of explaining the UPI Link deceleration principle.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present invention provides a method, a system, a terminal and a storage medium for UPI Link speed reduction testing, so as to solve the above-mentioned technical problems.
In a first aspect, the present invention provides a UPI Link speed reduction test method, including:
injecting UPI DataLane Failover error into the appointed UPI port, and simultaneously recording the speed limit value of the error port by the BIOS;
checking whether a web reported error log and a UPI speed reduction related log appear, and restarting the system if the web reported error log and the UPI speed reduction related log appear;
capturing PCIE bus corresponding to a UPI port with wrong injection through an lspci command, and acquiring a UPI Link speed value of the corresponding PCIE bus;
and comparing whether the UPI Link speed value is consistent with the speed limit value of the speed limit value recorded by the BIOS, and if so, passing the test.
Further, the method further comprises:
setting an option System Errors = Enable in the BIOS Setup to ensure that the log can be recorded under the web;
the Link L0p supported power save state is set.
Further, the method further comprises:
looking at the UPI link status ensures that all channels of UPI between CPUs are connected.
Further, the method further comprises:
and checking whether the state of the fault injection channel is displayed as disconnected or not, and if not, sending a test fault prompt.
In a second aspect, the present invention provides a UPI Link deceleration test system, including:
the error injection unit is configured to inject a UPI DataLane failure over error to a specified UPI port, and the BIOS records a speed limit value of the error injection port;
the error checking unit is configured for checking whether a web reported error log and a UPI speed reduction related log appear or not, and if so, restarting the system;
the speed capturing unit is configured to capture the PCIE bus corresponding to the UPI port which is wrongly annotated through an lspci command, and acquire a UPI Link speed value of the corresponding PCIE bus;
and the speed comparison unit is configured for comparing whether the UPI Link speed value is consistent with the speed limit value of the speed limit value recorded by the BIOS, and if so, the test is passed.
Further, the system further comprises:
the option setting unit is configured to set option System Errors = Enable in the BIOS Setup, and ensure that the log can be recorded under the web;
and the state setting unit is configured to set a Link L0p supporting power-saving state.
Further, the system further comprises:
through the checking unit, the UPI link status is checked, and all channels of the UPI between the CPUs are connected.
Further, the system further comprises:
and the error injection checking unit is configured for checking whether the error injection channel state is displayed as disconnected or not, and if not, sending a test error prompt.
In a third aspect, a terminal is provided, including:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is used for calling and running the computer program from the memory so as to make the terminal execute the method of the terminal.
In a fourth aspect, a computer storage medium is provided having stored therein instructions that, when executed on a computer, cause the computer to perform the method of the above aspects.
The beneficial effect of the invention is that,
the invention provides a UPI Link speed reduction test method, a system, a terminal and a storage medium, wherein a communication Link is formed by linking a CPU through a UPI port, the rate index value of the Link Frequency Select is 9.6GT/S or 10.4GT/S, when the rate is lower than the index value, the performance of a server is seriously influenced, but the invention leads UPI # lane to have a fault by error injection, prevents the UPI Link from being capable of operating and transmitting data in full width, leads to error report and downtime on a VGA interface, and simultaneously displays uncorrectable ECC logs related to UPI and logs related to UPI Link speed reduction under a web. The invention injects the UPI DataLane Failover error into the UPI Port to cause the channel to break down, thereby achieving the purpose of reducing the speed of the UPI Link and verifying whether the working mechanism of the UPI Link is normal at the moment.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.
FIG. 2 is a schematic block diagram of a system of one embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following explains key terms appearing in the present invention.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. The execution main body in fig. 1 may be a UPI Link speed reduction test system.
As shown in fig. 1, the method includes:
and 140, comparing whether the UPI Link speed value is consistent with the speed limit value of the speed limit value recorded by the BIOS, and if so, passing the test.
In order to facilitate understanding of the present invention, the principle of the UPI Link slowdown test method of the present invention is combined with the UPI Link slowdown test process in the embodiment to further describe the UPI Link slowdown test method provided by the present invention.
Specifically, the UPI Link speed reduction test method comprises the following steps:
firstly, option System Errors = Enable needs to be set in BIOS Setup, so that logs can be recorded under the web, CRC Mode = <16Bit CRC >, UPI Fail-over Support = Enable, link L0p Enable = Disabled supports Link L0p energy saving state.
In a Linux or Windows operating system, looking at the UPI link status, all UPI channels between CPUs are connected: when the UPI Tx Lane Status value shows 0, the Status of all channels is connected, otherwise, if a certain value shows 1, the Status of the channel is disconnected.
And injecting a UPI DataLane Failover error into one UPI port, and when an error is injected into the UPI port, recording the error by the BIOS, wherein the command is as follows: injectupidatailfailover (0, 2,1, 0x3), this server contains two CPUs, where 0 represents CPU0,2 represents UPI port2,1 represents Tx Lane #0and Lane #1 channel, and 0X3 represents disabling the specified channel.
When the UPI DataLane failure over error is finished, it is necessary to check whether this error has been successfully injected, and execute a command to check whether the specified Tx Lane #0and Lane #1 channel status is displayed as 1.
The closing of the channel causes the web to report an uncorrectable ECC error log and a UPI speed reduction related log, and the system is restarted, so that a red error report problem can occur on a VGA interface.
The PCIE bus is grabbed through an lspci command under the system, and because each CPU comprises 3 UPI ports, 6 buses can be actually displayed, the buses of an actual fault channel need to be accurately checked, and a UPI Link speed value is obtained according to the path. This speed value is compared to the value in BIOS Setup.
As shown in fig. 2, the system 200 includes:
an error injection unit 210 configured to inject a UPI DataLane failure over error to a specified UPI port, and simultaneously, a BIOS records a speed limit value of the port with the error;
an error checking unit 220 configured to check whether a web-reported error log and a UPI speed-down related log appear, and if so, restart the system;
the speed capturing unit 230 is configured to capture a PCIE bus corresponding to the error-injection UPI port through an lspci command, and acquire a UPI Link speed value of the corresponding PCIE bus;
and the speed comparison unit 240 is configured to compare whether the UPI Link speed value is consistent with the speed limit value of the speed limit value recorded by the BIOS, and if so, the test is passed.
Optionally, as an embodiment of the present invention, the system further includes:
the option setting unit is configured to set option System Errors = Enable in the BIOS Setup, and ensure that the log can be recorded under the web;
and the state setting unit is configured to set a Link L0p supporting power saving state.
Optionally, as an embodiment of the present invention, the system further includes:
through the checking unit, the UPI link status is checked, and all channels of the UPI between the CPUs are connected.
Optionally, as an embodiment of the present invention, the system further includes:
and the error injection checking unit is configured for checking whether the error injection channel state is displayed as disconnected or not, and if not, sending a test error prompt.
Fig. 3 is a schematic structural diagram of a controlled terminal 300 according to an embodiment of the present invention, where the controlled terminal 300 may be used to execute a UPI Link speed reduction test method according to the embodiment of the present invention.
Wherein, the controlled terminal 300 may include: a processor 310, a memory 320, and a communication unit 330. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 320 may be used for storing instructions executed by the processor 310, and the memory 320 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 320, when executed by processor 310, enable terminal 300 to perform some or all of the steps in the method embodiments described below.
The processor 310 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 320 and calling data stored in the memory. The processor may be formed by an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs with the same or different functions. For example, the processor 310 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 330, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Therefore, the invention forms a communication Link by linking the CPU through the UPI port, the rate index value of the Link Frequency Select is 9.6GT/S or 10.4GT/S, when the rate is lower than the index value, the performance of the server is seriously influenced, but the invention causes the failure of the UPI # lane by error injection, prevents the UPI Link from running and transmitting data in full width, and can cause error report on a VGA interface and crash at the time, and simultaneously can display the 'uncorrectable ECC log' related to the UPI and the log related to the UPI Link speed reduction under the web. In the invention, the UPI DataLane failure error is injected into the UPI Port, so that the channel fails, thereby achieving the purpose of reducing the speed of the UPI Link, and thus verifying whether the working mechanism of the UPI Link is normal at the time.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention.
The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.
In the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A UPI Link simulation deceleration test method is characterized by comprising the following steps:
injecting UPIDataLane Failover error into the appointed UPI port, and simultaneously recording the speed limit value of the error port by the BIOS;
checking whether a web reported error log and a UPI speed reduction related log appear, and restarting the system if the web reported error log and the UPI speed reduction related log appear;
capturing PCIE bus corresponding to the UPI port with wrong injection through an lspci command, and acquiring a UPI Link speed value corresponding to the PCIE bus;
and comparing whether the UPI Link speed value is consistent with the speed limit value recorded by the BIOS, and if so, passing the test.
2. The method of claim 1, further comprising:
setting an option System Errors = Enable in the BIOS Setup to ensure that the log can be recorded under the web;
the Link L0p supported power save state is set.
3. The method of claim 1, further comprising:
looking at the UPI link status ensures that all channels of UPI between CPUs are connected.
4. The method of claim 1, further comprising:
and checking whether the state of the fault injection channel is displayed as disconnected or not, and if not, sending a test fault prompt.
5. A UPI Link deceleration test system is characterized by comprising:
the error injection unit is configured to inject UPIDataLane failure over error into a specified UPIport, and the BIOS records the speed limit value of the error port;
the error checking unit is configured for checking whether a web reported error log and a UPI speed reduction related log appear or not, and if so, restarting the system;
the speed capturing unit is configured to capture the PCIE bus corresponding to the UPI port with wrong injection through an lspci command, and acquire a UPI Link speed value corresponding to the PCIE bus;
and the speed comparison unit is configured for comparing whether the UPI Link speed value is consistent with the speed limit value recorded by the BIOS, and if so, the test is passed.
6. The system of claim 5, further comprising:
the option setting unit is configured to set option System Errors = Enable in the BIOS Setup, and ensure that the log can be recorded under the web;
and the state setting unit is configured to set a Link L0p supporting power saving state.
7. The system of claim 5, further comprising:
through the checking unit, the UPI link status is checked, and all channels of the UPI between the CPUs are connected.
8. The system of claim 5, further comprising:
and the error injection checking unit is configured for checking whether the error injection channel state is displayed as disconnected or not, and if not, sending a test error prompt.
9. A terminal, comprising:
a processor;
a memory for storing instructions for execution by the processor;
wherein the processor is configured to perform the method of any one of claims 1-4.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-4.
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| CN114116330B (en) * | 2021-10-22 | 2024-05-24 | 苏州浪潮智能科技有限公司 | Server performance testing method, system, terminal and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107153553A (en) * | 2017-06-09 | 2017-09-12 | 郑州云海信息技术有限公司 | The method that Purley platform CPU end PCIe Tx Eq adjustment is carried out based on CScripts |
| CN108595297A (en) * | 2018-05-09 | 2018-09-28 | 郑州云海信息技术有限公司 | A kind of detection method and device of UPI speed |
| CN109918254A (en) * | 2019-02-27 | 2019-06-21 | 苏州浪潮智能科技有限公司 | A kind of AEP memory Error Detection function test method, system, terminal and storage medium |
| CN109992458A (en) * | 2019-03-29 | 2019-07-09 | 苏州浪潮智能科技有限公司 | A kind of UPI bandwidth detection method, apparatus, equipment and readable storage medium storing program for executing |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107153553A (en) * | 2017-06-09 | 2017-09-12 | 郑州云海信息技术有限公司 | The method that Purley platform CPU end PCIe Tx Eq adjustment is carried out based on CScripts |
| CN108595297A (en) * | 2018-05-09 | 2018-09-28 | 郑州云海信息技术有限公司 | A kind of detection method and device of UPI speed |
| CN109918254A (en) * | 2019-02-27 | 2019-06-21 | 苏州浪潮智能科技有限公司 | A kind of AEP memory Error Detection function test method, system, terminal and storage medium |
| CN109992458A (en) * | 2019-03-29 | 2019-07-09 | 苏州浪潮智能科技有限公司 | A kind of UPI bandwidth detection method, apparatus, equipment and readable storage medium storing program for executing |
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