CN111124028B - Multi-path combined power supply method and device and storage medium - Google Patents
Multi-path combined power supply method and device and storage medium Download PDFInfo
- Publication number
- CN111124028B CN111124028B CN201911121931.6A CN201911121931A CN111124028B CN 111124028 B CN111124028 B CN 111124028B CN 201911121931 A CN201911121931 A CN 201911121931A CN 111124028 B CN111124028 B CN 111124028B
- Authority
- CN
- China
- Prior art keywords
- power supply
- terminal
- voltage
- merging
- response
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 230000004044 response Effects 0.000 claims abstract description 41
- 238000004590 computer program Methods 0.000 claims description 15
- 238000002955 isolation Methods 0.000 abstract description 6
- 238000007599 discharging Methods 0.000 description 13
- 230000006870 function Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The invention discloses a multi-path combined power supply method, which comprises the following steps: judging whether the voltages of the multiple power supply ends are all at a set voltage threshold value; in response to the fact that the voltages of the multiple power supply ends are all at the set voltage threshold value, conducting each power supply end and the merging end respectively; periodically detecting the voltage of each power supply terminal and the voltage of the merging terminal; and responding to the voltage of the merging terminal being larger than the voltage of the power supply terminal, and disconnecting the power supply terminal with the voltage being smaller than the merging terminal from the merging terminal. The invention also discloses a computer device and a readable storage medium. When the method disclosed by the invention detects that the voltage of the merging end is greater than the voltage of the power supply end, the power supply end and the merging end are disconnected, so that the voltage isolation can be realized, and the mutual influence among multiple paths of power supply ends is avoided.
Description
Technical Field
The invention relates to the field of power supply, in particular to a multi-path combined power supply method, equipment and a storage medium.
Background
With the development of new internet technologies such as cloud computing, AI intelligence, big data and the like, a high requirement is put forward on the performance of a server, and the requirement on power supply power is also greater. In order to realize big data processing or more intelligent functions, processors with specific functions are usually added to some additional boards, the power requirement of a power supply is increased, the power of some circuits cannot meet the requirement of the boards at any time, and in order to meet the power requirement of the boards, multiple power supplies are combined into one path to supply power to the boards.
The combination of multiple power supplies in the existing board card can cause the voltage following fluctuation after combination due to the fact that one voltage fluctuates or suddenly increases, and damage is caused to a rear-end device. Due to the fluctuation or sudden increase of one path of voltage, the other path of voltage is fleed into the other path of voltage, and the device of the other path of voltage is damaged.
For example, as shown in fig. 1 and fig. 2, in the multi-way power supply combining method in the prior art, in the multi-way combined power supply scheme shown in fig. 1, a power supply a and a power supply B perform power supply combining through a diode, and in the scheme, isolation between two parties of combined voltage can be realized, for example: when the voltage of the power supply A fluctuates or suddenly increases, the fluctuation on the power supply A cannot be transmitted to the power supply B due to the unidirectional conductivity of the diode on the circuit of the power supply B; if the combined power supply fluctuates, the power supply can not be transmitted to the power supply A or the power supply B; however, due to the conduction voltage drop characteristic of the diode, the voltages of the power supply a and the power supply B become small (about 0.7V), which is unacceptable for devices with required voltages; in addition, due to the on-resistance of the diode, the resistance of the diode causes a large heat generation and a large power loss when the current continues to be conducted.
In the multiple combined power supply scheme shown in fig. 2, the power supply a and the power supply B pass through the opposite MOS transistors and then are combined, and since the on-resistance of the MOS transistors is smaller than that of the diodes, the heat generation and the power loss caused by the continuous current are also smaller than those of the diodes. When the power supply A or the power supply B is in a power failure state, the MOS tube in the power failure state is cut off, and the power supply can be isolated.
However, when both MOS transistors are turned on, the other is affected by power supply fluctuation and surge of the power supply a or the power supply B. That is, when both power supplies are turned on, voltage isolation cannot be achieved.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a method for multi-path combining power supply, including:
judging whether the voltages of the multiple power supply ends are all at a set voltage threshold value;
in response to the fact that the voltages of the multiple power supply ends are all at the set voltage threshold value, conducting each power supply end and the merging end respectively;
periodically detecting the voltage of each power supply terminal and the voltage of the merging terminal;
disconnecting the supply terminal having a voltage less than the merge terminal from the merge terminal in response to the voltage of the merge terminal being greater than the voltage of the supply terminal.
In some embodiments, further comprising the step of:
continuously and periodically detecting the voltages of the power supply end and the merging end;
and in response to the voltage of the merging terminal not being larger than the voltage of the power supply terminal, the power supply terminal and the merging terminal are conducted again.
In some embodiments, in response to that the voltages of the multiple power supply terminals are all at the set voltage threshold, each power supply terminal and the combining terminal are respectively conducted, further comprising:
and in response to the fact that the voltages of the multiple power supply ends are all at the set voltage threshold, controlling each power supply end to be conducted with the merging end after a preset time period.
In some embodiments, in response to the voltage at the combining terminal being greater than the voltage at the supply terminal, disconnecting the supply terminal having a voltage less than the combining terminal from the combining terminal, further comprises:
and in response to the voltage of the merging terminal being greater than the voltage of the power supply terminal, controlling the power supply terminal with the voltage less than the merging terminal to be disconnected from the merging terminal after a preset time period.
In some embodiments, further comprising:
in response to receiving a forced conduction instruction, conducting the power supply end and the merging end in a forced way;
and in response to receiving a forced disconnection instruction, forcibly disconnecting the power supply end and the merging end which are conducted again.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of:
judging whether the voltages of the multiple power supply ends are all at a set voltage threshold value;
in response to the fact that the voltages of the multiple power supply ends are all at the set voltage threshold value, conducting each power supply end and the merging end respectively;
periodically detecting the voltage of each power supply terminal and the voltage of the merging terminal;
disconnecting the supply terminal having a voltage less than the merge terminal from the merge terminal in response to the voltage of the merge terminal being greater than the voltage of the supply terminal.
In some embodiments, further comprising:
continuously and periodically detecting the voltages of the power supply end and the merging end;
and in response to the voltage of the merging terminal not being larger than the voltage of the power supply terminal, the power supply terminal and the merging terminal are conducted again.
In some embodiments, in response to that the voltages of the multiple power supply terminals are all at the set voltage threshold, each power supply terminal and the combining terminal are respectively conducted, further comprising:
and in response to the fact that the voltages of the multiple power supply ends are all at the set voltage threshold, controlling each power supply end to be conducted with the merging end after a preset time period.
In some embodiments, in response to the voltage at the combining terminal being greater than the voltage at the supply terminal, disconnecting the supply terminal having a voltage less than the combining terminal from the combining terminal, further comprises:
and in response to the voltage of the merging terminal being greater than the voltage of the power supply terminal, controlling the power supply terminal with the voltage less than the merging terminal to be disconnected from the merging terminal after a preset time period.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program, which when executed by a processor performs the steps of any of the multiple combining power supply methods described above.
The invention has one of the following beneficial technical effects: when the method disclosed by the invention detects that the voltage of the merging end is greater than the voltage of the power supply end, the power supply end and the merging end are disconnected, so that the voltage isolation can be realized, and the mutual influence among multiple paths of power supply ends is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of a multi-path combined power supply in the prior art;
FIG. 2 is a schematic diagram of another prior art multi-path combined power supply;
fig. 3 is a schematic flowchart of a multi-path combined power supply method according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a multi-path combined power supply according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
According to an aspect of the present invention, an embodiment of the present invention provides a multiple combining power supply method, as shown in fig. 3, which may include the steps of: s1, judging whether the voltages of the multiple power supply ends are all at the set voltage threshold value; s2, responding to the voltage of the multi-path power supply ends being at the set voltage threshold, respectively conducting each path of power supply end and the merging end; s3, periodically detecting the voltage of each circuit power supply terminal and the merging terminal; s4, in response to the voltage of the merging terminal being greater than the voltage of the power supply terminal, disconnecting the power supply terminal having a voltage less than the merging terminal from the merging terminal.
When the method disclosed by the invention detects that the voltage of the merging end is greater than the voltage of the power supply end, the power supply end and the merging end are disconnected, so that the voltage isolation can be realized, and the mutual influence among multiple paths of power supply ends is avoided.
In some embodiments, further comprising the step of:
continuously and periodically detecting the voltages of the power supply end and the merging end;
and in response to the voltage of the merging terminal not being larger than the voltage of the power supply terminal, the power supply terminal and the merging terminal are conducted again.
Specifically, when the voltage of the merging terminal is greater than the voltages of other normal power supply terminals due to the voltage increase or load fluctuation of one power supply terminal, the other normal power supply terminals are disconnected from the merging terminal, and after a period of time, the voltage of the merging terminal gradually decreases until the voltage of the merging terminal is not greater than the voltages of the other normal power supply terminals due to the voltage consumption or the voltage decrease of the power supply terminal with the increased voltage, and the other normal power supply terminals which have been disconnected are reconnected with the merging terminal.
In some embodiments, in response to that the voltages of the multiple power supply terminals are all at the set voltage threshold, each power supply terminal and the combining terminal are respectively conducted, further comprising:
and in response to the fact that the voltages of the multiple power supply ends are all at the set voltage threshold, controlling each power supply end to be conducted with the merging end after a preset time period.
Specifically, when the merging terminal is conducted with each of the power supply terminals, the conducting time of each of the power supply terminals and the merging terminal needs to be controlled due to the requirement of the power-on sequence, so that each of the power supply terminals and the merging terminal can be conducted simultaneously. For example, when the power supply terminal a is powered on first and the power supply terminal B is powered on later, the conduction speed of the power supply terminal a and the merging terminal needs to be controlled, that is, the conduction speed of the power supply terminal a and the merging terminal is controlled to be smaller than the conduction speed of the power supply terminal B and the merging terminal.
It should be noted that, due to error, the simultaneous conduction of the power supply terminal and the combining terminal of each circuit is not strictly simultaneous conduction, and a certain time difference is allowed.
In some embodiments, in response to the voltage at the combining terminal being greater than the voltage at the supply terminal, disconnecting the supply terminal having a voltage less than the combining terminal from the combining terminal, further comprises:
and in response to the voltage of the merging terminal being greater than the voltage of the power supply terminal, controlling the power supply terminal with the voltage less than the merging terminal to be disconnected with the merging terminal after a preset time period.
Specifically, when the voltage of the merging terminal is detected to be greater than the voltage of the power supply terminal, the power supply terminal can be controlled to be disconnected with the merging terminal within a preset time period, the disconnection time can be preset and set, and dynamic adjustment can be performed according to actual conditions.
In some embodiments, further comprising:
in response to receiving a forced conduction instruction, conducting the power supply end and the merging end in a forced way;
and in response to receiving a forced disconnection instruction, forcibly disconnecting the power supply end and the merging end which are conducted again.
Specifically, the merging terminal and the power supply terminal can be turned on or off by detecting the voltage of the merging terminal and the power supply terminal, and the connection or disconnection of the merging terminal and the power supply terminal can be controlled by an external instruction. Namely, after receiving an on command sent from the outside, the merging terminal is connected with the power supply terminal, and after receiving an off command sent from the outside, the merging terminal is disconnected with the power supply terminal.
It should be noted that, initially, the voltage thresholds of the power supply terminals need to be the same, so that the voltage of the merging terminal is the voltage threshold of the power supply terminal. For example, when the voltage threshold of the power supply terminal is 0.2V, the voltage threshold of the combining terminal is 0.2V.
The multi-path combined power supply method proposed by the present invention is described in detail below with reference to the structure diagram of multi-path combined power supply shown in fig. 4.
As shown in fig. 2, the power supply terminal a is connected to the drain of the MOS transistor and then connected to the merging terminal through the source of the MOS transistor, the charge pump charging module is connected to the power supply terminal a and the gate of the MOS transistor, one end of the charge discharging module is connected to the gate of the MOS transistor, and the other end of the charge discharging module is grounded; the control logic module is used for controlling the charging module and the discharging module, and the voltage comparison module is connected with the control logic module, the power supply end A and the merging end.
The input end of the voltage comparison module is connected to the power supply input end of a multi-path power supply, the output end of the comparison module is connected to the merging end of the multi-path power supply, the logic output signal of the voltage comparison module is connected to the logic controller module, the input end of the drive electrode charge pump charging module is connected to the power supply input end of the multi-path power supply, and the output end of the drive electrode charge pump charging module is connected to the drive GATE electrode of the MOS tube; the input end of the drive electrode charge discharge module is connected to a drive GATE electrode of the MOS tube, and the output end of the drive electrode charge discharge module is connected to the ground; the logic controller module receives a logic output signal of the input-output voltage comparison module and is then simultaneously connected with the driving electrode charge pump charging module and the driving electrode charge discharging module; at the moment, when the power supply is electrified, the driving electrode charge pump automatically charges and drives the MOS tube GATE electrode to be opened, and the power supply is directly output to the power merging end; the input and output voltage comparison module can compare the voltage levels of the power supply input end and the merging end in real time, when the voltage of the merging end is higher than a voltage threshold value set by the power supply input end, the input and output voltage comparison module can send the signal to the logic controller module, and the logic controller module sends an MOS tube turn-off enabling signal to the driving electrode charge discharge module to further close the MOS tube channel.
When the voltage of the merging end is lower than the voltage threshold value set by the power supply input end, the input-output voltage comparison module sends the signal to the logic controller module, and the logic controller module sends an MOS tube opening enabling signal to the driving electrode charge pump charging module so as to open the MOS tube channel.
In some embodiments, the voltage comparison module is connected to the input voltage terminal and the output voltage terminal, respectively, and the module can set a threshold of the input-output voltage difference, where the threshold is used to determine the timing of turning on or off the MOS transistor, that is, the ripple of the combined voltage can be adjusted. The charge pump charging module is used for increasing input voltage to obtain enough voltage to drive the MOS tube to be opened, and the charge pump can adjust the charging speed and is used for adjusting the opening speed of the MOS tube. The driving pole charge discharging module is used for discharging the charge of the driving pole to turn off the MOS tube to be conducted, and the charge discharging module can adjust the discharging speed and is used for adjusting the closing speed of the MOS tube. The logic controller module can be externally connected with external control logic to realize the forced opening or closing of the MOS tube. Meanwhile, the controller module can be interconnected with controllers of other power circuits, so that various logic controls of multi-power supply can be realized. For example, when the external control logic signal sends out a forced turn-off MOS transistor enable signal, the logic controller module sends out a signal to the charge discharging module, GATE electrode charges of the MOS transistors are connected to the ground through the charge discharging module, and channels of the MOS transistors are closed.
In some embodiments, the voltage comparison module may be a comparator, the control logic module may be an FPGA, the charge pump charging module may be a combination of a variable resistor and a capacitor or an MOS transistor, and the charge discharging module may be a combination of a variable resistor and a capacitor or an MOS transistor.
In some embodiments, when the voltage comparison module of the power supply a detects that the combined voltage due to the load fluctuation or the voltage rise of one of the power supplies B is higher than the voltage threshold set by the power supply a, the power supply a turns off the MOS tube channel; due to the fact that the power supply A is turned off, the combined voltage can be gradually reduced to the set voltage threshold value due to consumption of the voltage of the load end, the power supply A meets the condition that the MOS tube is conducted, and the power supply A can be turned on again. For example, when the voltage threshold of the supply terminal B is increased from the initial 0.2V to 0.3V, the supply terminal a and the merge terminal are disconnected, and after the voltage of the merge terminal is decreased to 0.2V, the supply terminal a and the merge terminal are connected.
Therefore, the voltage threshold of the on/off of the MOS tube can be adjusted through the input/output voltage comparison module, so that the voltage threshold or the voltage ripple of the combined voltage can be adjusted, the on speed of the MOS tube is adjusted through the driving electrode charge pump charging module, and the requirements of different circuits on power-on time sequences are met; the closing speed of the MOS tube is adjusted through the driving electrode charge discharging module, so that the requirements of different circuits on discharging time sequences are met; the logic controller module can be externally connected with external control logic to realize the forced opening or closing of the MOS tube; meanwhile, the controller module can be interconnected with controllers of other power circuits, so that various logic controls of multi-power supply can be realized. The method can effectively solve the defects of large conduction resistance, voltage drop, large electric energy loss, or incapability of realizing voltage isolation and the like in the traditional design method for multipath power supply of the DC power supply of the server and the computer.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 5, an embodiment of the present invention further provides a computer apparatus 501, comprising:
at least one processor 520; and
the memory 510, the memory 510 stores a computer program 511 that is executable on the processor, and the processor 520 executes the computer program to perform the steps of any of the above-described multiplexing-combined power supply methods.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 6, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610, when executed by a processor, perform the steps of any of the above multi-way merge power supply methods.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program to instruct related hardware to implement the methods. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
In addition, the apparatuses, devices, and the like disclosed in the embodiments of the present invention may be various electronic terminal devices, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television, and the like, or may be a large terminal device, such as a server, and the like, and therefore the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of apparatus, device. The client disclosed by the embodiment of the invention can be applied to any one of the electronic terminal devices in the form of electronic hardware, computer software or a combination of the electronic hardware and the computer software.
Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (8)
1. A multi-path combined power supply method comprises the following steps:
judging whether the voltages of the multiple power supply ends are all at a set voltage threshold value;
in response to the fact that the voltages of the multiple power supply ends are all at the set voltage threshold value, conducting each power supply end and the merging end respectively;
periodically detecting the voltage of each power supply terminal and the voltage of the merging terminal;
disconnecting the supply terminal having a voltage less than the combining terminal from the combining terminal in response to the voltage of the combining terminal being greater than the voltage of the supply terminal;
continuously and periodically detecting the voltages of the power supply end and the merging end;
and in response to the voltage of the merging terminal not being larger than the voltage of the power supply terminal, the power supply terminal and the merging terminal are conducted again.
2. The method of claim 1, wherein each of the plurality of power supply terminals is respectively conducted with the combining terminal in response to the voltages of the plurality of power supply terminals being at the set voltage threshold, further comprising:
and in response to the fact that the voltages of the multiple power supply ends are all at the set voltage threshold, controlling each power supply end to be conducted with the merging end after a preset time period.
3. The method of claim 1, wherein the supply terminal having a voltage less than the combining terminal is disconnected from the combining terminal in response to the voltage of the combining terminal being greater than the voltage of the supply terminal, further comprising:
and in response to the voltage of the merging terminal being greater than the voltage of the power supply terminal, controlling the power supply terminal with the voltage less than the merging terminal to be disconnected from the merging terminal after a preset time period.
4. The method of claim 1, further comprising:
in response to receiving a forced conduction instruction, conducting the power supply end and the merging end in a forced way;
and in response to receiving a forced disconnection instruction, forcibly disconnecting the power supply end and the merging end which are conducted again.
5. A computer device, comprising:
at least one processor; and
a memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of:
judging whether the voltages of the multiple power supply ends are all at a set voltage threshold value;
in response to the fact that the voltages of the multiple power supply ends are all at the set voltage threshold value, conducting each power supply end and the merging end respectively;
periodically detecting the voltage of each power supply terminal and the voltage of the merging terminal;
disconnecting the supply terminal having a voltage less than the merge terminal from the merge terminal in response to the voltage of the merge terminal being greater than the voltage of the supply terminal
Continuously and periodically detecting the voltages of the power supply end and the merging end;
and in response to the voltage of the merging terminal not being larger than the voltage of the power supply terminal, the power supply terminal and the merging terminal are conducted again.
6. The computer device of claim 5, wherein each of the plurality of power supply terminals is respectively conducted with the combining terminal in response to the voltages of the plurality of power supply terminals being at a set voltage threshold, further comprising:
and in response to the fact that the voltages of the multiple power supply ends are all at the set voltage threshold, controlling each power supply end to be conducted with the merging end after a preset time period.
7. The computer device of claim 5, wherein in response to the voltage of the combining terminal being greater than the voltage of the supply terminal, disconnecting the supply terminal having a voltage less than the combining terminal from the combining terminal, further comprising:
and in response to the voltage of the merging terminal being greater than the voltage of the power supply terminal, controlling the power supply terminal with the voltage less than the merging terminal to be disconnected from the merging terminal after a preset time period.
8. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method of any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911121931.6A CN111124028B (en) | 2019-11-15 | 2019-11-15 | Multi-path combined power supply method and device and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911121931.6A CN111124028B (en) | 2019-11-15 | 2019-11-15 | Multi-path combined power supply method and device and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111124028A CN111124028A (en) | 2020-05-08 |
| CN111124028B true CN111124028B (en) | 2022-02-18 |
Family
ID=70495972
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911121931.6A Active CN111124028B (en) | 2019-11-15 | 2019-11-15 | Multi-path combined power supply method and device and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111124028B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111431027B (en) * | 2020-03-30 | 2021-07-16 | 武汉光谷信息光电子创新中心有限公司 | Power-off control method, circuit, device and storage medium |
| CN111857222B (en) * | 2020-06-18 | 2022-04-19 | 苏州浪潮智能科技有限公司 | System for power supply voltage regulation |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101533074B (en) * | 2008-09-22 | 2011-07-20 | 珠海赛比特电气设备有限公司 | Electric energy feedback type electronic load with multi-channel wide voltage input |
| TWI506909B (en) * | 2013-11-22 | 2015-11-01 | Accton Technology Corp | Power sharing device and method thereof |
| CN109274085A (en) * | 2018-10-08 | 2019-01-25 | 武汉船用电力推进装置研究所（中国船舶重工集团公司第七二研究所） | A kind of online switching device of DC power supply and switching method |
| CN110429644B (en) * | 2019-07-31 | 2021-08-20 | 华为技术有限公司 | Inverter and power supply system |
-
2019
- 2019-11-15 CN CN201911121931.6A patent/CN111124028B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN111124028A (en) | 2020-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI742287B (en) | Switched capacitor power converter and electronic system | |
| US9479051B2 (en) | Single-inductor multiple-output DC to DC converter | |
| US8829979B2 (en) | Power-efficient multi-mode charge pump | |
| US7285941B2 (en) | DC-DC converter with load intensity control method | |
| CN111124028B (en) | Multi-path combined power supply method and device and storage medium | |
| US11539294B2 (en) | Multi-level power converter with light load flying capacitor voltage regulation | |
| EP2686945B1 (en) | Charge pump surge current reduction | |
| US20070176671A1 (en) | Charge pump circuit and electric appliance therewith | |
| US20150145497A1 (en) | Low-loss step-up and step-down voltage converter | |
| WO2014003967A1 (en) | Bridge driver for a switching voltage regulator | |
| US20110148377A1 (en) | Power supply converter and method | |
| US11552565B2 (en) | Switch-mode power supply with load current based throttling | |
| US20180375438A1 (en) | Apparatus, system, and method for reducing voltage overshoot in voltage regulators | |
| WO2023134381A1 (en) | Switch power source circuit and terminal device | |
| US10594313B2 (en) | Adaptive modulation scheme of MOSFET driver key parameters for improved voltage regulator efficiency and system reliability | |
| CN103973087A (en) | Power-down holding circuit | |
| CN204669334U (en) | The isolated drive circuit of MOSFET element | |
| WO2016177197A1 (en) | Single-power-supply circuit and power supply system | |
| CN114094660B (en) | Linear charging system with high-voltage turn-off function | |
| WO2022144004A1 (en) | Solar charging circuit, charging method, electronic device and storage medium | |
| TW201907636A (en) | A power apparatus operating method, a power apparatus, and a management system of power apparatus(es) | |
| US20170077813A1 (en) | Switched mode power supply circuit | |
| KR20120116946A (en) | Switching mode power supply comprising asynchronous limiter circuit | |
| US10680603B2 (en) | Isolation and voltage regulation circuit | |
| US9935550B2 (en) | System and method for preventing cross-conduction when switching circuitry during voltage regulation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |