CN111123792B - Multi-main-system interactive communication and management method and device - Google Patents
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Abstract
The invention provides a method and a device for interactive communication and management of multiple main systems, wherein the method comprises the following steps: responding to a command sent to a main system by a user, writing a control right indication mark into a corresponding control right register on a programmable logic device by the main system, and synchronizing the control right indication mark to other main systems; the programmable logic device periodically polls all the control right registers, responds to the control right indication marks in the control right registers, and transmits the control instruction of the main system with the highest priority to peripheral equipment according to the preset priority for control; and synchronizing the control instruction of the main system with the highest priority to other main systems. The invention realizes the interactive communication and management of the multi-master system, ensures that the data communication is barrier-free and avoids the conflict.
Description
Technical Field
The present invention relates to the field of computers, and more particularly, to a method and an apparatus for multi-master system interactive communication and management.
Background
In the system such as the switch, the CPLD-FPGA chip is used for controlling the power-on and power-off sequence control, the communication control, the key detection, the fan rotating speed control, the SFP lighting control and serial port switching, the I2C multi-master control, the high-speed data interaction and the like of the whole switch. The CPLD-FPGA controls the working state of some key devices, so that the CPLD-FPGA is closely related to the working state of the whole hardware of the switch system. Meanwhile, the CPLD-FPGA is a semi-customized special integrated circuit, has the series advantages of flexible programming, quick response, high integration level and the like, and is more and more widely applied to the field of development, verification and control application in the prior art.
The upstream controller such as BMC or CPU realizes interactive communication with the CPLD-FPGA through the register based on I2C protocol, and comprises the steps that the upstream controller acquires information from the CPLD-FPGA and writes control instructions into the CPLD-FPGA register to control CPLD-FPGA peripheral equipment. And the single main system is simple, and only control data needs to be written into the CPLD-FPGA. However, for a multi-master system, a plurality of sets of independent registers are usually designed for independent control, so that the problems of control authority conversion and information synchronization are also involved for the multi-master system.
Disclosure of Invention
In view of this, an objective of the embodiments of the present invention is to provide a method and an apparatus for interactive communication and management of multiple master systems, so as to solve the problems of control authority transformation and information synchronization in the multiple master systems.
Based on the above object, an aspect of the embodiments of the present invention provides a method for interactive communication and management of multiple main systems, including the following steps:
responding to a command sent to a main system by a user, writing a control right indication mark into a corresponding control right register on a programmable logic device by the main system, and synchronizing the control right indication mark to other main systems;
the programmable logic device periodically polls all the control right registers, responds to the control right indication marks in the control right registers, and transmits the control instruction of the main system with the highest priority to peripheral equipment according to the preset priority for control;
and synchronizing the control instruction of the main system with the highest priority to other main systems.
In some embodiments, in response to a user sending an instruction to a host system, the host system writing a control right indicator to its corresponding control right register on the programmable logic device, and synchronizing the control right indicator to other host systems includes:
and responding to a command sent to a main system by a user, and writing a control command into a corresponding data register on the programmable logic device by the main system.
In some embodiments, synchronizing the control instruction of the master system with the highest priority to the other master systems includes:
and synchronizing the control instruction written in the data register corresponding to the main system with the highest priority to the data registers corresponding to other main systems.
In some embodiments, the programmable logic device periodically polling all of the control right registers, and in response to a control right indication flag existing in a plurality of control right registers, transmitting a control instruction of the host system with the highest priority to the peripheral device according to a preset priority to perform control includes:
and responding to the corresponding control right indication mark in only one control right register, and transmitting the control instruction of the main system corresponding to the control right register to the peripheral equipment for control.
In some embodiments, synchronizing the control instruction of the master system with the highest priority to other master systems includes:
and synchronizing the control instruction of the main system corresponding to the control right register with the control right indication mark to other main systems.
In some embodiments, the host system includes a BMC, a CPU, a PCH.
In some embodiments, the programmable logic device comprises a CPLD, FPGA.
Another aspect of the embodiments of the present invention provides a multi-host system interactive communication and management apparatus, including a plurality of host systems and a programmable logic device communicatively connected to the plurality of host systems, wherein,
the plurality of main systems are configured to respond to a sending instruction of a user, write a control right indication mark into a corresponding control right register on the programmable logic device, and synchronize the control right indication mark to other main systems;
the programmable logic device is configured to poll all the control right registers periodically, respond to the control right indication marks in the plurality of control right registers, transmit the control instruction of the main system with the highest priority to the peripheral equipment according to a preset priority for control, and synchronize the control instruction of the main system with the highest priority to other main systems.
In some embodiments, the host system includes a BMC, a CPU, a PCH.
In some embodiments, the programmable logic device comprises a CPLD, FPGA.
The invention has the following beneficial technical effects: the multi-host system interactive communication and management method and device provided by the embodiment of the invention realize the interactive communication and management of the multi-host system through the CPLD and the FPGA register, ensure that the data communication is free from obstacles and avoid conflicts; meanwhile, a synchronous communication mechanism between the registers ensures that the controller can obtain accurate information of peripheral equipment in real time, the problem that the peripheral equipment cannot be monitored in a full time is solved, and the flexible reliability of the switch design is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a flow chart of a multi-master system interactive communication and management method according to the present invention;
fig. 2 is a schematic diagram of a multi-master system interactive communication and management device according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described below. However, it is to be understood that the disclosed embodiments are merely examples and that other embodiments may take various and alternative forms. The figures are not necessarily to scale; certain features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. As one of ordinary skill in the art will appreciate, various features illustrated and described with reference to any one of the figures may be combined with features illustrated in one or more other figures to produce embodiments that are not explicitly illustrated or described. The combination of features shown provides a representative embodiment for a typical application. However, various combinations and modifications of the features consistent with the teachings of the present invention may be desired for certain specific applications or implementations.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
Based on the above object, an embodiment of the present invention provides an interactive communication and management method for multiple main systems, as shown in fig. 1, including the following steps:
step S101: responding to a command sent to a main system by a user, writing a control right indication mark into a corresponding control right register on a programmable logic device by the main system, and synchronizing the control right indication mark to other main systems;
step S102: the programmable logic device periodically polls all the control right registers, responds to the control right indication marks in the control right registers, and transmits the control instruction of the main system with the highest priority to peripheral equipment according to the preset priority for control;
step S103: and synchronizing the control instruction of the main system with the highest priority to other main systems.
In some embodiments, in response to a user sending an instruction to a host system, the host system writing a control right indication flag to its corresponding control right register on the programmable logic device, and synchronizing the control right indication flag to other host systems includes: and responding to a command sent to a main system by a user, and writing a control command into a corresponding data register on the programmable logic device by the main system. For example, independent register areas corresponding to different main systems are divided on the programmable logic device, and the register area corresponding to each main system comprises a control right register and a data register so as to store a control right indication mark and a control instruction of the main system respectively.
In some embodiments, synchronizing the control instruction of the master system with the highest priority to the other master systems includes: and synchronizing the control instruction written in the data register corresponding to the main system with the highest priority to the data registers corresponding to other main systems. That is, when the peripheral device is under the control of one host system, other host systems can acquire the control data of the host system in real time, in addition to the control right under the control of the host system.
In some embodiments, the periodically polling all the control right registers by the programmable logic device, and in response to the control right indication flag existing in a plurality of control right registers, transmitting the control instruction of the main system with the highest priority to the peripheral device according to the preset priority to perform control includes: and responding to the corresponding control right indication mark in only one control right register, and transmitting the control instruction of the main system corresponding to the control right register to the peripheral equipment for control.
In some embodiments, synchronizing the control instruction of the host system with the highest priority to other host systems includes: and synchronizing the control instruction of the main system corresponding to the control right register with the control right indication mark to other main systems.
In some embodiments, a register accessible by other host systems may be included in the independent register area corresponding to each host system on the programmable logic device, and the content in the register may synchronize the content in the control right register of the host system in real time, that is, the content in the control right register in each independent register area and the content in the register accessible by other host systems always remain the same. In this way, other host systems can know which host system has written the control right indication flag, that is, which host system has received a user instruction to attempt to control the peripheral device through the host system. When only one main system writes the control right indication mark into the corresponding control right register, the main system can directly control the peripheral equipment, and other main systems synchronize control instruction information from the main system.
In some embodiments, the host system includes a BMC, CPU, PCH, or any other processing system suitable for use with the present invention.
In some embodiments, the programmable logic device comprises any programmable logic device such as a CPLD, FPGA, or the like, which can implement the present invention.
In one embodiment according to the invention, as shown in FIG. 2, in a dual master control system for a switch, e.g., a heat sink dual master controlIn the system, the lamp panel double-master control system and the write-protection double-master control system, the BMC and the CPU have I which can independently access and manage and control without interference in the CPLD/FPGA2C drives and registers. When the BMC and the CPU control the behavior of the peripheral device through the CPLD or the FPGA, an arbitration mechanism and a synchronous communication mechanism are designed besides ensuring that the BMC and the CPU can independently control the independent registers, wherein the arbitration mechanism means that after the CPLD/FPGA is logically analyzed, a control instruction of the BMC or the CPU can be selected to control the peripheral device, so that control indication marks need to be set to respectively indicate the control rights of the BMC and the CPU, and meanwhile, the mark indicating the control rights must be visible to both sides. The independent data registers of the BMC or the CPU are synchronous, that is, when the peripheral device is under the control of the BMC, the CPU can know the control right under the control of the BMC and can also know the control data of the BMC in real time. Vice versa, when the peripheral device is under the control of the CPU, the BMC can know the control data of the CPU in real time in addition to the control right under the control of the CPU.
When the peripheral device is under the control of BMC, the following design is needed to be made in the register corresponding to the CPU: on one hand, a BMC control right indication mark is fed back through a CPU control right readable register; on the other hand, when the BMC control right indication mark is valid, the content written into the data register by the BMC is allowed to be synchronized to the CPU register; besides, the CPU register content inside the CPLD/FPGA only allows CPU operation. Vice versa, when the peripheral device is under the control of the CPU, the BMC register needs to be designed as follows: on one hand, a CPU control right indication mark is fed back through a BMC control right readable register; on the other hand, when the CPU control right indication mark is valid, the content written into the data register by the CPU is allowed to be synchronized to the BMC register; besides, the BMC register content inside the CPLD/FPGA only allows the BMC to operate.
When the BMC and the CPU control right indication mark exist at the same time, the CPLD/FPGA defaults that the CPU or the BMC obtains the control right unilaterally, namely, the arbitration mechanism obtains the control right with high priority according to the preset priority, and the arbitration mechanism transmits the control instruction of the party obtaining the control right to the peripheral equipment. Meanwhile, when one party obtains the control right, the arbitration mechanism synchronizes the control instruction and other related information of the party obtaining the control right to the register which can be accessed by the other party. That is, when the dual-master-control peripheral device is under the control of the BMC, the control data written by the BMC can also be synchronized to the register that the CPU can access, so that the CPU can perform real-time monitoring according to the control information and the real-time feedback information of the BMC; similarly, when the peripheral device of the dual master control is under the control of the CPU, the control data written by the CPU can also be synchronized to the register that the BMC can access, so that the BMC can perform real-time monitoring according to the control information and the real-time feedback information of the CPU. Therefore, the BMC and the CPU can know the current control of a peripheral device in real time, so that monitoring and upper-layer control strategy design are facilitated.
Where technically feasible, the technical features listed above for the different embodiments may be combined with each other or changed, added, omitted, etc. to form further embodiments within the scope of the invention.
It can be seen from the foregoing embodiments that the multi-host system interactive communication and management method provided by the embodiments of the present invention implements interactive communication and management of the multi-host system through the CPLD and the FPGA register, thereby ensuring that data communication is free of obstacles and avoiding conflicts; meanwhile, a synchronous communication mechanism between the registers ensures that the controller can obtain accurate information of peripheral equipment in real time, the problem that the peripheral equipment cannot be monitored in a full time is solved, and the flexible reliability of the switch design is ensured.
In view of the above objects, in another aspect of the embodiments of the present invention, a multi-host system interactive communication and management apparatus is provided, which includes a plurality of host systems and a programmable logic device communicatively connected to the plurality of host systems, wherein,
the plurality of main systems are configured to respond to a sending instruction of a user, write a control right indication mark into a corresponding control right register on the programmable logic device, and synchronize the control right indication mark to other main systems;
the programmable logic device is configured to poll all the control right registers periodically, respond to the control right indication marks in the plurality of control right registers, transmit the control instruction of the main system with the highest priority to the peripheral equipment according to a preset priority for control, and synchronize the control instruction of the main system with the highest priority to other main systems.
In some embodiments, the host system includes a BMC, a CPU, a PCH.
In some embodiments, the programmable logic device comprises a CPLD, FPGA.
Any embodiment of the computer device executing the multi-host system interactive communication and management method can achieve the same or similar effects as any corresponding method embodiment.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes in the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like.
In addition, the apparatuses, devices and the like disclosed in the embodiments of the present invention may be various electronic terminal devices, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television and the like, or may be a large terminal device, such as a server and the like, and therefore the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of apparatus, device. The client disclosed in the embodiment of the present invention may be applied to any one of the above electronic terminal devices in the form of electronic hardware, computer software, or a combination of both.
Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions described herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disk, or the like.
The above-described embodiments are possible examples of implementations and are presented merely for a clear understanding of the principles of the invention. Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (9)
1. A multi-main system interactive communication and management method is characterized by comprising the following steps:
responding to a command sent to a main system by a user, writing a control right indication mark into a corresponding control right register on a programmable logic device by the main system, and synchronizing the control right indication mark to other main systems;
the programmable logic device periodically polls all the control right registers and responds to the control right indication marks in a plurality of control right registers, and transmits the control instruction of the main system with the highest priority to the peripheral equipment according to the preset priority for control, and the method comprises the following steps: responding to the corresponding control right indication mark in only one control right register, and transmitting the control instruction of the main system corresponding to the control right register to peripheral equipment for control;
and synchronizing the control instruction of the main system with the highest priority to other main systems.
2. The method of claim 1, wherein in response to a user sending an instruction to a host system, the host system writing a control right indicator to its corresponding control right register on the programmable logic device and synchronizing the control right indicator to other host systems comprises:
and responding to a command sent to a main system by a user, and writing a control command into a corresponding data register on the programmable logic device by the main system.
3. The method of claim 2, wherein synchronizing the control instructions of the highest priority host system to other host systems comprises:
and synchronizing the control instruction written in the data register corresponding to the main system with the highest priority to the data registers corresponding to other main systems.
4. The method of claim 1, wherein synchronizing the control instruction of the highest-priority host system to other host systems comprises:
and synchronizing the control instruction of the main system corresponding to the control right register with the control right indication mark to other main systems.
5. The method of claim 1, wherein the host system comprises a BMC, a CPU, a PCH.
6. The method of claim 1, wherein the programmable logic device comprises a CPLD, an FPGA.
7. A multi-host system interactive communication and management device is characterized by comprising a plurality of host systems and programmable logic devices in communication connection with the host systems, wherein,
the plurality of main systems are configured to respond to a sending instruction of a user, write a control right indication mark into a corresponding control right register on the programmable logic device, and synchronize the control right indication mark to other main systems;
the programmable logic device is configured to periodically poll all the control right registers, and in response to the control right indication flag existing in the plurality of control right registers, transmit a control instruction of the main system with the highest priority to the peripheral device according to a preset priority for control, and includes: responding to the corresponding control right indication mark in only one control right register, and transmitting the control instruction of the main system corresponding to the control right register to peripheral equipment for control;
and synchronizing the control instruction of the main system with the highest priority to other main systems.
8. The apparatus of claim 7, wherein the host system comprises a BMC, a CPU, a PCH.
9. The apparatus of claim 7, wherein the programmable logic device comprises a CPLD, an FPGA.
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