CN111105990A - Thin film structure suitable for copper metallized semiconductor device and preparation method thereof - Google Patents

Thin film structure suitable for copper metallized semiconductor device and preparation method thereof Download PDF

Info

Publication number
CN111105990A
CN111105990A CN201811271305.0A CN201811271305A CN111105990A CN 111105990 A CN111105990 A CN 111105990A CN 201811271305 A CN201811271305 A CN 201811271305A CN 111105990 A CN111105990 A CN 111105990A
Authority
CN
China
Prior art keywords
layer
titanium
film structure
copper
barrier layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201811271305.0A
Other languages
Chinese (zh)
Other versions
CN111105990B (en
Inventor
刘国友
罗海辉
张鸿鑫
谭灿健
唐智慧
冯宇
丁杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhuzhou CRRC Times Semiconductor Co Ltd
Original Assignee
Zhuzhou CRRC Times Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhuzhou CRRC Times Electric Co Ltd filed Critical Zhuzhou CRRC Times Electric Co Ltd
Priority to CN201811271305.0A priority Critical patent/CN111105990B/en
Publication of CN111105990A publication Critical patent/CN111105990A/en
Application granted granted Critical
Publication of CN111105990B publication Critical patent/CN111105990B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a film structure suitable for a copper metallized semiconductor device, which comprises a copper metal layer, a barrier layer and an adhesion layer, wherein the copper metal layer, the barrier layer and the adhesion layer are sequentially arranged between an upper metal layer and a substrate, the barrier layer is used for preventing copper from diffusing to the substrate, and the adhesion layer is used for adhering the barrier layer to the substrate. The invention also discloses a preparation method of the film structure suitable for the copper metallized semiconductor device. The film structure of the invention can improve the adhesiveness between the copper and the barrier layer and between the barrier layer and the substrate, and prevent the metal layer on the surface of the device from falling off.

Description

Thin film structure suitable for copper metallized semiconductor device and preparation method thereof
Technical Field
The invention relates to the field of semiconductors, in particular to a thin film structure suitable for a copper metallized semiconductor device and a preparation method thereof.
Background
Currently, copper-metallized semiconductor devices are widely used due to their excellent performance, but there are some problems that copper diffuses rapidly in semiconductor devices such as silicon and silicon oxide, and once copper ions enter the silicon devices, the copper ions become deep level acceptor impurities, so that the device performance is degraded or even fails, and therefore, a barrier layer is generally required to be added between copper and silicon. In order to solve the above problems, in the prior art, a single-layer or multi-layer thin film structure of titanium, titanium nitride, tantalum nitride, etc. is applied to a damascene process of an integrated circuit, and is mainly used for blocking copper ion diffusion and improving contact resistance. There are also a few patents that mention the use of metals such as gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, etc. as conductive layers in semiconductor device packages, mainly for improving contact resistance and corrosion resistance. In addition, there are some patents describing methods of filling holes with metals such as copper, tungsten, hot aluminum, and the like.
However, in the above process of using the metal layer structure as a barrier layer to block copper ion diffusion and improve resistance, there are still many problems, such as large leakage current of the device, poor adhesion of the metal layer, etc., which seriously affect the reliability and service life of the device, and even make the device completely fail.
Therefore, there is a need to design a new film structure suitable for copper-metallized semiconductor devices, which can block the diffusion of copper ions in the semiconductor device and improve the adhesion between copper and the barrier layer and silicon.
Disclosure of Invention
In order to solve the technical problems, the invention discloses a film structure suitable for a copper metallized semiconductor device and a preparation method thereof.
A first aspect of the present invention provides a thin film structure suitable for copper-metallized semiconductor devices, comprising a copper metal layer, a barrier layer and an adhesion layer sequentially disposed between an upper metal layer and a substrate, the barrier layer being for preventing diffusion of copper to the substrate, the adhesion layer being for adhering the barrier layer to the substrate. The adhesion layer is arranged between the barrier layer and the substrate, so that the viscosity between the barrier layer and the substrate is improved, the reliability of the device is improved, and the service life of the device is prolonged.
In one embodiment, the adhesion layer is a single layer of aluminum, tungsten, titanium, aluminum-silicon alloy, titanium-tungsten alloy, or titanium silicide, or a composite layer of any two or more of aluminum, tungsten, titanium, aluminum-silicon alloy, and titanium-tungsten alloy. For the design of the adhesion layer, the adhesion between the barrier layer and the substrate material is increased, ohmic contact can be formed between the barrier layer and the lower layer material, the contact resistance is reduced, and in addition, a certain barrier effect is realized on the diffusion of copper in the copper metal layer to the substrate material.
In one embodiment, the adhesion layer is a single aluminum layer, a single tungsten layer, a single titanium layer, a single aluminum-silicon alloy layer or a single titanium-tungsten alloy layer, and the thickness of the aluminum layer, the single tungsten layer, the single titanium layer, the single aluminum-silicon alloy layer or the single titanium-tungsten alloy layer is 0.001-5 μm.
In one embodiment, the adhesion layer is a titanium silicide layer, and the thickness of the titanium silicide layer is 0.001-2 μm.
In one embodiment, the barrier layer is a single layer of Ti, TiN, Ta, TaN, Co, or Ni, or a composite layer of two or more of Ti, TiN, Ta, TaN, Co, and Ni.
In one embodiment, the thickness of the barrier layer is 0.001 to 5 μm.
In one embodiment, the thickness of the copper metal layer is 0.1-100 μm.
In one embodiment, the upper metal layer is a single-layer metal structure of nickel, palladium, gold, silver, tin or lead, or a composite-layer metal structure of two or more layers of nickel, palladium, gold, silver, tin and lead.
In another aspect of the present invention, a method for preparing a thin film structure suitable for a copper-metallized semiconductor device is provided, which includes the following steps:
firstly, growing an adhesion layer and a barrier layer on a substrate in sequence by means of physical vapor deposition, chemical vapor deposition, atomic layer deposition or chemical plating;
forming a pattern on the barrier layer through a photoetching process;
step three, sequentially forming a copper metal layer and an upper metal layer on the barrier layer in the formed pattern in a physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating or chemical plating mode;
removing the photoresist in a dry photoresist removing or wet photoresist removing mode;
and fifthly, removing the redundant parts of the barrier layer and the adhesion layer in a dry etching or wet etching mode.
The film structure in the invention can not only improve the adhesion between the barrier layer and the substrate material, but also effectively prevent the diffusion of copper in the substrate material, optimize the performance of the device, improve the reliability of the device and ensure that the device can normally operate in severe environments such as high temperature, high pressure, high vibration and the like. Meanwhile, the film structure is suitable for all semiconductor devices containing copper metal and has wide application range.
Drawings
The invention will be described in more detail hereinafter on the basis of embodiments and with reference to the accompanying drawings. Wherein:
FIG. 1 is a schematic structural diagram of a thin film structure suitable for copper metallization of a semiconductor device in an embodiment of the present invention;
fig. 2 is a process flow diagram of a method for fabricating a thin film structure suitable for copper metallization of a semiconductor device in accordance with an embodiment of the present invention.
In the drawings, like parts are provided with like reference numerals. The drawings are not to scale.
Detailed Description
The invention will be further explained with reference to the drawings.
In the present invention, μm is a unit of length of μm.
Fig. 1 shows an embodiment of the present invention, which shows a thin film structure for copper-metallized semiconductor devices, the thin film structure is arranged between an upper metal layer 1 and a substrate 5, and sequentially comprises a copper metal layer 2, a barrier layer 3 and an adhesion layer 4, wherein the barrier layer 3 is used for preventing copper of the copper metal layer 2 from diffusing to the substrate 5, and the adhesion layer 4 is used for adhering the barrier layer 3 to the substrate 5. Preferably, the adhesion layer 4 may be a single aluminum layer, a single tungsten layer, a single titanium layer, an aluminum-silicon alloy layer, a titanium-tungsten alloy layer, or a single titanium silicide layer, or may be a composite layer of two or more of any of the aluminum layer, the tungsten layer, the titanium layer, the aluminum-silicon alloy layer, and the titanium-tungsten alloy layer. The adhesion layer 4 mainly functions to increase the adhesion between the barrier layer and the substrate material, and simultaneously can form ohmic contact between the barrier layer and the substrate material, reduce contact resistance, and also has a certain barrier effect on the diffusion of copper of the copper metal layer to the substrate material.
In some embodiments, when the adhesion layer 4 is an aluminum layer, a tungsten layer, a titanium layer, an aluminum-silicon alloy layer or a titanium-tungsten alloy layer, the thickness of the adhesion layer 4 in this case is preferably in the range of 0.001 to 5 μm, and in a preferred embodiment, the thickness of the adhesion layer 4 is 3 μm; in other embodiments, the adhesion layer 4 is a titanium silicide layer, which preferably has a thickness in the range of 0.001-2 μm, and in a preferred embodiment, the thickness of the titanium silicide layer is 0.05 μm.
Further, in the present embodiment, the barrier layer 3 may be a single layer of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Co (cobalt), or Ni (nickel), and in some embodiments, may also be a composite layer of two or more layers of Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Co (cobalt), or Ni (nickel). The barrier layer functions to block the diffusion of copper into the substrate material. In some embodiments, the barrier layer preferably has a thickness in the range of 0.001 to 5 μm; further, in a preferred embodiment wherein the barrier layer has a thickness of 0.05 μm.
Furthermore, in some embodiments, the thickness of the copper metal layer 2 is 0.1-100 μm; copper metal layers of such thickness become the main conductive layer of the semiconductor device and are also buffer layers for package bonding. More preferably, the thickness of the copper metal layer is 60 μm.
Further, the upper metal layer 1 is a single layer of nickel, palladium, gold, silver, tin or lead, or a composite layer metal structure of two or more layers of nickel, palladium, gold, silver, tin and lead. The main function of the upper metal layer 1 is to protect the device.
In one embodiment, the barrier layer 3, the copper metal layer 2 and the upper metal layer 1 can be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating or electroless plating.
As shown in fig. 2, which is a schematic process flow diagram of a method for manufacturing a thin film structure suitable for a copper-metallized semiconductor device, fig. 2 illustrates that the manufacturing method in the present application includes the following steps:
the method comprises the following steps: sequentially growing an adhesion layer 4 and a barrier layer 3 on a substrate 5 by means of physical vapor deposition, chemical vapor deposition, atomic layer deposition or chemical plating;
step two: forming a pattern on the barrier layer 3 by a photolithography process;
step three: in the formed pattern, sequentially forming a copper metal layer 2 and an upper metal layer 1 on a barrier layer 3 in a physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating or chemical plating mode;
step four: removing the photoresist 6 by a dry photoresist removing mode or a wet photoresist removing mode;
step five: and removing the redundant parts of the barrier layer and the adhesion layer by means of dry etching or wet etching.
The thin film structure of the present invention has the following advantages: the film structure is simple in structure and small in stress, and can form good ohmic contact with a substrate material, so that the power loss of a device is reduced; moreover, the adhesion layer is matched with the barrier layer to effectively prevent copper atoms from diffusing to the substrate material; the upper layer metal and the lower layer substrate can be effectively bonded, and the metal layer on the surface of the device is prevented from falling off.
While the invention has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (9)

1. A film structure suitable for copper metallized semiconductor device is characterized in that it includes a copper metal layer, a barrier layer and an adhesion layer which are arranged between an upper metal layer and a substrate in turn,
the barrier layer is used to prevent diffusion of copper into the substrate,
the adhesion layer is used to adhere the barrier layer to the substrate.
2. The film structure of claim 1, wherein the adhesion layer is a single layer of aluminum, tungsten, titanium, aluminum-silicon alloy, titanium-tungsten alloy, or titanium silicide, or a composite layer of any two or more of aluminum, tungsten, titanium, aluminum-silicon alloy, and titanium-tungsten alloy.
3. The film structure according to claim 1, wherein the adhesion layer is a single layer of aluminum, tungsten, titanium, aluminum-silicon alloy or titanium-tungsten alloy, and the thickness of the aluminum, tungsten, titanium, aluminum-silicon alloy or titanium-tungsten alloy is 0.001 to 5 μm.
4. The film structure of claim 1, wherein the adhesion layer is a titanium silicide layer, and the thickness of the titanium silicide layer is 0.001-2 μm.
5. The thin film structure of any of claims 1 to 4, wherein the barrier layer is a single layer of Ti, TiN, Ta, TaN, Co, or Ni, or a composite layer of two or more layers of Ti, TiN, Ta, TaN, Co, and Ni.
6. The film structure of claim 5, wherein the barrier layer has a thickness of 0.001 to 5 μm.
7. The film structure of claim 1, wherein the copper metal layer has a thickness of 0.1-100 μm.
8. The film structure according to claim 1, wherein the upper metal layer is a single-layer metal structure of nickel, palladium, gold, silver, tin or lead, or a composite-layer metal structure of two or more layers of nickel, palladium, gold, silver, tin and lead.
9. A method for preparing a thin film structure suitable for a copper metallized semiconductor device is characterized by comprising the following steps:
the method comprises the following steps: sequentially growing an adhesion layer and a barrier layer on the substrate in a physical vapor deposition, chemical vapor deposition, atomic layer deposition or chemical plating mode;
step two: forming a pattern on the barrier layer by a photoetching process;
step three: sequentially forming a copper metal layer and an upper metal layer on the barrier layer in the formed pattern in a physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating or chemical plating mode;
step four: removing the photoresist by a dry photoresist removing mode or a wet photoresist removing mode;
step five: and removing the redundant parts of the barrier layer and the adhesion layer by means of dry etching or wet etching.
CN201811271305.0A 2018-10-29 2018-10-29 Thin film structure suitable for copper metallized semiconductor device and preparation method thereof Active CN111105990B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811271305.0A CN111105990B (en) 2018-10-29 2018-10-29 Thin film structure suitable for copper metallized semiconductor device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811271305.0A CN111105990B (en) 2018-10-29 2018-10-29 Thin film structure suitable for copper metallized semiconductor device and preparation method thereof

Publications (2)

Publication Number Publication Date
CN111105990A true CN111105990A (en) 2020-05-05
CN111105990B CN111105990B (en) 2023-06-23

Family

ID=70420057

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811271305.0A Active CN111105990B (en) 2018-10-29 2018-10-29 Thin film structure suitable for copper metallized semiconductor device and preparation method thereof

Country Status (1)

Country Link
CN (1) CN111105990B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112645275A (en) * 2020-12-11 2021-04-13 中国科学院微电子研究所 Metal microelectrode applied to high-temperature pressure sensor and preparation method thereof

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000075964A2 (en) * 1999-06-05 2000-12-14 Kim Ki Bum Method of fabricating semiconductor device employing copper interconnect structure
US6355562B1 (en) * 1998-07-01 2002-03-12 Advanced Technology Materials, Inc. Adhesion promotion method for CVD copper metallization in IC applications
US6403465B1 (en) * 1999-12-28 2002-06-11 Taiwan Semiconductor Manufacturing Company Method to improve copper barrier properties
US6740580B1 (en) * 1999-09-03 2004-05-25 Chartered Semiconductor Manufacturing Ltd. Method to form copper interconnects by adding an aluminum layer to the copper diffusion barrier
CN1783478A (en) * 2004-12-01 2006-06-07 台湾积体电路制造股份有限公司 Semiconductor element of improved electronic migration and method for forming semiconductor element
US20070023919A1 (en) * 2005-07-29 2007-02-01 Mou-Shiung Lin Bonding pad on ic substrate and method for making the same
US20070128857A1 (en) * 2005-12-06 2007-06-07 Quanta Display Inc. Method for manufacturing copper wires on substrate of flat panel display device
JP2009021570A (en) * 2007-06-12 2009-01-29 Semiconductor Energy Lab Co Ltd Semiconductor device
CN102969274A (en) * 2012-11-01 2013-03-13 上海集成电路研发中心有限公司 Method for forming copper Damascus structure
US20130221528A1 (en) * 2012-02-24 2013-08-29 Skyworks Solutions, Inc. Devices and methods related to a sputtered titanium tungsten layer formed over a copper interconnect stack structure
CN104362139A (en) * 2014-09-23 2015-02-18 上海华力微电子有限公司 Copper-interconnection diffusion barrier layer, semiconductor device and method for manufacturing copper-interconnection diffusion barrier layer
US20160379947A1 (en) * 2015-06-29 2016-12-29 Infineon Technologies Ag Semiconductor Device with Metal Structure Electrically Connected to a Conductive Structure
CN106898582A (en) * 2015-12-18 2017-06-27 株洲南车时代电气股份有限公司 A kind of semiconductor device metal membrane structure and preparation method thereof

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6355562B1 (en) * 1998-07-01 2002-03-12 Advanced Technology Materials, Inc. Adhesion promotion method for CVD copper metallization in IC applications
WO2000075964A2 (en) * 1999-06-05 2000-12-14 Kim Ki Bum Method of fabricating semiconductor device employing copper interconnect structure
US6740580B1 (en) * 1999-09-03 2004-05-25 Chartered Semiconductor Manufacturing Ltd. Method to form copper interconnects by adding an aluminum layer to the copper diffusion barrier
US6403465B1 (en) * 1999-12-28 2002-06-11 Taiwan Semiconductor Manufacturing Company Method to improve copper barrier properties
CN1783478A (en) * 2004-12-01 2006-06-07 台湾积体电路制造股份有限公司 Semiconductor element of improved electronic migration and method for forming semiconductor element
US20070023919A1 (en) * 2005-07-29 2007-02-01 Mou-Shiung Lin Bonding pad on ic substrate and method for making the same
US20070128857A1 (en) * 2005-12-06 2007-06-07 Quanta Display Inc. Method for manufacturing copper wires on substrate of flat panel display device
JP2009021570A (en) * 2007-06-12 2009-01-29 Semiconductor Energy Lab Co Ltd Semiconductor device
US20130221528A1 (en) * 2012-02-24 2013-08-29 Skyworks Solutions, Inc. Devices and methods related to a sputtered titanium tungsten layer formed over a copper interconnect stack structure
CN102969274A (en) * 2012-11-01 2013-03-13 上海集成电路研发中心有限公司 Method for forming copper Damascus structure
CN104362139A (en) * 2014-09-23 2015-02-18 上海华力微电子有限公司 Copper-interconnection diffusion barrier layer, semiconductor device and method for manufacturing copper-interconnection diffusion barrier layer
US20160379947A1 (en) * 2015-06-29 2016-12-29 Infineon Technologies Ag Semiconductor Device with Metal Structure Electrically Connected to a Conductive Structure
CN106898582A (en) * 2015-12-18 2017-06-27 株洲南车时代电气股份有限公司 A kind of semiconductor device metal membrane structure and preparation method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
宋双喜,刘玉章,毛大立,李明: "铜与硅之间W/Mo-N薄膜的扩散阻挡层性能", 功能材料与器件学报, no. 02 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112645275A (en) * 2020-12-11 2021-04-13 中国科学院微电子研究所 Metal microelectrode applied to high-temperature pressure sensor and preparation method thereof

Also Published As

Publication number Publication date
CN111105990B (en) 2023-06-23

Similar Documents

Publication Publication Date Title
JP2943805B1 (en) Semiconductor device and manufacturing method thereof
US7919835B2 (en) Semiconductor device and method for manufacturing the same
US6144100A (en) Integrated circuit with bonding layer over active circuitry
US10573611B2 (en) Solder metallization stack and methods of formation thereof
US8508018B2 (en) Barrier layers
CN103681555A (en) Structure to increase resistance to electromigration
KR100426904B1 (en) Structure for connecting interconnect lines and method of manufacturing same
SG186360A1 (en) Methods, devices, and materials for metallization
JP2008527739A (en) Interconnect structure with covering cap and method of manufacturing the same
CN108461407B (en) Bond pad protection for harsh media applications
US9627335B2 (en) Method for processing a semiconductor workpiece and semiconductor workpiece
US20080274294A1 (en) Copper-metallized integrated circuits having electroless thick copper bond pads
WO2007098306A2 (en) Cap layer for an aluminum copper bond pad
CN111105990B (en) Thin film structure suitable for copper metallized semiconductor device and preparation method thereof
US20140264865A1 (en) Semiconductor device and manufacturing method thereof
JP2007180313A (en) Semiconductor device and manufacturing method thereof
JP2001274191A (en) Semiconductor device and method of manufacturing the same
US9054080B2 (en) Method for the production of an electronic component and electronic component produced according to this method
KR100744419B1 (en) Semiconductor device and method for fabricating thereof
JP2020084321A (en) Method for reducing interfacial stress accumulation of two-sided copper plating layer and aluminum nitride substrate
RU2717264C1 (en) Method of using platinum metallization in system of redistribution of contact pads of crystals of integrated microcircuits and semiconductor devices
JPH11102911A (en) Semiconductor device and its manufacture
KR20030087131A (en) Metal line with a diffusion barrier and fabrication method thereof
KR100236093B1 (en) Structure of metal interconnector of semiconductor device and method of fabricating the same
CN111463168A (en) Metal interconnection structure and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20200928

Address after: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province

Applicant after: Zhuzhou CRRC times Semiconductor Co.,Ltd.

Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169

Applicant before: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant