CN111105353A

CN111105353A - Image amplification method based on FPGA

Info

Publication number: CN111105353A
Application number: CN201911294232.1A
Authority: CN
Inventors: 朱翠林; 叶晓峰
Original assignee: Suzhou Retina Electronic Technology Co ltd
Current assignee: Suzhou Retina Electronic Technology Co ltd
Priority date: 2019-12-16
Filing date: 2019-12-16
Publication date: 2020-05-05

Abstract

The invention discloses an image amplification method based on an FPGA (field programmable gate array), which comprises the following steps of: defining a step size step in the FPGA; setting an adder, wherein the step size step is added once every time one pixel is inserted; defining the brightness values of two adjacent pixels as x and y, the current value of the adder as m, and the maximum value of the adder as N, then the brightness value Z of the newly inserted pixel passes through the formula

And (4) determining. The invention has the advantages that the image amplification process is completely processed by the FPGA, thereby improving the system operation efficiency and the system stability; the method of interpolating pixel intensity calculations strikes a balance between computational efficiency and image fidelity.

Description

Image amplification method based on FPGA

Technical Field

The invention relates to an image amplification method, in particular to an image amplification method based on an FPGA (field programmable gate array).

Background

The conventional image magnification technology is generally implemented by using a computer CPU or a computer graphics card GPU, for example, magnifying and watching a photo on a computer. The image splicing processor made of the CPU and the GPU is high in cost and poor in stability, the problem that the system is always halted after being used for a long time cannot be solved, and the system performance is obviously reduced along with the expansion of the screen and the expansion of the number of display units to be processed.

The image amplifying and distributing function is realized by using FPGA (field programmable gate array), the defects of the prior art can be overcome, the cost is only one third of that of CPU plus GPU, the performance is stable, the long-time fault-free operation can be realized, and the performance can not be reduced along with the enlargement of the scale.

The method is used for a data processing channel of an image splicing processor. The image splicing processor has the main functions of amplifying an input image, dividing the image into a plurality of parts, distributing the parts to a plurality of display units for display, and finally realizing the effect of outputting a picture by a super-large screen.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides an image amplification method based on an FPGA, and the image amplification data processing process is completely realized by the FPGA.

In order to achieve the purpose, the invention adopts the following technical scheme:

an image amplification method based on FPGA comprises the following steps:

s01, defining a step size, the step size is used to control the magnification of the input image;

s02, setting an adder, and defining the maximum value of the sum of the adder to be N; the adder adds the step length once every time a pixel is inserted; after the adder adds one or more step lengths, the added sum exceeds N, the sum overflows, if the adder overflows, the sum of the adder subtracts the maximum value N, and meanwhile, an overflow mark is output;

s03, setting a memory for storing image data of a certain line; reading out the values of two adjacent pixels from the memory for any row of image data, and defining the two pixels as a previous pixel value O (a, b) and a next pixel value O (a, b +1), wherein a and b respectively represent the row and the column of the pixel;

s04, if the adder does not overflow, defining the luminance value of the previous pixel value O (a, b) as x, the luminance value of the next pixel value O (a, b +1) as y, and the current adder value as m, the luminance value Z of the newly inserted pixel is determined by formula (1):

s05, if the adder overflows, reading the next pixel value O (a, b +2) from the memory, and meanwhile setting the pixel value O (a, b +1) as the previous pixel value and the pixel value O (a, b +2) as the next pixel value, and determining the brightness of the newly inserted pixel value through the formula (1) until the adder overflows again;

and S06, processing the next line of data after the image processing of one line is finished.

Preferably, the processing of the interpolation of each column of pixels of the image through the above steps S03 to S06.

Preferably, each pixel has three color components of red, green and blue, and the three color components are processed respectively during the image magnification processing.

Preferably, the actually required magnification of the image is defined as P, the value of the step size is calculated by formula (2),

step＝N/P (2)。

the invention has the advantages that the image amplification process is completely processed by the FPGA, thereby improving the system operation efficiency and the system stability; the method of interpolating pixel intensity calculations strikes a balance between computational efficiency and image fidelity.

Drawings

FIG. 1 is a schematic diagram of an FPGA processing image magnification system.

FIG. 2 is a digital image pixel schematic.

Fig. 3 is a schematic diagram of an interpolated image pixel.

FIG. 4 is a schematic flow chart of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

As shown in fig. 1, the present invention needs to output an enlarged image in real time after inputting a moving image. The data processing process is carried out in the FPGA, and one of the advantages of the design is that the data processing which consumes more resources is carried out by a special FPGA, so that the working efficiency of the system is optimized on the whole, and the stability of the system is improved.

A digital image, which is composed of individual pixels, as shown in fig. 2, the positions of the pixels are indicated in brackets, the legend in fig. 2 includes 3 rows and 5 columns of pixels, the brightness of each pixel can be indicated by the numbers 0 to 255, 0 being darkest and 255 being brightest.

When the image is to be enlarged, the original image is interpolated, and a new pixel is inserted between two adjacent pixels of any row and column, so that the enlargement effect can be realized. As shown in fig. 3, "+" indicates interpolated pixels.

In order to achieve the purpose, the specific implementation method is as follows:

in the field-programmable gate array (FPGA),

1) defining a step size, wherein the step size is used for controlling the magnification of the input image, and the magnification is larger when the step size is smaller.

2) Setting an adder, and defining the maximum value of the sum of the adder to be N; the adder adds the step length once every time one pixel is output; after the adder adds one or more step lengths, the added sum value exceeds N, and the sum value overflows; upon overflow, the sum of the adders subtracts the maximum value N while outputting the overflow flag, which is calculated as follows:

count＝count+step

if(count>＝N)

count＝count–N

3) the magnification factor is calculated according to the following formula,

multiple N/step

In practical application, the value of step to be set is calculated according to the needed magnification factor,

step is N/multiple

4) Setting a memory for storing image data of one line;

5) at the beginning of each line, values for 2 pixels, e.g., o (1, 1), o (1, 2) are read out from the line memory, and o (1, 1) is set to be the "previous pixel value" and o (1, 2) is set to be the "next pixel value".

6) The calculation of the adder plus step size begins, as long as the adder does not overflow, the pixel displayed at this time is the value between the 2 pixels just read,

7) the luminance value of the interpolated pixel is calculated by an algorithm of linear interpolation, for example, when the value of the adder is m, using the following formula to calculate the luminance value of the interpolated pixel,

(previous pixel value x (N-m) + subsequent pixel value x m)/N

8) When the adder overflows, subtracting N from the sum, putting the result in the adder, and continuing to add the step length in the next time; at the same time, a new pixel value, e.g. o (1, 3), is read from the memory, while the update setting o (1, 2) is "previous pixel value" and o (1, 3) is "next pixel value"

9) The operations of steps 6, 7 are repeated until step 8 is encountered, and updates of "previous pixel value" and "next pixel value" are made.

10) After one line is processed, the process returns to step 4 to start the next line until all lines of the whole image are processed.

Each pixel has 3 color components of red, green and blue, and the 3 color components need to be processed respectively during amplification processing. And respectively realizing complete image amplification processing through the steps.

Claims

1. An image amplification method based on FPGA is characterized by comprising the following steps:

2. The method for enlarging an image according to claim 1, wherein the step S03 to S06 is used to process the insertion of each column of pixels in the image.

3. An image amplification method based on FPGA is characterized in that each pixel has red, green and blue color components, and the three color components are respectively processed during image amplification processing.

4. An image amplification method based on FPGA is characterized in that the amplification factor actually needed by an image is defined as P, the value of step length is calculated by a formula (2),

step＝N/P (2)。