CN111081772A - Gallium nitride transistor and method for manufacturing the same - Google Patents

Gallium nitride transistor and method for manufacturing the same Download PDF

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Publication number
CN111081772A
CN111081772A CN201911407484.0A CN201911407484A CN111081772A CN 111081772 A CN111081772 A CN 111081772A CN 201911407484 A CN201911407484 A CN 201911407484A CN 111081772 A CN111081772 A CN 111081772A
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layer
gallium nitride
hole injection
gate structure
manufacturing
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逯永建
贾利芳
肖金平
闻永祥
李东昇
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Hangzhou Silan Integrated Circuit Co Ltd
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Hangzhou Silan Integrated Circuit Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The application discloses a gallium nitride transistor and a manufacturing method thereof, comprising the following steps: forming a gate stack in a first region over the barrier layer, the gate stack including a gate structure layer and a first intervening layer between the gate structure layer and the barrier layer; and forming a first hole injection layer in a second region above the barrier layer, the first and second regions being spaced apart from each other, wherein the step of forming the gate stack includes patterning the hard mask layer using the first resist mask, patterning the doped layer using the first resist mask to form a gate structure layer, and patterning the insertion layer using the hard mask layer to form a first insertion layer. The manufacturing method uses the hard mask layer in the subsequent patterning process, can avoid dislocation of multiple times of photoetching, and simplifies the manufacturing process of the gallium nitride transistor and improves the yield of products. The gallium nitride transistor injects charges into a channel layer using the first hole injection layer to release electrons trapped at a trap level, and thus can obtain a stable on-resistance.

Description

Gallium nitride transistor and method for manufacturing the same
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a gallium nitride transistor and a method for manufacturing the same.
Background
Compared with semiconductor materials such as silicon, gallium arsenide and the like, the wide-bandgap semiconductor material gallium nitride (GaN) has a larger bandgap width (3.4eV), a stronger critical breakdown field strength and a higher electron transfer rate, is widely concerned by researchers at home and abroad, and has huge advantages and potentials in the aspects of power electronic power devices and high-frequency power devices. As a typical representative of the third generation wide bandgap semiconductor, the gallium nitride material not only has the characteristics of large forbidden bandwidth, high critical breakdown electric field, large electron saturation drift velocity, high temperature resistance, radiation resistance, good chemical stability and the like, but also can form a material with high concentration (more than 10) with aluminum gallium nitrogen and the like due to the polarization effect of the gallium nitride material13cm-2) And high mobility (greater than 2000 cm)2The two-dimensional electron gas (2DEG) of/V.s) is very suitable for preparing power switch devices, and becomes a research hotspot in the field of current power devices.
At present, a gallium nitride single crystal substrate is difficult to obtain, and most of gallium nitride films are realized by performing heteroepitaxy on other substrates. Common substrates include silicon, sapphire, and silicon carbide. Due to the large lattice mismatch and thermal strain between gan and the substrate, the defect density of gan epitaxial materials can be 3 to 4 orders of magnitude higher than that of si materials. In addition, in order to achieve a high breakdown voltage, carbon, iron or magnesium doping is performed on the high-resistance nitride layer. Defects and impurities in the gallium nitride channel layer can form trap levels. At a reverse high pressure, the trap energy level will trap electrons. As a result, when the gallium nitride transistor is turned on again, the on-resistance increases, and the device stability and reliability deteriorate.
As a further improved device structure, composite stacks are formed in the gate region and the drain region of the gallium nitride transistor, respectively. In a reverse off state, holes are injected into the channel layer using the drain region hole injection layer, so that electrons trapped at the trap level can be released. Therefore, a substantially constant on-resistance can be obtained when the gallium nitride transistor is turned back on.
However, the method of manufacturing the gallium nitride transistor is complicated in process, including secondary photolithography after the patterning step of the insertion layer and additional epitaxial growth, and thus has a problem of secondary photolithography dislocation. As a result, in the composite stack of the gate region, the gate structure layer and the insertion layer are misaligned with each other, resulting in the malfunction of the gan transistor.
Disclosure of Invention
In view of the above, the present invention provides a gan transistor and a method for fabricating the same, in which a hard mask layer is patterned during the formation of a gate structure layer and used in a subsequent patterning process, thereby simplifying a process for fabricating the gan transistor and improving a product yield.
According to an aspect of the present invention, there is provided a method of manufacturing a gallium nitride transistor, including: forming a barrier layer on a substrate; forming a gate stack in a first region over the barrier layer, the gate stack comprising a gate structure layer and a first intervening layer between the gate structure layer and the barrier layer; and forming a first hole injection layer in a second region above the barrier layer, the first region and the second region being spaced apart from each other, wherein the step of forming the gate stack includes patterning a hard mask layer using a first resist mask, patterning a doped layer using the first resist mask to form the gate structure layer, and patterning an insertion layer using the hard mask layer to form the first insertion layer.
Preferably, the insertion layer is patterned with a second resist mask to form the first hole injection layer while the insertion layer is patterned with the hard mask layer to form the first insertion layer.
Preferably, the gate stack is formed by a single photolithographic etch.
Preferably, the hard mask layer is removed after patterning the insertion layer.
Preferably, the doped layer is formed using an epitaxial growth method.
Preferably, the gate structure layer, the first insertion layer and the first hole injection layer are respectively composed of doped nitride.
Preferably, the dopant distribution in the gate structure layer, the first insertion layer, and the first hole injection layer is any one of fixed composition, graded composition, and abrupt composition.
Preferably, the gate structure layer includes a p-type dopant.
Preferably, the dopant doped in the gate structure layer includes any one selected from magnesium, calcium, zinc beryllium or a combination thereof.
Preferably, before the step of forming the barrier layer on the substrate, the method further includes: forming a nucleation layer on a substrate; forming a buffer layer on the nucleation layer; forming a gallium nitride channel layer on the buffer layer, the barrier layer being on the gallium nitride channel layer.
Preferably, the doping concentration of the gate structure layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer under the gate stack is in an off state at zero bias.
Preferably, the first insertion layer and the first hole injection layer include a p-type dopant.
Preferably, the dopant incorporated in the first hole injection layer includes any one selected from magnesium, calcium, zinc beryllium, or a combination thereof.
Preferably, the doping concentration of the first hole injection layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer located below the first hole injection layer is in an on state at zero bias, and the first hole injection layer injects holes into the barrier layer in a reverse off state.
Preferably, the thickness of the first hole injection layer is reduced by etching, so that a channel in the gallium nitride channel layer below the first hole injection layer is in an on state under zero bias, and the first hole injection layer injects holes into the channel in the gallium nitride channel layer in a reverse off state.
Preferably, after the step of forming the gate stack and the first hole injection layer, the method further comprises: and forming a source electrode, a drain electrode, and a gate electrode between the source electrode and the drain electrode over the barrier layer, respectively, wherein the gate electrode and the gate structure layer are in contact with each other, the source electrode and the barrier layer are in contact with each other, a first portion of the drain electrode and the first hole injection layer are in contact with each other, and a second portion and the barrier layer are in contact with each other.
Preferably, the gate electrode forms a schottky contact with the gate structure layer.
Preferably, the source electrode and the drain electrode form ohmic contact with the barrier layer.
Preferably, a two-dimensional electron gas is formed between the channel layer and the barrier layer.
Preferably, the method further comprises forming a second insertion layer between the first insertion layer and the gate structure layer, the second insertion layer serving as a stop layer in the step of patterning the doping layer using the first resist mask.
Preferably, the gate structure layer is a p-type doped gallium nitride layer, the first insertion layer is a p-type doped gallium nitride layer, and the second insertion layer is a p-type doped aluminum gallium nitride layer.
Preferably, the thickness of the second insertion layer is one fifth to one twentieth of the thickness of the gate structure layer.
Preferably, a second hole injection layer is further included between the drain electrode and the first hole injection layer, the second hole injection layer serving as a stop layer in the step of patterning the doped layer using the first resist mask.
Preferably, the first hole injection layer is a p-type doped gallium nitride layer, and the second hole injection layer is a p-type doped aluminum gallium nitride layer.
According to another aspect of the present invention, there is provided a gallium nitride transistor comprising: a barrier layer on the substrate; a gate stack in a first region over the barrier layer, the gate stack comprising a gate structure layer and a first intervening layer between the gate structure layer and the barrier layer; and a first hole injection layer located in a second region above the barrier layer, the first and second regions being spaced apart from each other, wherein a drain electrode of the gallium nitride transistor is in contact with both the first hole injection layer and the barrier layer.
Preferably, the gate structure layer, the first insertion layer and the first hole injection layer are respectively composed of doped nitride.
Preferably, the dopant distribution in the gate structure layer, the first insertion layer, and the first hole injection layer is any one of fixed composition, graded composition, and abrupt composition.
Preferably, the gate structure layer includes a p-type dopant.
Preferably, the dopant doped in the gate structure layer includes any one selected from magnesium, calcium, zinc beryllium or a combination thereof.
Preferably, between the substrate and the barrier layer, further comprising: a nucleation layer located on the substrate; a buffer layer on the nucleation layer; a gallium nitride channel layer on the buffer layer; the barrier layer is on the gallium nitride channel layer.
Preferably, the doping concentration of the gate structure layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer under the gate stack is in an off state at zero bias.
Preferably, the first insertion layer and the first hole injection layer include a p-type dopant.
Preferably, the dopant incorporated in the first hole injection layer includes any one selected from magnesium, calcium, zinc beryllium, or a combination thereof.
Preferably, the doping concentration of the first hole injection layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer located below the first hole injection layer is in an on state at zero bias, and the first hole injection layer injects holes into the barrier layer in a reverse off state.
Preferably, the gate electrode of the gallium nitride transistor and the gate structure layer are in contact with each other, and the source electrode and the drain electrode of the gallium nitride transistor and the barrier layer are in contact with each other.
Preferably, the gate electrode forms a schottky contact with the gate structure layer.
Preferably, the source electrode and the drain electrode form ohmic contact with the barrier layer.
Preferably, a two-dimensional electron gas is formed between the gallium nitride channel layer and the barrier layer.
Preferably, a second insertion layer is further included between the first insertion layer and the gate structure layer.
Preferably, the gate structure layer is a p-type doped gallium nitride layer, the first insertion layer is a p-type doped gallium nitride layer, and the second insertion layer is a p-type doped aluminum gallium nitride layer.
Preferably, the thickness of the second insertion layer is one fifth to one twentieth of the thickness of the gate structure layer.
Preferably, a second hole injection layer is further included between the drain electrode and the first hole injection layer.
Preferably, the first hole injection layer is a p-type doped gallium nitride layer, and the second hole injection layer is a p-type doped aluminum gallium nitride layer.
According to the manufacturing method of the gallium nitride transistor, the hard mask layer is patterned when the gate structure layer is formed, and the hard mask layer is used for a patterning process of forming the insertion layer subsequently. The manufacturing method adopts one-time photoetching to form the pattern of the gate stack, utilizes the hard mask layer to retain the mask pattern, and can respectively form the gate structure layer and the first insertion layer in the gate stack in different etching steps. According to the manufacturing method, the hard mask layer is used for the subsequent patterning process for forming the first insertion layer, the alignment deviation of the secondary photoetching pattern is avoided, the design size of the grid can be reduced, the dislocation problem of the secondary photoetching is avoided, and meanwhile, the secondary epitaxial process is avoided, so that the manufacturing process of the gallium nitride transistor is simplified and the product yield is improved.
In a preferred embodiment, the manufacturing method includes forming an insertion layer, a doping layer and a hard mask layer on the barrier layer in this order before the step of forming the first insertion layer and the first hole injection layer, wherein the doping layer is an epitaxially grown nitride layer. Since the epitaxial growth is performed before the patterning step, the manufacturing process of the gallium nitride transistor can be further simplified and the product yield can be improved.
The gallium nitride transistor formed by the manufacturing method has a gate stack sandwiched between a gate electrode and a barrier layer, the gate stack including a stacked gate structure layer and a first insertion layer. The first insertion layer is made of P-type doped nitride, and can be used as an etching stop layer of the gate structure layer and can effectively reduce gate leakage current.
The gallium nitride transistor also includes a first hole injection layer on the barrier layer. The first hole injection layer is composed of, for example, P-type doped nitride. The drain electrode and the first hole injection layer are in contact with each other. By modulating the doping concentration of the first hole injection layer or etching and thinning, the first hole injection layer enables the channel layer to be in a conducting state under zero bias, and injects holes into the channel layer in a reverse cut-off state to release captured electrons, so that the increase of the dynamic on-resistance of the gallium nitride transistor is inhibited, the stability of the dynamic resistance is increased, and the stability and the reliability of the gallium nitride transistor are improved.
In a preferred embodiment, a second insertion layer is further included between the first insertion layer and the gate structure layer, and the second insertion layer can also serve as an etching stop layer, so that the etching process can be accurately stopped on the second insertion layer, underetching of the gate structure layer or overetching of the first insertion layer can be avoided, and stability of the process is improved.
In a preferred embodiment, the first hole injection layer further includes a second hole injection layer which can also be used as an etching stop layer, so that the etching process can be accurately stopped on the second hole injection layer, the consistency of the thickness of the hole injection layer is ensured, and the stability of the process is increased.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description only relate to some embodiments of the present invention and are not limiting on the present invention.
Fig. 1 shows a schematic structural view of a gallium nitride transistor according to a first embodiment of the present invention.
Fig. 2 shows a flowchart of a method of manufacturing a gallium nitride transistor according to a first embodiment of the present invention.
Fig. 3a to 3e show cross-sectional views of a gallium nitride transistor according to a first embodiment of the invention at different stages of the method, respectively.
Fig. 4 shows a schematic structural diagram of a gallium nitride transistor according to a second embodiment of the present invention.
Fig. 5a to 5e show cross-sectional views of a gallium nitride transistor according to a second embodiment of the invention at different stages of its manufacturing method, respectively.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the invention may be practiced in other ways than those described herein, and it will be apparent to those skilled in the art that the invention can be similarly generalized without departing from the spirit of the invention, and therefore the invention is not limited to the specific embodiments disclosed below. Next, the present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration when describing the embodiments of the present invention, and the drawings are only examples, which should not limit the scope of the present invention. In addition, three dimensional dimensions of length, width and depth should be included in actual manufacturing.
< first embodiment >
Fig. 1 shows a schematic structural view of a gallium nitride transistor according to a first embodiment of the present invention.
As shown in fig. 1, a gallium nitride transistor 100 according to a first embodiment of the present invention includes: substrate 101, nucleation layer 102, buffer layer 103, channel layer 104, barrier layer 105, gate stack 210, first hole injection layer 221, gate electrode 301, source electrode 302, and drain electrode 303. Wherein the gate stack 210 comprises: a stacked first insertion layer 211 and a gate structure layer 212.
A nucleation layer 102, a buffer layer 103, a channel layer 104, and a barrier layer 105 are sequentially formed on a substrate 101. The substrate 101 is composed of, for example, any one of silicon, sapphire, and silicon carbide. The nucleation layer 102 is composed of, for example, gallium nitride or aluminum nitride. The buffer layer 103 is made of, for example, any one of aluminum gallium nitride of different aluminum compositions or semi-insulating high-resistance gallium nitride self-doped with carbon. The channel layer 104 is, for example, an epitaxially grown gallium nitride layer, and the barrier layer 105 may, for example, be made of a material including aluminum gallium nitride having an aluminum composition of 5% to 30%, indium aluminum gallium nitride, aluminum nitride, or the like. The channel layer 104 and the barrier layer 105 form a heterojunction, and a two-dimensional electron gas is formed between the channel layer 104 and the barrier layer 105.
Gate stack 210 is situated on barrier layer 105. In this embodiment, the first insertion layer 211 is located between the gate structure layer 212 and the barrier layer 105, and both the gate structure layer 212 and the first insertion layer 211 are p-type doped nitride, for example, composed of any one of aluminum nitride, aluminum gallium nitride, or gallium nitride, and further, the dopant profile is any one of fixed composition, graded composition, and abrupt change in composition, including any one of p-type dopants selected from magnesium, calcium, zinc beryllium, or a combination.
A first hole injection layer 221 is located on the barrier layer 105, spaced apart from the gate stack 210 in a lateral direction. In this embodiment, the first hole injection layer 221 is a p-type doped nitride, and further, the dopant distribution in the first hole injection layer 221 is any one of fixed composition, graded composition, and abrupt composition. The first hole injection layer 221 includes any one p-type dopant selected from magnesium, calcium, zinc beryllium, or a combination thereof. The doping type and the doping concentration of the first hole injection layer 221 are selected such that a two-dimensional electron gas between the channel layer 104 and the barrier layer 105 located below the first hole injection layer 221 is in an on state at zero bias, and the first hole injection layer 221 injects holes into the two-dimensional electron gas between the channel layer 104 and the barrier layer 105 in a reverse off state.
The gate electrode 301 is located between the source electrode 302 and the drain electrode 303. Gate electrode 301 is located on gate stack 210. The gate electrode 301 and the gate structure layer 212 in the gate stack 210 contact each other, thereby forming a schottky contact. A source electrode 302 is located on the barrier layer 105. A first portion of the drain electrode 303 is located on the first hole injection layer 221 and a second portion is located on the barrier layer 105. The source electrode 302 and the drain electrode 303 form ohmic contact with the barrier layer 105 by Rapid Thermal Annealing (RTA), and the first portion of the drain electrode 303 and the first hole injection layer 221 contact each other, thereby forming schottky contact.
Any one of the gate electrode 301, the source electrode 302, and the drain electrode 303 is composed of, for example, any one of titanium, aluminum, nickel, gold, silver, platinum, tungsten, copper, tantalum, molybdenum, titanium tungsten, titanium nitride, or an alloy combination thereof.
In this embodiment, the first hole injection layer 221 may inject holes into the channel layer 104 by adjusting the doping concentration of the first hole injection layer 221, such as p-type doping with magnesium, calcium, zinc beryllium, or a combination, so that a two-dimensional electron gas formed between the channel layer 104 and the barrier layer 105 under the first hole injection layer 221 is in an on state at zero bias and in a reverse off state, so that the trapped electrons are released. When the gallium nitride transistor is turned on again, the on-resistance of the transistor is maintained to be approximately unchanged, so that the stability of the dynamic on-resistance of the device is improved. The gate stack 210 is composed of a gate structure layer 212 and a first insertion layer 211, and two-dimensional electron gas formed between the channel layer 104 and the barrier layer 105 under the gate stack 210 is in an off state under zero bias by adjusting the doping concentration of the gate structure layer 212.
In an alternative embodiment, in order to realize that the two-dimensional electron gas is in an on state at zero bias and in a reverse off state, the thickness of the first hole injection layer 221 may be etched to be thin.
Fig. 2 shows a flowchart of a method of manufacturing a gallium nitride transistor according to a first embodiment of the present invention. The individual steps of the manufacturing method are explained in detail below with reference to the cross-sectional views shown in fig. 3a to 3 e.
In step S01, the nucleation layer 102, the buffer layer 103, the channel layer 104, the barrier layer 105, the insertion layer 201, and the doping layer 202 are sequentially formed on the substrate 101, as shown in fig. 3a and 3 b.
In this step, the nucleation layer 102, the buffer layer 103, the channel layer 104, the barrier layer 105, the insertion layer 201, and the doping layer 202 are formed, for example, using a Metal Organic Chemical Vapor Deposition (MOCVD), a Molecular Beam Epitaxy (MBE), or other methods. The processes for forming the various material layers are known in the art and will not be described in detail herein.
After cleaning the substrate 101, a nucleation layer 102 is grown on the substrate 101. The material of the substrate 101 may include silicon, silicon carbide, sapphire, or the like, and the material of the nucleation layer 102 may include gallium nitride, aluminum nitride, or the like.
Further, a buffer layer 103 is grown on the nucleation layer 102, wherein the material of the buffer layer 103 may include carbon self-doped semi-insulating high-resistance gallium nitride, aluminum gallium nitride.
Further, a channel layer 104 is grown on the buffer layer 103, wherein the material of the channel layer 104 may be unintentionally doped gallium nitride, aluminum gallium nitride, or the like.
Further, a barrier layer 105 is grown on the channel layer 104, wherein a two-dimensional electron gas is formed at an interface of the channel layer 104 and the barrier layer 105, and a material of the barrier layer 105 may include nitride such as aluminum gallium nitride, indium aluminum gallium nitride, aluminum nitride, or the like having an aluminum composition of 5% to 30%.
Further, an insertion layer 201 is grown on the barrier layer 105. The insertion layer 201 is composed of, for example, any one or more of p-type doped aluminum nitride, aluminum gallium nitride, or gallium nitride.
Further, a doped nitride layer is epitaxially grown on the insertion layer 201, thereby forming a p-type doped layer 202. The doped layer 202 is for example made of a nitride, such as a binary or polynary nitride containing In, Ga, Al, etc., such as any one or more of aluminum nitride, aluminum gallium nitride or gallium nitride, wherein the dopant for example comprises any one p-type dopant selected from magnesium, calcium, zinc beryllium, or a combination thereof. The dopant profile in the doped layer 202 is any one of fixed composition, graded composition, and abrupt composition.
Then, in step S02, a hard mask layer 203 is formed on the doped layer 202, as shown in fig. 3 b.
In this step, the hard mask layer 203 is formed by, for example, sputtering, PECVD, or the like. The processes for forming the various material layers are known in the art and will not be described in detail herein.
The hard mask layer 203 is composed of, for example, any one of silicon oxide, silicon nitride, or other materials.
Then, in step S03, the hard mask layer 203 and the doped layer 202 are patterned using the resist mask PR1 to form the gate structure layer 212 in the gate stack 210, as shown in fig. 3 c.
In this step, for example, a resist layer is formed on the hard mask layer 203, and an opening pattern is formed in the resist layer using a photolithography method to obtain a resist mask PR 1. The resist mask PR1 blocks the gate region of the gan transistor. The exposed portions of the hard mask layer 203 and the doped layer 202 are then removed through the openings in the resist mask PR1 using a dry or wet etch process. Etching is stopped at the surface of the insertion layer 201 by controlling the etching time or using a selective etchant. After the etching step, the resist mask PR1 is removed by ashing or solvent dissolution.
Then, in step S04, the insertion layer 201 is patterned using the resist mask PR2 and the mask layer 203 to form the first insertion layer 211 of the gate stack 210, and the first hole injection layer 221, as shown in fig. 3 d.
In this step, for example, a resist layer is formed on the insertion layer 201, and an opening pattern is formed in the resist layer using a photolithography method to obtain a resist mask PR 2. The mask layer 203 and the resist mask PR2 block the gate region and the drain region of the gallium nitride transistor, respectively. The exposed portions of the insertion layer 201 are then removed via the openings collectively defined by the hard mask layer 203 and the resist mask PR2 using a dry or wet etching method. Etching is stopped at the surface of the barrier layer 105 by controlling the time of etching, or using a selective etchant. After the etching step, the resist mask PR2 is removed by dissolving with an ashing solvent.
In the semiconductor structure obtained in this step, a gate stack 210 has been formed in the gate region above barrier layer 105, gate stack 210 including a first insertion layer 211 and a gate structure layer 212. In this embodiment, the first insertion layer 211 is, for example, a p-type doped gallium nitride layer, and the gate structure layer 212 is, for example, a p-type doped gallium nitride layer
Then, in step S05, the hard mask layer 203 is removed. The hard mask layer 203 is removed, for example, by a selective etching or etching solution.
Then, in step S06, the gate electrode 301, the source electrode 302, and the drain electrode 303 are formed as shown in fig. 3 e.
A gate electrode is formed on gate stack 210. A gate metal is deposited on the gate stack 210, a gate metal contact area is opened by gluing and photolithography, and a gate electrode 301 is formed on the gate structure layer 212 by electron beam evaporation or sputtering. The gate electrode 301 and the gate structure layer 212 contact each other. The gate metal is made of titanium, aluminum, nickel, gold, silver, platinum, tungsten, copper, tantalum, molybdenum, titanium tungsten, titanium nitride or an alloy combination thereof, and the gate electrode 301 and the gate structure layer 212 are annealed at a high temperature to form a schottky contact.
Further, source and drain metals are deposited on the barrier layer 105, and a source electrode 302 and a drain electrode 303 are formed on the barrier layer 105 by electron beam evaporation, sputtering, or the like. The source metal may be titanium, aluminum, nickel, gold, silver, platinum, tungsten, copper, tantalum, molybdenum, titanium tungsten, titanium nitride, or an alloy thereof, and may be annealed to form an ohmic contact between the source electrode 302 and the barrier layer 105.
< second embodiment >
Fig. 4 shows a schematic structural diagram of a gallium nitride transistor according to a second embodiment of the present invention.
As shown in fig. 4, a gallium nitride transistor 200 according to a first embodiment of the present invention includes: substrate 101, nucleation layer 102, buffer layer 103, channel layer 104, barrier layer 105, gate stack 310, drain stack 320, gate electrode 301, source electrode 302, and drain electrode 303. The gate stack 310 includes: a first insertion layer 211, a second insertion layer 231, and a gate structure layer 212 stacked. The drain stack 320 includes: a first hole injection layer 221 and a second hole injection layer 232 are stacked.
The gate stack 310 and the drain stack 320 are located on the barrier layer 105 and are laterally spaced apart from each other. In this embodiment, the first insertion layer 211, the second insertion layer 231 and the gate structure layer 212 in the gate stack 310 are all p-type doped nitrides, for example, composed of any one of aluminum nitride, aluminum gallium nitride or gallium nitride, and further, the dopant profile is any one of fixed composition, graded composition and abrupt change composition, including any one of p-type dopants selected from magnesium, calcium, zinc beryllium or a combination. For example, the first insertion layer 211 is a p-type doped gan layer, the second insertion layer 231 is a p-type doped algan layer, and the gate structure layer 212 is a p-type doped gan layer. For example, the thickness of the second insertion layer 231 is one fifth to one twentieth of the thickness of the gate structure layer 212.
The first hole injection layer 221 and the second hole injection layer 232 in the drain stack 320 are both p-type doped nitrides, for example, composed of any one of aluminum nitride, aluminum gallium nitride, or gallium nitride, and further, the dopant profile is any one of fixed composition, graded composition, and abrupt change in composition, including any one of p-type dopants selected from magnesium, calcium, zinc beryllium, or a combination. For example, the first hole injection layer 221 is a p-type doped gallium nitride layer, and the second hole injection layer 232 is a p-type doped aluminum gallium nitride layer.
Other aspects of the gallium nitride transistor 200 according to the second embodiment are the same as the first embodiment and will not be described in detail herein. The steps of the method for manufacturing a gallium nitride transistor according to the second embodiment will be briefly described with reference to fig. 5a to 5 e.
A nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105, insertion layers 2011 and 2012, a doping layer 202, and a hard mask layer 203 are sequentially formed on a substrate 101, as shown in fig. 5 a.
In this step, the nucleation layer 102, the buffer layer 103, the channel layer 104, the barrier layer 105, the insertion layers 2011 and 2012, the doping layer 202, and the hard mask layer 203 are formed, for example, using a Metal Organic Chemical Vapor Deposition (MOCVD) or a Molecular Beam Epitaxy (MBE) method or other methods. The processes for forming the various material layers are known in the art and will not be described in detail herein.
The insertion layer 2011 and the insertion layer 2012 are composed of, for example, p-type doped aluminum nitride, aluminum gallium nitride, or gallium nitride, specifically, the insertion layer 2011 is, for example, a p-type doped gallium nitride layer, and the insertion layer 2012 is, for example, a p-type doped aluminum gallium nitride layer.
In this embodiment, the steps of the nucleation layer 102, the buffer layer 103, the channel layer 104, the barrier layer 105, the doping layer 202, and the hard mask layer 203 are the same as those of the first embodiment, and will not be described in detail herein.
Further, the hard mask layer 203 and the doped layer 202 are patterned using a resist mask PR1 to form a gate structure layer 212 in the gate stack 310, as shown in fig. 5 b.
Further, the insertion layers 2011 and 2012 are patterned using the resist mask PR2 and the hard mask layer 203 to form the first and second insertion layers 211 and 231 in the gate stack 310 and the drain stack 320, as shown in fig. 5 c.
In this embodiment, gate stack 310 includes: a first insertion layer 211, a second insertion layer 231, and a gate structure layer 212 stacked. The drain stack 320 includes: a first hole injection layer 221 and a second hole injection layer 232 are stacked. Specifically, the first and second insertion layers 211 and 231 of the gate stack 310 and the first and second hole injection layers 221 and 232 of the drain stack 320 are formed in this step.
Further, the hard mask layer 203 and the resist mask PR2 are removed, as shown in fig. 5 d.
Further, a gate electrode 301, a source electrode 302 and a drain electrode 303 are formed, as shown in fig. 5 e.
In this embodiment, the gate structure layer 212 and the second insertion layer 231 are respectively composed of different materials. For example, the gate structure layer 212 and the second insertion layer 231 are a gallium nitride layer and an aluminum gallium nitride layer, respectively, and a selective gas etchant is used, for example, the etching gas is CL2/BCl3/O2 or SF6, and auxiliary gases such as AR, N2, HE, and the like may be added, so that the rate ratio of etching gallium nitride and aluminum gallium nitride is about 30: 1 or even higher. Therefore, in the patterning step of the gate structure layer 212 shown in fig. 5b, the insertion layer 2012 serves as an etching stop layer, which can avoid underetching of the gate structure layer 212 or overetching of the insertion layer 2011, and solve the problem of poor consistency of the hole injection region due to the influence of epitaxial uniformity and etching uniformity in the conventional process, thereby ensuring the repeatability and stability of the manufacturing process.
According to the gallium nitride transistor of the embodiment of the invention, the gate stack is clamped between the gate electrode and the barrier layer, and the gate stack comprises the gate structure layer and the first insertion layer. The first insertion layer is made of P-type doped nitride, and can be used as an etching stop layer of the gate structure layer and can effectively reduce gate leakage current.
The gallium nitride transistor also includes a first hole injection layer on the barrier layer. The first hole injection layer is composed of, for example, P-type doped nitride. The drain electrode and the first hole injection layer are in contact with each other. By modulating the doping concentration of the first hole injection layer or etching and thinning, the two-dimensional electron gas between the channel layer and the barrier layer is in a conducting state under zero bias of the first hole injection layer, and holes are injected into the two-dimensional electron gas between the channel layer and the barrier layer in a reverse cut-off state to release captured electrons, so that the increase of the dynamic conducting resistance of the gallium nitride transistor is inhibited, the stability of the dynamic resistance is increased, and the stability and the reliability of the gallium nitride transistor are improved.
In a further embodiment, a second insertion layer is further included between the first insertion layer and the gate structure layer, and the second insertion layer can also serve as an etching stop layer, so that the etching process can be accurately stopped on the second insertion layer, underetching of the gate structure layer or overetching of the first insertion layer can be avoided, and the stability of the process is improved.
In a further embodiment, a second hole injection layer is further included between the first hole injection layer and the drain electrode, and the second hole injection layer can also serve as an etching stop layer, so that an etching process can be accurately stopped on the second hole injection layer, the thickness consistency of the first hole injection layer is ensured, and the stability of a technological process is improved.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the disclosure to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (43)

1. A method of fabricating a gallium nitride transistor, comprising:
forming a barrier layer on a substrate;
forming a gate stack in a first region over the barrier layer, the gate stack comprising a gate structure layer and a first intervening layer between the gate structure layer and the barrier layer; and
forming a first hole injection layer in a second region over the barrier layer, the first and second regions being spaced apart from each other,
the step of forming the gate stack includes patterning a hard mask layer using a first resist mask, patterning a doping layer using the first resist mask to form the gate structure layer, and patterning an insertion layer using the hard mask layer to form the first insertion layer.
2. The manufacturing method according to claim 1, wherein the insertion layer is patterned with a second resist mask to form the first hole injection layer while the insertion layer is patterned with the hard mask layer to form the first insertion layer.
3. The manufacturing method according to claim 1, wherein the gate stack is formed by one photolithography etching.
4. A method of manufacturing according to claim 2 or 3, wherein the hard mask layer is removed after patterning the insertion layer.
5. The manufacturing method according to claim 1, wherein the doped layer is formed by an epitaxial growth method.
6. The manufacturing method according to claim 2, wherein the gate structure layer, the first insertion layer and the first hole injection layer are each composed of a doped nitride.
7. The manufacturing method according to claim 6, wherein the dopant distribution in the gate structure layer, the first insertion layer, and the first hole injection layer is any one of fixed composition, graded composition, and abrupt composition.
8. The method of manufacturing of claim 6, wherein the gate structure layer comprises a p-type dopant.
9. The manufacturing method according to claim 8, wherein the dopant doped in the gate structure layer comprises any one selected from magnesium, calcium, zinc beryllium, or a combination thereof.
10. The method of manufacturing of claim 1, wherein prior to the step of forming a barrier layer on a substrate, further comprising:
forming a nucleation layer on a substrate;
forming a buffer layer on the nucleation layer;
forming a gallium nitride channel layer on the buffer layer, the barrier layer being on the gallium nitride channel layer.
11. The manufacturing method of claim 10, wherein a doping concentration of the gate structure layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer under the gate stack is in an off state at zero bias.
12. The manufacturing method according to claim 6, wherein the first insertion layer and the first hole injection layer include a p-type dopant.
13. The manufacturing method according to claim 12, wherein the dopant incorporated in the first hole injection layer includes any one selected from magnesium, calcium, zinc beryllium, or a combination thereof.
14. The manufacturing method according to claim 12, wherein a doping concentration of the first hole injection layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer located below the first hole injection layer is in an on state at zero bias, and the first hole injection layer injects holes to the barrier layer in a reverse off state.
15. The manufacturing method according to claim 12, wherein the etching reduces a thickness of the first hole injection layer such that a channel in the gallium nitride channel layer located below the first hole injection layer is in an on state at zero bias and the first hole injection layer injects holes into the channel in the gallium nitride channel layer in a reverse off state.
16. The manufacturing method according to claim 1, further comprising, after the step of forming the gate stack and the first hole injection layer:
forming a source electrode, a drain electrode, and a gate electrode between the source electrode and the drain electrode, respectively, over the barrier layer,
wherein the gate electrode and the gate structure layer are in contact with each other, the source electrode and the barrier layer are in contact with each other, a first portion of the drain electrode and the first hole injection layer are in contact with each other, and a second portion and the barrier layer are in contact with each other.
17. The method of manufacturing of claim 16, wherein the gate electrode forms a schottky contact with the gate structure layer.
18. The manufacturing method according to claim 16, wherein the source electrode and the drain electrode form ohmic contact with the barrier layer.
19. The manufacturing method according to claim 1, wherein a two-dimensional electron gas is formed between the channel layer and the barrier layer.
20. The manufacturing method according to claim 1, further comprising forming a second insertion layer between the first insertion layer and the gate structure layer, the second insertion layer serving as a stop layer in the step of patterning the doping layer using the first resist mask.
21. The method of manufacturing of claim 20, wherein the gate structure layer is a p-type doped gallium nitride layer, the first intervening layer is a p-type doped gallium nitride layer, and the second intervening layer is a p-type doped aluminum gallium nitride layer.
22. The method of manufacturing of claim 21, wherein the thickness of the second insertion layer is one fifth to one twentieth of the thickness of the gate structure layer.
23. The manufacturing method according to claim 21, further comprising a second hole injection layer between the drain electrode and the first hole injection layer, the second hole injection layer serving as a stopper layer in the step of patterning the doped layer with the first resist mask.
24. The manufacturing method according to claim 23, wherein the first hole injection layer is a p-type doped gallium nitride layer, and the second hole injection layer is a p-type doped aluminum gallium nitride layer.
25. A gallium nitride transistor, comprising:
a barrier layer on the substrate;
a gate stack in a first region over the barrier layer, the gate stack comprising a gate structure layer and a first intervening layer between the gate structure layer and the barrier layer; and
a first hole injection layer located in a second region above the barrier layer, the first and second regions being spaced apart from each other,
wherein a drain electrode of the gallium nitride transistor is in contact with both the first hole injection layer and the barrier layer.
26. The gallium nitride transistor of claim 25, wherein the gate structure layer, the first insertion layer, and the first hole injection layer are each comprised of a doped nitride.
27. The gallium nitride transistor of claim 26, wherein the dopant profile in the gate structure layer, the first insertion layer, and the first hole injection layer is any one of fixed composition, graded composition, and abrupt composition.
28. The gallium nitride transistor of claim 26, wherein the gate structure layer comprises a p-type dopant.
29. The gallium nitride transistor of claim 28, wherein the dopant incorporated in the gate structure layer comprises any one selected from magnesium, calcium, zinc beryllium, or a combination thereof.
30. The gallium nitride transistor of claim 25, wherein, between the substrate and the barrier layer, further comprising:
a nucleation layer located on the substrate;
a buffer layer on the nucleation layer;
a gallium nitride channel layer on the buffer layer; the barrier layer is on the gallium nitride channel layer.
31. The gallium nitride transistor of claim 28, wherein a doping concentration of the gate structure layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer under the gate stack is in an off state at zero bias.
32. The gallium nitride transistor of claim 26, wherein the first insertion layer and the first hole injection layer comprise p-type dopants.
33. The gallium nitride transistor of claim 32, wherein the dopant incorporated in the first hole injection layer comprises any one selected from magnesium, calcium, zinc beryllium, or a combination.
34. The gallium nitride transistor according to claim 32, wherein a doping concentration of the first hole injection layer is selected such that a two-dimensional electron gas between the gallium nitride channel layer and the barrier layer located below the first hole injection layer is in an on state at zero bias and the first hole injection layer injects holes to the barrier layer in a reverse off state.
35. The gallium nitride transistor of claim 25, wherein the gate electrode and the gate structure layer of the gallium nitride transistor are in contact with each other, and the source and drain electrodes and the barrier layer of the gallium nitride transistor are in contact with each other.
36. The gallium nitride transistor of claim 35, wherein the gate electrode forms a schottky contact with the gate structure layer.
37. The gallium nitride transistor of claim 35, wherein the source and drain electrodes form ohmic contacts with the barrier layer.
38. The gallium nitride transistor of claim 25, wherein a two-dimensional electron gas is formed between the gallium nitride channel layer and the barrier layer.
39. The gallium nitride transistor of claim 25, further comprising a second intervening layer between the first intervening layer and the gate structure layer.
40. The gallium nitride transistor of claim 39, wherein the gate structure layer is a p-type doped gallium nitride layer, the first intervening layer is a p-type doped gallium nitride layer, and the second intervening layer is a p-type doped aluminum gallium nitride layer.
41. The gallium nitride transistor of claim 39, wherein the second insertion layer has a thickness that is one-fifth to one-twentieth of the thickness of the gate structure layer.
42. The gallium nitride transistor of claim 40, further comprising a second hole injection layer between the drain electrode and the first hole injection layer.
43. The gallium nitride transistor of claim 42, wherein the first hole injection layer is a p-type doped gallium nitride layer and the second hole injection layer is a p-type doped aluminum gallium nitride layer.
CN201911407484.0A 2019-12-31 2019-12-31 Gallium nitride transistor and method for manufacturing the same Pending CN111081772A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112614778A (en) * 2020-12-18 2021-04-06 江苏能华微电子科技发展有限公司 Method and device for forming multifunctional p-GaN electrode in GaN HEMT device
WO2023197213A1 (en) * 2022-04-13 2023-10-19 华为技术有限公司 Semiconductor device and working method therefor, and electronic device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112614778A (en) * 2020-12-18 2021-04-06 江苏能华微电子科技发展有限公司 Method and device for forming multifunctional p-GaN electrode in GaN HEMT device
CN112614778B (en) * 2020-12-18 2024-06-04 江苏能华微电子科技发展有限公司 Method and device for forming multifunctional p-GaN electrode in GaN HEMT device
WO2023197213A1 (en) * 2022-04-13 2023-10-19 华为技术有限公司 Semiconductor device and working method therefor, and electronic device

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