CN111064452B - Enabling signal generation circuit - Google Patents
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Abstract
The application discloses enable signal generation circuit, this enable signal generation circuit includes: a counter, an edge trigger, a first logic operation unit and a second logic operation unit; the counter is used for triggering a starting counting or resetting function according to the state of the input PWM signal and outputting a first signal; the edge trigger is used for receiving the PWM signal and the first signal and triggering and outputting a second signal according to the states of the PWM signal and the first signal; the first logic operation unit is used for carrying out logic operation on the PWM signal, the first signal and the second signal to obtain a PWM output signal, and sending the PWM output signal to the driving unit; and the second logic operation unit is used for carrying out logic operation on the first signal and the second signal to obtain an enabling signal. The technical problem that a driving system is complex in the prior art is solved.
Description
Technical Field
The present disclosure relates to the field of driving technologies, and in particular, to an enable signal generating circuit.
Background
The pulse width modulation (Pulse Width Modulation, PWM) is a method for changing the pulse width according to the amplitude of a signal wave, and is widely used in driving circuits such as motor control and power amplification, etc., for modulating the width of a series of pulses to equivalently obtain a desired waveform. In the prior art, a motor or a power amplifier is usually powered by a battery, for example, a lithium battery, and the driving capability of the motor or the power amplifier is limited due to the limitation of the battery voltage, so that in order to improve the electric driving capability, a control signal output by a control circuit is usually amplified by a driving circuit to drive the motor or the power amplifier to work.
Referring to fig. 1, a conventional driving circuit includes a boosting unit for boosting an input Battery Voltage (VBAT) and transmitting the boosted voltage to a driving unit, so as to supply the driving unit with a power driving unit for amplifying an input control signal and outputting the amplified signal. Currently, in order to make the boost unit and the driving unit work, the boost circuit is usually started by a first control signal to supply power to the driving unit, and then the driving unit is controlled by a second control signal to amplify the signal, for example, the first control signal is an enable signal, and the second control signal may be a PWM signal, that is, in the prior art, in order to make the driving circuit work, not only the PWM signal needs to be input, but also an additional enable signal needs to be input, therefore, an additional circuit is needed in the system to obtain the enable signal, which results in a complex driving system.
Disclosure of Invention
The application provides an enabling signal generating circuit which is used for solving the technical problem that a driving system is complex in the prior art.
In a first aspect, the present application provides an enable signal generating circuit connected to a driving circuit including a boosting unit and a driving unit connected to the boosting unit, the enable signal generating circuit including: a counter, an edge trigger, a first logic operation unit and a second logic operation unit; wherein,,
the counter is used for receiving PWM signals input from the outside, triggering a starting counting or resetting function according to the state of the PWM signals, and outputting a first signal;
the edge trigger is used for receiving the PWM signal and the first signal and triggering and outputting a second signal according to the states of the PWM signal and the first signal;
the first logic operation unit is configured to receive the PWM signal, the first signal, and the second signal, perform logic operation on the PWM signal, the first signal, and the second signal, obtain a PWM output signal, and send the PWM output signal to the driving unit;
the second logic operation unit is configured to receive the first signal and the second signal, perform logic operation on the first signal and the second signal, obtain an enable signal, enable the enable signal to start the boost unit, and drive the driving unit to generate a driving signal according to the PWM output signal.
In the scheme provided by the embodiment of the application, the first signal is output through the counter, the second signal is output through the edge trigger, the first logic operation unit carries out logic operation on the first signal, the second signal and the input PWM signal to obtain the PWM output signal, and the second logic operation unit carries out logic operation on the first signal and the second signal to obtain the enabling signal, namely in the scheme provided by the embodiment of the application, the enabling signal generating circuit can output the PWM signal and the enabling signal according to one path of PWM signal input, and the problem that the complexity of the system and the application is increased due to the fact that the additional enabling signal is input into the driving system is avoided.
Optionally, the enabling signal includes a first enabling signal and a second enabling signal, the first enabling signal is used for driving the boosting unit to boost the input power supply signal, the second enabling signal is used for driving the driving unit to generate the driving signal according to the PWM signal, and time delay exists between the first enabling signal and the second enabling signal.
Optionally, the method further comprises: a delay unit;
the delay unit is connected with the output end of the second logic operation unit, which outputs the second enabling signal, and is used for delaying the second enabling signal so that delay exists between the first enabling signal and the second enabling signal.
Optionally, the delay unit is a rising edge delay unit, and the rising edge delay unit is used for delaying a time point corresponding to each rising edge in the second enabling signal.
Optionally, the counter triggers to start a counting function once at each rising edge of the PWM signal, and ends counting once when the count value reaches a preset threshold;
the counter triggers the start of a reset function once each time the PWM signal goes low.
Optionally, the edge trigger comprises a first edge trigger and a second edge trigger connected with the first edge trigger, wherein,
the first edge trigger is configured to trigger and generate a third signal according to the PWM signal and the state of the first signal, and send the third signal to the second edge trigger;
the second edge trigger is configured to trigger to generate the second signal according to states of the first signal and the third signal.
Optionally, the first edge trigger and the second edge trigger are both rising edge triggers.
Optionally, if the first signal is at a high level, the first edge trigger triggers an output state to flip once at each rising edge of the PWM signal, so as to obtain the third signal;
and if the first signal is at a low level, the first edge trigger is in a reset state to obtain the third signal, and the third signal is at a low level.
Optionally, if the first signal is at a high level, the second edge trigger triggers an output state to flip once at a first rising edge of the third signal, so as to obtain the second signal;
and if the first signal is at a low level, the second edge trigger is in a reset state to obtain the second signal, and the second signal is at a low level.
Optionally, the first logic operation unit and the second logic unit are both logic and operation units.
Drawings
Fig. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a driving system according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of an enable signal generating circuit according to an embodiment of the present application;
FIG. 4a is a waveform diagram of a first signal according to an embodiment of the present disclosure;
FIG. 4b is a waveform diagram of a first signal according to an embodiment of the present disclosure;
FIG. 5 is a waveform diagram of a counter and an edge trigger output in an enable signal generating circuit according to an embodiment of the present application;
fig. 6 is a waveform diagram of the output of each unit in the enable signal generating circuit according to the embodiment of the present application;
fig. 7 is a waveform diagram of the output of each unit of the enable signal generating circuit according to the embodiment of the present application;
fig. 8 is a waveform diagram of each unit output of an enable signal generating circuit according to an embodiment of the present application;
fig. 9 is a waveform diagram of the output of each unit of the enable signal generating circuit according to the embodiment of the present application;
fig. 10 is a waveform diagram of each unit output of an enable signal generating circuit according to an embodiment of the present application.
Detailed Description
In the solutions provided by the embodiments of the present application, the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In order to better understand the technical solutions described above, the following detailed description of the technical solutions of the present application is provided through the accompanying drawings and specific embodiments, and it should be understood that the specific features of the embodiments and embodiments of the present application are detailed descriptions of the technical solutions of the present application, and not limit the technical solutions of the present application, and the technical features of the embodiments and embodiments of the present application may be combined with each other without conflict.
An enabling signal generating circuit provided in the embodiments of the present application is described in further detail below with reference to the accompanying drawings.
Referring to fig. 2, a schematic structural diagram of a driving system according to an embodiment of the present application is provided, where the driving system includes an enable signal generating circuit 1 and a driving circuit 2; wherein the enabling signal generating circuit 1 is used for generating a PWM output signal and an enabling signal according to one input PWM signal; the driving circuit 2 includes a boost unit 21 and a driving unit 22, the boost unit 21 is used for being started under the driving of the enabling signal, and supplying power to the driving unit 22, and the driving unit 22 is used for amplifying the PWM output signal under the condition that the boost unit 21 supplies power, so that the amplified PWM output signal drives the motor or the amplifier to work.
Referring to fig. 3, an enable signal generating circuit according to an embodiment of the present application is connected to a driving circuit, and includes: a counter 31, an edge trigger 32, a first logic operation unit 33, and a second logic operation unit 34; wherein,,
the counter 31 is configured to receive a PWM signal input from the outside, trigger a start count or reset function according to a state of the PWM signal, and output a first signal;
the edge trigger 32 is configured to receive the PWM signal and the first signal, and trigger to output a second signal according to states of the PWM signal and the first signal;
the first logic operation unit 33 is configured to receive the PWM signal, the first signal, and the second signal, perform logic operation on the PWM signal, the first signal, and the second signal, obtain a PWM output signal, and send the PWM output signal to the driving unit;
the second logic operation unit 34 is configured to receive the first signal and the second signal, perform logic operation on the first signal and the second signal to obtain an enable signal, so that the enable signal starts the boost unit, and drive the driving unit to generate a driving signal according to the PWM output signal.
In the scheme provided in the embodiment of the present application, the PWM signal is input not only to the counter 31 but also to the edge trigger 32 and the first logic operation unit 33. The counter 31 may be a level triggered count function, an edge triggered count function, or another type of triggered count function, and is not limited herein.
In one possible implementation, the counter 31 triggers the start of a count function once at each rising edge of the PWM signal and ends the count once when the count value reaches a preset threshold; the counter 31 triggers the reset function to be turned on once every occurrence of a low level of the PWM signal.
In the scheme provided in the embodiment of the present application, the counter 31 ends one count irrespective of the level or the edge of the PWM signal, is related to the count value, and ends one count when the count value reaches the preset threshold. Therefore, the first signal output by the counter 31 is related to the time period for which the count value of the counter 31 reaches the preset threshold, specifically, there are two cases:
in case 1, the duration of the count value of the counter 31 reaching the preset threshold value is longer than half a period of the PWM signal.
In case 2, the duration in which the count value of the counter 31 reaches the preset threshold value is not longer than half the period of the PWM signal.
With respect to the above case 1, a procedure in which the counter 31 outputs the first signal will be described below in an exemplary form.
For example, if the PWM signal is a periodic signal and the period of the PWM signal is T 1 The counter 31 outputs a high level signal at the time of counting and a low level signal at the time of resetting, and the counter 31 counts a time period t up to a preset threshold value, wherein,
specifically, the process of outputting the first signal by the counter is as follows: in the PWM signal shown in fig. 4a, t 11 At the moment (the moment corresponding to the first rising edge), the trigger counter 31 starts the counting function, outputs a high level signal, and t is a PWM signal 21 At the moment, the counter 3 finishes counting, the PWM signal is a low level signal at the moment, the counter 31 is triggered to start the reset function, the low level signal is output,this process is then repeated at each period counter 31 of the PWM signal until the PWM signal has ended, resulting in the first signal shown in fig. 4 a.
In the case 2, the process of outputting the first signal by the counter 31 will be described by taking the example of outputting the high level signal by the counter 31 at the time of counting and outputting the low level signal by the counter 31 at the time of resetting.
For example, the period of the PWM signal is T 1 The time period t for which the count value of the counter 31 reaches the preset threshold value, wherein,
specifically, the process of outputting the first signal by the counter is as follows: referring to fig. 4b, t is in the PWM signal 12 (first rising edge corresponding to time), the trigger counter 31 starts the counting function, outputs a high level signal, and t is a PWM signal 22 The counter 31 counts up, the PWM signal is at high level, the output state is kept unchanged, and the counter 31 is t in the PWM signal 3 At the moment (low level start position), the trigger counter 31 starts the reset function, outputs a low level signal, and then the counter 31 repeats the process at each period of the PWM signal until the PWM signal ends, resulting in the first signal shown in fig. 4 b.
Further, the counter 31 inputs the first signal to the edge trigger 32 after outputting the first signal. In the scheme provided in the embodiment of the present application, the edge trigger 32 triggers when the first signal is at a high level, and changes the output state according to the input PWM signal; the edge trigger 32 is in a reset state when the first signal is low.
Referring to fig. 3, in one implementation, the edge trigger 32 includes a first edge trigger 321 and a second edge trigger 322 connected to the first edge trigger 321, where the first edge trigger 321 is configured to trigger generation of a third signal according to the PWM signal and a state of the first signal, and send the third signal to the second edge trigger 322; the second edge trigger 322 is configured to trigger to generate the second signal according to the states of the first signal and the third signal.
In one implementation, the first edge trigger 321 and the second edge trigger 322 are both rising edge triggers.
Further, in the scheme provided in the embodiment of the present application, the first edge trigger 321 triggers the generation of the third signal according to the PWM signal and the state of the first signal, and a preferred mode is described below.
If the first signal is at a high level, the first edge trigger 321 triggers an output state to flip once at each rising edge of the PWM signal, so as to obtain the third signal;
if the first signal is at a low level, the first edge trigger 321 is in a reset state, so as to obtain the third signal, and the third signal is a low level signal.
Further, in the solution provided in the embodiment of the present application, the second edge trigger 322 triggers the generation of the second signal according to the states of the first signal and the third signal in various ways, and a preferred one is described below for the sake of illustration.
If the first signal is at a high level, the second edge trigger 322 triggers an output state to flip once at a first rising edge of the third signal, so as to obtain the second signal;
if the first signal is at a low level, the second edge trigger 322 is in a reset state, so as to obtain the second signal, and the second signal is at a low level.
In order to facilitate understanding of the operation principle of the first edge trigger 321 and the second edge trigger 322, the PWM signal and the first signal shown in fig. 4a are taken as an example.
For example, referring to fig. 4a, the first signal is at (t 11 ，t 21 ) Also high during the period, the PWM signal is at (t 11 ，t 21 ) The time period is high level, no rising edge exists, so the first edge trigger 321 is not triggered in the whole PWM signal time period, the third signal is output as a low level signal, and the second edge trigger 322 is similarly triggered in the whole PWM signal time periodThe segment is not triggered, and the second signal is output as a low level signal. Specifically, the waveforms of the third signal and the second signal are shown in fig. 5.
Further, in the scheme provided by the embodiment of the application, the boost unit and the driving unit can be controlled respectively by two different enabling signals, for example, the boost unit is controlled to be turned on by one enabling signal to provide a boost power supply for the driving unit, and then the driving unit is controlled to amplify the input PWM signal by the other enabling signal to obtain the PWM signal meeting the requirement. Therefore, in order to operate the driving circuit, the enable signal generating circuit needs to output two enable signals and one PWM signal.
Specifically, after the second edge trigger 322 outputs the second signal, the first signal and the PWM signal are input to the first logic operation unit 33, and logic operation is performed in the first logic operation unit 33 to obtain a PWM output signal, and the PWM output signal is input to the driving unit; the second signal and the first signal are input to the second logic operation unit 34, and the second logic operation unit 34 performs logic operation to obtain two enable signals.
In one possible implementation, the first logic unit 33 and the second logic unit 34 are both logical and operation units.
In one possible implementation manner, the enabling signals include a first enabling signal and a second enabling signal, the first enabling signal is used for driving the boosting unit to boost the input power supply signal, the second enabling signal is used for driving the driving unit to generate the driving signal according to the PWM signal, and time delay exists between the first enabling signal and the second enabling signal.
For example, referring to fig. 3, the second logic operation unit 34 has two outputs, one of which is used to output the first enable signal and the other of which is used to output the second enable signal. Since the boosting unit in the driving circuit is used for providing the boosting power for the driving circuit, the boosting unit needs to be turned on before the driving unit, and the second enabling signal needs to be delayed from the first enabling signal.
In order to delay the second enable signal by the first enable signal, the enable signal generation circuit further comprises a delay unit 35;
the delay unit 35 is connected to the output end of the second logic operation unit 34 outputting the second enable signal, and is configured to delay the second enable signal, so that there is delay between the first enable signal and the second enable signal.
In one possible implementation, the delay unit 35 is a rising edge delay unit, where the rising edge delay unit is configured to delay a time point corresponding to each rising edge in the second enable signal.
In the scheme provided by the embodiment of the application, the PWM signal input to the enable signal generating circuit has the following states:
in state 1, no pulse is present in the PWM signal.
The state 2, PWM signal is that there is one pulse.
The state 3, PWM signal is that there are at least two pulses.
In order to facilitate understanding of the process of generating the enable signal and the PWM output signal by the enable signal generating circuit based on the input PWM signal, the process of generating the enable signal and the PWM output signal will be described below by way of example with respect to the states of the three PWM signals input to the enable signal generating circuit, respectively.
1. For state 1 above, the absence of pulses in the pwm signal includes two further cases:
case 1), the PWM signal is a low level signal.
If the PWM signal is a low-level signal, the counter triggers a counting function to be started once at each rising edge in the PWM signal, and the counter finishes counting once when the count value reaches a preset threshold value, and a reset function is started at the low level of the PWM signal, so that when the PWM signal is the low-level signal, a first signal output by the counter in a reset state is the low-level signal; when the first signal is a low-level signal, the first edge trigger and the second edge trigger are both in a reset state, so that the third signal output by the first edge trigger is a low-level signal, and the second signal output by the second edge trigger is also a low-level signal; the PWM signal, the first signal and the second signal are input into a first logic operation unit to carry out logical AND operation, and the PWM output signal output by the first logic operation unit is also a low-level signal because the PWM signal, the first signal and the second signal are all low-level signals; the first signal and the second signal are input to the second logic operation unit to perform logical AND operation, and the first signal and the second signal are low level signals, so that the first enabling signal and the second signal output by the second logic operation unit are low level signals, and specifically, waveforms of the PWM signal, the first signal, the second signal, the third signal, the first enabling signal, the second enabling signal and the PWM output signal are shown in fig. 6.
Case 2), there is one rising edge in the PWM signal.
If a rising edge exists in the PWM signal, the counter triggers a counting function when the rising edge arrives, and counts after the count value reaches a threshold value, and the PWM signal is a high-level signal after the counting is finished, so that a first signal output by the counter is a low-level signal before the rising edge of the PWM signal and is a high-level signal all the time after the rising edge; in the period when the first signal is at the high level, the PWM signal is also at the high level, and no rising edge exists, so that in the period when the first signal is at the high level, the first edge trigger and the second edge trigger are not started, the first edge trigger outputs a third signal as a low level signal, and the second edge trigger outputs a second signal as a low level signal; the first logic operation unit carries out logical AND operation on the PWM signal, the first signal and the second signal, and the PWM output signal output by the first logic operation unit is a low-level signal because the second signal is a low-level signal; the second logic operation unit performs logical AND operation on the first signal and the second signal, and the first enabling signal and the second enabling signal output by the second logic operation unit are low-level signals because the second signal is low-level signal. Specifically, waveforms of the PWM signal, the first signal, the second signal, the third signal, the first enable signal, the second enable signal, and the PWM output signal are shown in fig. 7.
2. For state 2 above, one pulse is included in the pwm signal.
Referring to fig. 8, the starting position time point of the pulse in the pwm signal is t 4 The ending time point is t 5 The time point when the counter count value reaches the preset threshold value is t 6 The method comprises the steps of carrying out a first treatment on the surface of the The counter is at t 4 Triggering the starting counting function at the moment, and at t 3 The time counting is completed, so the first signal is at [ t ] 4 ，t 5 ]The time period is high level, and the other time periods are low level; at (t) 4 ，t 5 ) In the time period, no rising edge exists in the PWM signal, so that the first edge trigger and the second edge trigger are not triggered, the third signal output by the first edge trigger is a low-level signal, and the second signal output by the second edge trigger is a low-level signal; the first logic operation unit carries out logical AND operation on the PWM signal, the first signal and the second signal to obtain a PWM output signal, wherein the level of the PWM output signal is low level; the second logic operation unit performs logical AND operation on the first signal and the second signal to obtain a first enabling signal and a second enabling signal, wherein the first enabling signal and the second enabling signal are high-level signals.
3. For state 3 above, the pwm signal is such that there are at least two pulses, including the following two cases:
case 1, the counter counts only once.
Referring to fig. 9, the counter is at t 7 Starting the counting function at the moment, at t 8 Time counting is finished, [ t ] 7 ，t 8 ]The PWM signal has a plurality of pulses during a time period, at t 5 Since the PWM signal is always a low level signal after the time, the counter performs only [ t ] 7 ，t 8 ]Counting once in a time period, and outputting a first signal in [ t ] 7 ，t 8 ]A high level signal in a time period and a low level signal in other time periods; at (t) 7 ，t 8 ) In the segment, the first edge flip-flop toggles the output state once every rising edge of the PWM signal, so that the third signal outputted from the first edge flip-flop is in (t 7 ，t 8 ) A plurality of pulses are arranged in the time period, and the pulses are low-level signals in other time periods; at (t) 7 ，t 8 ) The first rising edge time of the third signal is t in a period of time 9 At the moment, the second edge trigger t 8 The moment triggers the output state to send a flip, so the second signal is in (t 9 ，t 8 ) A high level signal in a time period and a low level signal in other time periods; since the time interval (t 9 ，t 8 ) The first signal and the second signal are both high level signals in the time period, so that when the first logic operation unit performs logic AND operation on the PWM signal, the first signal and the second signal, the output PWM output signal is in (t) 9 ，t 8 ) The waveform in the time period is the same as the waveform of the PWM signal, and the other time periods are low level signals, and when the second logic operation unit performs logic AND operation on the first signal and the second signal, the output first enable signal is in (t) 9 ，t 8 ) A high level signal in a time period, and delta t exists between the rising edges of the second enabling signal and the first enabling signal 1 Time delay.
Case 2, counter performs at least two counts.
Referring to fig. 10, the counter is at t 31 Starting the counting function at the moment, at t 32 Time counting is finished, [ t ] 31 ，t 32 ]The PWM signal has a plurality of pulses during a time period, at [ t ] 32 ，t 33 ]The PWM signal is a low level signal during the period of time, so the counter is at [ t ] 31 ，t 32 ]The first signal output in the time period is high level, at [ t ] 32 ，t 33 ]The first signal output in the time period is low level, at [ t ] 33 ，t 34 ]The first signal output in the time period is high level, at t 34 The first signal output after the moment is at a low level.
The first and second edge flip-flops may be at [ t ] 31 ，t 32 ][ t ] 33 ，t 34 ]Is triggered during a time period. Specifically, the PWM signal is at [ t ] 31 ，t 32 ]Having multiple pulses within a time period, the first edge trigger being at [ t ] 31 ，t 32 ]Each rising edge of the PWM signal triggers a flip of the output state within a time period, at (t 33 ，t 34 ) The PWM signal does not have a rising edge in the period, and the first edge trigger is not triggered, so the first edge trigger outputs a third signal as shown in fig. 10. At [ t ] 31 ，t 32 ]The second edge trigger is at the first rising edge of the third signal (i.e., t 35 Time of day), triggers the output state to send a change, and outputs a second signal as shown in fig. 10. When the first logic operation unit performs logical AND operation on the PWM signal, the first signal and the second signal, the PWM output signal shown in fig. 10 is output, when the second logic operation unit performs logical AND operation on the first signal and the second signal, the first enabling signal and the second enabling signal shown in fig. 10 are output, and delta t exists between rising edges of the second enabling signal and the first enabling signal 2 Time delay.
In the scheme provided by the embodiment of the application, the first signal is output through the counter, the second signal is output through the edge trigger, the first logic operation unit carries out logic operation on the first signal, the second signal and the input PWM signal to obtain the PWM output signal, and the second logic operation unit carries out logic operation on the first signal and the second signal to obtain the enabling signal, namely in the scheme provided by the embodiment of the application, the enabling signal generating circuit can output the PWM signal and the enabling signal according to one path of PWM signal input, and the problem that the complexity of the system and the application is increased due to the fact that the additional enabling signal is input into the driving system is avoided.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (10)
1. An enable signal generation circuit connected to a driving circuit including a boosting unit and a driving unit connected to the boosting unit, the enable signal generation circuit comprising: a counter, an edge trigger, a first logic operation unit and a second logic operation unit; wherein,,
the counter is used for receiving PWM signals input from the outside, triggering a starting counting or resetting function according to the state of the PWM signals, and outputting a first signal;
the edge trigger is used for receiving the PWM signal and the first signal and triggering and outputting a second signal according to the states of the PWM signal and the first signal;
the first logic operation unit is configured to receive the PWM signal, the first signal, and the second signal, perform logic operation on the PWM signal, the first signal, and the second signal, obtain a PWM output signal, and send the PWM output signal to the driving unit;
the second logic operation unit is configured to receive the first signal and the second signal, perform logic operation on the first signal and the second signal, obtain an enable signal, enable the enable signal to start the boost unit, and drive the driving unit to generate a driving signal according to the PWM output signal.
2. The circuit of claim 1, wherein the enable signal comprises a first enable signal for driving the boost unit to boost the input power signal and a second enable signal for driving the drive unit to generate a drive signal from the PWM signal, wherein a time delay exists between the first enable signal and the second enable signal.
3. The circuit of claim 2, further comprising: a delay unit;
the delay unit is connected with the output end of the second logic operation unit, which outputs the second enabling signal, and is used for delaying the second enabling signal so that delay exists between the first enabling signal and the second enabling signal.
4. The circuit of claim 3, wherein the delay element is a rising edge delay element, the rising edge delay element configured to delay a point in time corresponding to each rising edge in the second enable signal.
5. The circuit of claim 1, wherein the counter triggers a start of a count function at each rising edge of the PWM signal and ends a count when the count value reaches a preset threshold;
the counter triggers the start of a reset function once each time the PWM signal goes low.
6. The circuit of claim 1, wherein the edge trigger comprises a first edge trigger and a second edge trigger coupled to the first edge trigger, wherein,
the first edge trigger is configured to trigger and generate a third signal according to the PWM signal and the state of the first signal, and send the third signal to the second edge trigger;
the second edge trigger is configured to trigger to generate the second signal according to states of the first signal and the third signal.
7. The circuit of claim 6, wherein the first edge flip-flop and the second edge flip-flop are both rising edge flip-flops.
8. The circuit of claim 7, wherein if the first signal is high, the first edge flip-flop toggles the output state once at each rising edge of the PWM signal to obtain the third signal;
and if the first signal is at a low level, the first edge trigger is in a reset state to obtain the third signal, and the third signal is at a low level.
9. The circuit of claim 8, wherein the second edge trigger toggles the output state once at a first rising edge of the third signal to obtain the second signal if the first signal is high;
and if the first signal is at a low level, the second edge trigger is in a reset state to obtain the second signal, and the second signal is at a low level.
10. The circuit of any of claims 1-9, wherein the first logic operation unit and the second logic operation unit are both logical and operation units.
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