CN111063771A - Preparation method of LED chip and LED chip - Google Patents
Preparation method of LED chip and LED chip Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
The invention provides a preparation method of an LED chip and the LED chip. The preparation method of the LED chip provided by the embodiment of the invention comprises the following steps: and after carrying out mesa photoetching, etching the transparent conductive layer by taking the first adhesive layer left by the mesa photoetching as a mask so as to form a gap between the transparent conductive layer and the mesa edge of the epitaxial layer, and removing the first adhesive layer. According to the preparation method of the LED chip provided by the embodiment of the invention, the TCL photoetching and the MESA photoetching in the existing process are combined into one step, so that a photoetching step and photoresist removal are omitted, the capacity of a photoetching workshop and a cleaning workshop is improved, and the manufacturing cost of the LED chip is reduced.
Description
Technical Field
The invention relates to a chip manufacturing technology, in particular to a preparation method of an LED chip and the LED chip.
Background
With the development of Light Emitting Diode (LED) technology, LED chips have been widely used in lighting, indication, display and backlight sources, and the cutting technology of semiconductor wafers has a certain effect on the brightness of the LED chips.
In the prior art, the photolithography process for the forward LED chip includes Current B | ocMng Layer, CBL lithography, Transparent Conductive Layer (TCL) lithography, MESA lithography (MESA lithography), PAD lithography, and protective Layer lithography (PV lithography), and the flip chip process further includes ISO deep etching lithography, DBR lithography, and the like. The MESA lithography is to etch a MESA to expose the N region, and the TCL lithography is to etch back the conductive glass, i.e. Indium Tin Oxide (ITO), to prevent the ITO from contacting with the MESA edge to cause leakage. Specifically, after the MESA lithography in the prior art, the photoresist needs to be removed first, and then, after the photoresist is re-homogenized, the TCL lithography is continued.
Therefore, in the prior art, both the MESA lithography and the TCL lithography are necessary in both the normal chip and the flip chip, but the prior art has complicated process steps, which leads to a technical problem of high manufacturing cost of the LED chip.
Disclosure of Invention
The embodiment of the invention provides a preparation method of an LED chip and the LED chip, which aim to reduce the complexity of process steps and further reduce the manufacturing cost of the LED chip.
In a first aspect, an embodiment of the present invention provides a method for manufacturing an LED chip, including:
after mesa photoetching is carried out, etching the transparent conducting layer by taking the first adhesive layer left by the mesa photoetching as a mask so as to form a gap between the transparent conducting layer and the mesa edge of the epitaxial layer;
and removing the first adhesive layer.
In one possible design, the etching uses wet etching.
In a possible design, the method for manufacturing an LED chip further includes:
and fusing the transparent conducting layer.
In one possible design, after the fusing the transparent conductive layer, the method further includes:
and laminating a silicon dioxide protective layer on the transparent conductive layer.
In one possible design, after the silicon dioxide protective layer is laminated on the transparent conductive layer, the method further includes:
and photoetching is carried out on the silicon dioxide protective layer.
In one possible design, after the performing photolithography on the silicon dioxide protection layer, the method further includes:
and evaporating a metal electrode on the silicon dioxide protective layer.
In one possible design, after the metal electrode is evaporated on the silicon dioxide protective layer, the method further includes:
and carrying out metal fusion on the metal electrode.
In a possible design, before etching the transparent conductive layer by using the remaining first adhesive layer of the mesa lithography as a mask, the method further includes:
the transparent conducting layer is vapor-plated on the epitaxial layer;
and carrying out the mesa photoetching on the transparent conducting layer.
In one possible design, before the evaporation of the transparent conductive layer on the epitaxial layer, the method further includes:
and cleaning the epitaxial layer.
In a second aspect, an embodiment of the present invention further provides an LED chip, where the LED chip is manufactured by using any one of the methods for manufacturing an LED chip according to the first aspect.
According to the preparation method of the LED chip and the LED chip, provided by the embodiment of the invention, after the MESA photoetching is carried out, the transparent conducting layer is etched by taking the first adhesive layer left by the MESA photoetching as a mask, so that a gap is formed between the transparent conducting layer and the MESA edge of the epitaxial layer, and then the first adhesive layer is removed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIGS. 1A-1F are schematic diagrams of chip structures in a method of fabricating an LED chip according to an exemplary embodiment of the present invention;
FIG. 1G is a schematic diagram of an LED chip structure according to an exemplary embodiment of the present invention;
FIG. 2 is a schematic flow diagram illustrating a method of fabricating an LED chip according to an example embodiment of the invention;
FIGS. 3A-3C are schematic diagrams of chip structures in a method of making an LED chip according to another exemplary embodiment of the present invention;
FIG. 3D is a schematic diagram of an LED chip structure according to another exemplary embodiment of the present invention;
FIG. 4 is a schematic diagram of an LED chip structure according to yet another exemplary embodiment of the present invention;
fig. 5 is a schematic diagram of an LED chip structure according to yet another exemplary embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
With the development of Light Emitting Diode (LED) technology, LED chips have been widely used in lighting, indication, display and backlight sources, and the cutting technology of semiconductor wafers has a certain effect on the brightness of the LED chips. In the prior art, the lithography processes of the front-mounted LED chip include CBL lithography, TCL lithography, MESA lithography, PAD lithography, and PV lithography, and the flip-chip process further includes ISO deep etching lithography, DBR lithography, and the like. The MESA lithography is to etch a MESA to expose the N region, and the TCL lithography is to etch back the conductive glass, i.e. Indium Tin Oxide (ITO), to prevent the ITO from contacting with the MESA edge to cause leakage. Specifically, after the MESA lithography in the prior art, the photoresist needs to be removed first, and then, after the photoresist is re-homogenized, the TCL lithography is continued. Therefore, in the prior art, both the MESA lithography and the TCL lithography are necessary in both the normal chip and the flip chip, but the prior art has complicated process steps, which leads to a technical problem of high manufacturing cost of the LED chip. The current LED industry is competitive, and how to save cost and improve product competitiveness on the premise of ensuring chip quality is a problem which needs to be solved urgently.
In view of the above problems, embodiments of the present invention provide a method for manufacturing an LED chip, in which after performing MESA lithography, a transparent conductive layer is etched using a first adhesive layer remaining after the MESA lithography as a mask, so that a gap is formed between the transparent conductive layer and a MESA edge of an epitaxial layer, and then the first adhesive layer is removed.
Fig. 1A to 1F are schematic views of a chip structure in a method for manufacturing an LED chip according to an exemplary embodiment of the present invention. As shown in fig. 1A, in the conventional LED chip manufacturing process, an epitaxial layer 102 is usually disposed on a sapphire layer 101, and then a transparent conductive layer 103 is laminated on the epitaxial layer 102, and mesa lithography is performed, wherein a first glue layer 104 is left after the mesa lithography.
As shown in fig. 1B, in the conventional process for manufacturing an LED chip, the first glue layer 104 needs to be removed. As shown in fig. 1C, after the first glue layer 104 is removed, it is inspected, after passing the inspection, glue needs to be applied again to form a second glue layer 105, and transparent conductive layer lithography is performed.
As shown in fig. 1D, after TCL lithography is performed, TCL development, and inspection after development are performed, and hard baking is performed.
After the hard bake, a TCL etch is performed, as shown in fig. 1E. Fig. 1G is a schematic diagram of an LED chip structure according to an example embodiment of the invention. Referring to fig. 1G, the LED chip in this embodiment retracts the ITO, wherein the retracted ITO width 120 is formed to prevent the ITO from contacting the MESA edge to cause current leakage. And then removing the photoresist after the ITO is retracted, wherein the ITO below the P bonding pad is provided with an opening.
As shown in fig. 1F, after the TCL etch, an inspection is performed and the second glue layer 105 is removed.
Fig. 2 is a schematic flow chart illustrating a method of manufacturing an LED chip according to an example embodiment of the invention. As shown in fig. 2, the method for manufacturing an LED chip provided in this embodiment includes:
s101, carrying out mesa photoetching on the transparent conducting layer.
In this embodiment, the epitaxial layer may be cleaned first, and then the transparent conductive layer may be vapor-deposited on the epitaxial layer. Fig. 3A to 3C are schematic diagrams illustrating a chip structure in a method for manufacturing an LED chip according to another exemplary embodiment of the present invention, and as shown in fig. 3A, after a transparent conductive layer 203 is vapor-deposited on an epitaxial layer 202, mesa lithography is performed on the transparent conductive layer 203, wherein the epitaxial layer 202 is disposed on a sapphire layer 101.
And S102, etching the transparent conductive layer by taking the first adhesive layer left by the mesa photoetching as a mask.
As shown in fig. 3B, after the MESA is etched by photolithography, photoresist is not removed, TCL wet etching is performed using the remaining first adhesive layer 204 as a mask to shrink the ITO inward, so that a gap is formed between the transparent conductive layer and the MESA edge of the epitaxial layer, i.e., leakage caused by contact between the ITO and the MESA edge is prevented, and photoresist is removed after the ITO inward shrinkage is completed.
S103, removing the first glue layer.
As shown in fig. 3C, after etching the transparent conductive layer, the first glue layer 204 is removed, and the ITO under the P pad is remained.
Fig. 3D is a schematic diagram of an LED chip structure according to another exemplary embodiment of the present invention. As shown in FIG. 3D, the ITO is shrunk in this embodiment, wherein the width 220 of the ITO is shrunk in order to prevent the ITO from contacting the MESA edge to cause current leakage.
As can be seen from comparison between fig. 1A to 1G and fig. 3A to 3D, the method for manufacturing an LED chip provided in this embodiment improves the existing LED process, and combines two processes of TCL lithography and MESA lithography into one process. In the preparation method of the LED chip provided in this embodiment, after MESA etching, the photoresist is not removed, and the remaining photoresist is used as a mask to perform TCL wet etching, so as to shrink the ITO inward, thereby preventing the ITO from leaking electricity due to the contact with the MESA edge. After ITO retraction is finished, photoresist is removed, the subsequent process is the same as the prior process, and the ITO below the P bonding pad is reserved. The original process is that photoresist is removed after MESA etching, and TCL photoetching (including steps of photoresist homogenizing, TCL photoetching, TCL developing, hard baking and the like) is carried out. And then TCL etching is carried out, ITO is retracted to prevent the ITO from contacting with the MESA edge to cause electric leakage, the ITO is removed after retraction is finished, and the ITO below the P bonding pad is provided with an opening.
Therefore, the preparation method of the LED chip provided by this embodiment is different from the original process, and the preparation method of the LED chip provided by this embodiment omits one-step photolithography (TCL photolithography), omits one-step photoresist removal, and improves the productivity of the photolithography shop and the cleaning shop.
For a visual description of the differences between the prior art process and the method for manufacturing the LED chip provided in this embodiment, reference may be made to the following table:
in a specific embodiment, taking the CBL-free process as an example, the flow of the current production line process is as follows: cleaning an epitaxial wafer, evaporating an ITO transparent conducting layer, performing MESA photoetching, performing MESA-ITO wet etching, performing ICP etching to expose an N region, performing ICP etching, removing photoresist, performing TCL photoetching, performing TCL etching, performing TCL photoresist removal, performing ITO fusion, depositing a SiO2 protective layer, performing PAD photoetching, performing SiO2 protective layer patterning, performing metal electrode evaporation, performing PAD stripping and photoresist removal, performing PAD alloy, performing data extraction, performing chip grinding, polishing and thinning, performing chip cutting and cracking, performing full-test data, performing Automatic Optical Inspection (AOI) appearance detection, and warehousing.
In the preparation method of the LED chip provided in this embodiment, taking a CBL-free process as an example, an epitaxial wafer is cleaned, an ITO transparent conductive layer is evaporated, MESA lithography is performed, MESA-ITO wet etching is performed, ICP etching is performed to expose an N region, ITO shrink-in etching is performed, photoresist is removed, ITO fusion is performed, a SiO2 protective layer is deposited, PAD lithography is performed, a SiO2 protective layer is patterned, a metal electrode is evaporated, PAD stripping and photoresist removal are performed, PAD alloy is performed, data is sampled, a chip is ground, polished and thinned, a chip is cut and cracked, full-test data is performed, AOI appearance detection is performed, and warehousing is performed.
Therefore, the preparation method of the LED chip provided by the embodiment omits one-step photoetching (TCL photoetching), one-step photoresist removal, and improves the productivity of a photoetching workshop and a cleaning workshop.
In addition, for the CBL process, the production line process and the flow of the LED chip preparation method provided in this embodiment are all only to sequentially add CBL deposition, CBL lithography, CBL etching, and CBL photoresist removal between the epitaxial wafer cleaning and the ITO transparent conductive layer evaporation, and other processes are not changed.
In this embodiment, after the MESA lithography is performed, the transparent conductive layer is etched by using the first adhesive layer remaining in the MESA lithography as a mask, so that a gap is formed between the transparent conductive layer and the MESA edge of the epitaxial layer, and then the first adhesive layer is removed.
In order to further explain the technical effects of the method for manufacturing an LED chip provided in this embodiment, the following comparative experiments may be set up:
first set of comparative experiments: and 4 epitaxial wafers in the same circle with the furnace are selected to be made into the 08K type LED chip. It should be noted that the naming rule for the LED chip is usually named according to the length and width of the LED chip, for example, for a certain chip with a length of 7.9mil and a width of 5.2mil, since 7.9 is close to 8, the 08 number can be used to characterize the length of the LED chip, and therefore, the naming rule can be named as 08K or 08 a, and the specific naming rule of the LED chip is not limited in this embodiment. The epitaxial wafer has to be in the same circle with the furnace, so that the consistency of the photoelectric parameters of the epitaxial wafer is ensured, and the accuracy of the experimental conclusion is ensured. Specifically, 2 epitaxial wafers are processed by the method for manufacturing the LED chip provided in this embodiment (the numbers are EB08K105S69a50 and EB08K105S69a52), while the other 2 epitaxial wafers are processed by the existing process steps (the numbers are EB08K105S69a49 and EB08K105S69a51), and then the Forward Voltage (VF), the brightness (IV), the electrostatic breakdown (ESD) and the Reverse leakage (IR) performances of the two are compared. Specifically, comparative data for the finished core pellets made from both are shown in the following table:
| numbering | Average value of VF | IV mean value | ESD200V yield | IR yield |
| EB08K105S69A49 | 3.46 | 66.6 | 98.0％ | 99.0％ |
| EB08K105S69A51 | 3.43 | 66.7 | 98.1％ | 98.7％ |
| EB08K105S69A50 | 3.40 | 66.8 | 98.1％ | 99.0％ |
| EB08K105S69A52 | 3.38 | 66.9 | 98.1％ | 98.6％ |
Therefore, compared with the 08K type LED chip manufactured by the prior art, the VF mean value of the 08K type LED chip manufactured by the method provided by the embodiment is reduced to be nearly 0.05-0.06V, so that the epitaxial wafer feeding proportion and the chip delivery rate can be improved. In addition, the brightness of the LED chip manufactured by the method provided by the embodiment is higher than that of the LED chip manufactured by the prior art.
For the LED chip manufactured by the method provided by this embodiment, firstly, because the ITO under the P pad is retained, this not only has a smaller influence on the brightness but also can reduce the voltage, and secondly, because the ITO shrinkage of the method provided by this embodiment is smaller than that of the current production line process, this is also beneficial to both the brightness and the voltage.
Specifically, in the method provided in this embodiment, ITO recessing is achieved by undercutting. Referring to fig. 1A and fig. 3A, since both are subjected to mesa lithography, the remaining first glue layer has the same area as ITO, i.e., ITO is completely covered by glue. However, in the method provided by this embodiment, the etching solution can only etch the ITO through the side underetching, the etching rate is slow, and the area of the remaining ITO is larger than that of the existing process, i.e. the effective light-emitting area of the chip is larger than that of the existing process, and the current spreading area is larger than that of the existing process, so that the LED chip manufactured finally has a lower voltage and a higher brightness than the LED chip manufactured by the existing process. Correspondingly, referring to fig. 1D, since the glue area is smaller than the ITO area in this step, the ITO etching solution contacts the front surface of the ITO during ITO etching, the reaction is faster, and in addition to the front surface etching, there is also side underetching. Therefore, the ITO retraction is larger than that in the method provided by the embodiment, and the area of the effective light emitting area of the chip is smaller.
In addition, because the method provided by the embodiment maintains the ITO under the P bonding pad, the P bonding pad is changed from the original main contact with the epitaxial layer to the complete contact with the ITO, the current expansion is better, and the voltage is lower. However, more light is generated under the P pad, and more light is absorbed by the P electrode, and although there is a certain loss of brightness, because the ITO retraction in the method provided by the embodiment is smaller than that in the prior art, the light emitting area of the chip is increased, and the loss is compensated.
With reference to fig. 1G and fig. 3D, the difference between the 08K type LED chip manufactured by the method of this embodiment and the 08K type LED chip manufactured by the prior art in terms of appearance is that there is ITO under the P pad in the method of this embodiment, so there is no inner trace of the opening under the P pad, and there is an inner trace of the opening of the ITO because the ITO has the opening under the P pad in the prior art. In addition, the method provided by the embodiment has narrower ITO retraction, while the ITO retraction in the prior art is wider.
In addition, the ESD yield and the IR yield of the 08K type LED chip manufactured by the method provided in this embodiment are comparable to those of the 08K type LED chip manufactured by the conventional process.
Second set of comparative experiments: and 4 epitaxial wafers in the same circle with the furnace are selected to be made into the LED chip of the 07A type. The epitaxial wafer has to be in the same circle with the furnace, so that the consistency of the photoelectric parameters of the epitaxial wafer is ensured, and the accuracy of the experimental conclusion is ensured. Specifically, 2 epitaxial wafers were processed by the method for manufacturing LED chips provided in this example (nos. EB07a215H09a05 and EB07a215H09a07), while the other 2 epitaxial wafers were processed by the existing process steps (nos. EB07a215H09a04 and EB07a215H09a06), and the comparative data of the finished core particles manufactured by the two are shown in the following table:
| numbering | Average value of VF | IV mean value | ESD200V yield | IR yield |
| EB07A215H09A04 | 3.37 | 62.1 | 98.0％ | 99.0％ |
| EB07A215H09A06 | 3.39 | 61.9 | 98.2％ | 99.0％ |
| EB07A215H09A05 | 3.32 | 62.2 | 98.1％ | 99.0％ |
| EB07A215H09A07 | 3.34 | 62.0 | 98.1％ | 99.0％ |
It can be seen that compared with the 07A type LED chip manufactured by the conventional process, the VF average value of the 07A type LED chip manufactured by the method of this embodiment is reduced by approximately 0.05V, so that the epitaxial wafer feeding ratio and the chip shipment rate can be improved. In addition, the brightness of the LED chip manufactured by the method provided by the embodiment is higher than that of the LED chip manufactured by the prior art.
For the LED chip manufactured by the method provided by this embodiment, firstly, because the ITO under the P pad is retained, this not only has a smaller influence on the brightness but also can reduce the voltage, and secondly, because the ITO shrinkage of the method provided by this embodiment is smaller than that of the current production line process, this is also beneficial to both the brightness and the voltage.
Specifically, in the method provided in this embodiment, ITO recessing is achieved by undercutting. Referring to fig. 1A and fig. 3A, since both are subjected to mesa lithography, the remaining first glue layer has the same area as ITO, i.e., ITO is completely covered by glue. However, in the method provided by this embodiment, the etching solution can only etch the ITO through the side underetching, the etching rate is slow, and the area of the remaining ITO is larger than that of the existing process, i.e. the effective light-emitting area of the chip is larger than that of the existing process, and the current spreading area is larger than that of the existing process, so that the LED chip manufactured finally has a lower voltage and a higher brightness than the LED chip manufactured by the existing process. Correspondingly, referring to fig. 1D, since the glue area is smaller than the ITO area in this step, the ITO etching solution contacts the front surface of the ITO during ITO etching, the reaction is faster, and in addition to the front surface etching, there is also side underetching. Therefore, the ITO retraction is larger than that in the method provided by the embodiment, and the area of the effective light emitting area of the chip is smaller.
In addition, because the method provided by the embodiment maintains the ITO under the P bonding pad, the P bonding pad is changed from the original main contact with the epitaxial layer to the complete contact with the ITO, the current expansion is better, and the voltage is lower. However, more light is generated under the P pad, and more light is absorbed by the P electrode, and although there is a certain loss of brightness, because the ITO retraction in the method provided by the embodiment is smaller than that in the prior art, the light emitting area of the chip is increased, and the loss is compensated.
With continued reference to fig. 1G and fig. 3D, the difference in appearance between the model 07A LED chip manufactured by the method of this embodiment and the model 07A LED chip manufactured by the prior art is that there is ITO under the P pad in the method of this embodiment, so there is no inner trace of the opening under the P pad, and there is an inner trace of the opening of ITO because there is an opening under the P pad in the prior art. In addition, the method provided by the embodiment has narrower ITO retraction, while the ITO retraction in the prior art is wider.
In addition, the model 07A LED chip manufactured by the method of the present embodiment has ESD yield comparable to the model 07A LED chip manufactured by the conventional process and IR yield comparable to the model 07A LED chip manufactured by the conventional process.
Third set of comparative experiments: and 6 epitaxial wafers in the same circle with the furnace are selected to be made into the 22S type LED chip. The epitaxial wafer has to be in the same circle with the furnace, so that the consistency of the photoelectric parameters of the epitaxial wafer is ensured, and the accuracy of the experimental conclusion is ensured. Specifically, 3 epitaxial wafers were processed by the method for manufacturing LED chips provided in this embodiment (numbered FC22S774G01E13, FC22S774G01E15, and FC22S774G01E17), and the other 3 epitaxial wafers were processed by the existing process steps (numbered FC22S774G01E12, FC22S774G01E14, and FC22S774G01E16), and the comparison data of the finished core particles manufactured by the two are shown in the following table:
it can be seen that compared with the 22S type LED chip manufactured by the conventional process, the 22S type LED chip manufactured by the method of the present embodiment has a VF average value reduced by approximately 0.03V, so that the epitaxial wafer feeding ratio and the chip shipment rate can be improved. In addition, the brightness of the LED chip manufactured by the method provided by the embodiment is higher than that of the LED chip manufactured by the prior art.
For the LED chip manufactured by the method provided by this embodiment, firstly, because the ITO under the P pad is retained, this not only has a smaller influence on the brightness but also can reduce the voltage, and secondly, because the ITO shrink-in of the method provided by this embodiment is smaller than that of the current production line process, this is beneficial to both the brightness and the voltage.
Specifically, in the method provided in this embodiment, ITO recessing is achieved by undercutting. Referring to fig. 1A and fig. 3A, since both are subjected to mesa lithography, the remaining first glue layer has the same area as ITO, i.e., ITO is completely covered by glue. However, in the method provided by this embodiment, the etching solution can only etch the ITO through the side underetching, the etching rate is slow, and the area of the remaining ITO is larger than that of the existing process, i.e. the effective light-emitting area of the chip is larger than that of the existing process, and the current spreading area is larger than that of the existing process, so that the LED chip manufactured finally has a lower voltage and a higher brightness than the LED chip manufactured by the existing process. Correspondingly, referring to fig. 1D, since the glue area is smaller than the ITO area in this step, the ITO etching solution contacts the front surface of the ITO during ITO etching, the reaction is faster, and in addition to the front surface etching, there is also side underetching. Therefore, the ITO retraction is larger than that in the method provided by the embodiment, and the area of the effective light emitting area of the chip is smaller.
In addition, because the method provided by the embodiment maintains the ITO under the P bonding pad, the P bonding pad is changed from the original main contact with the epitaxial layer to the complete contact with the ITO, the current expansion is better, and the voltage is lower. However, more light is generated under the P pad, and more light is absorbed by the P electrode, and although there is a certain loss of brightness, because the ITO retraction in the method provided by the embodiment is smaller than that in the prior art, the light emitting area of the chip is increased, and the loss is compensated.
With reference to fig. 1G and fig. 3D, the difference between the 22S type LED chip manufactured by the method of this embodiment and the 22S type LED chip manufactured by the prior art in terms of appearance is that there is ITO under the P pad in the method of this embodiment, so there is no inner trace of the opening under the P pad, and there is an inner trace of the opening of ITO because there is an opening under the P pad in the prior art. In addition, the method provided by the embodiment has narrower ITO retraction, while the ITO retraction in the prior art is wider.
In addition, the ESD yield and the IR yield of the 22S type LED chip manufactured by the method provided in this embodiment are comparable to those of the 22S type LED chip manufactured by the conventional process.
It is worth to be noted that, the LED chips in the first group of comparison experiments, the second group of comparison experiments, and the third group of comparison experiments are not provided with CBLs, and in the fourth group of comparison experiments, the LED chips provided with CBLs can be used for comparison, and 6 epitaxial wafers in the same furnace and the same ring are selected to be made into 18V-type LED chips. The epitaxial wafer has to be in the same circle with the furnace, so that the consistency of the photoelectric parameters of the epitaxial wafer is ensured, and the accuracy of the experimental conclusion is ensured. Specifically, 3 epitaxial wafers were processed by the method for manufacturing LED chips provided in this embodiment (nos. TL18V412J14P31, TL18V412J14P33, and TL18V412J14P35), while the other 3 epitaxial wafers were processed by the existing process steps (nos. TL18V412J14P30, TL18V412J14P32, and TL18V412J14P34), and the comparative data of the finished core particles manufactured by the two wafers are shown in the following table:
| numbering | Average value of VF | IV mean value | ESD200V yield | IR yield |
| TL18V412J14P30 | 3.04 | 93.7 | 98.6％ | 99.2％ |
| TL18V412J14P32 | 3.03 | 93.6 | 98.7％ | 99.0％ |
| TL18V412J14P34 | 3.05 | 93.8 | 98.4％ | 99.4％ |
| Average data | 3.04 | 93.7 | 98.6％ | 99.2％ |
| TL18V412J14P31 | 3.02 | 93.9 | 98.7％ | 99.4％ |
| TL18V412J14P33 | 3.01 | 94.0 | 98.5％ | 99.1％ |
| TL18V412J14P35 | 3.03 | 93.9 | 98.4％ | 99.3％ |
| Average data | 3.02 | 93.9 | 98.5％ | 99.3％ |
As can be seen, compared with the 18V-type LED chip manufactured by the existing process, the 18V-type LED chip manufactured by the method provided by this embodiment is of a medium-sized or large-sized type, and its VF average value is reduced by approximately 0.02V, so that the epitaxial wafer feeding ratio and the chip shipment rate can be improved. In addition, the brightness of the LED chip manufactured by the method provided by the embodiment is higher than that of the LED chip manufactured by the prior art.
Fig. 4 is a schematic diagram of an LED chip structure according to yet another exemplary embodiment of the present invention. As shown in fig. 4, in the 18V LED chip manufactured by the prior art, both the CBL106 and the transparent conductive layer 103 under the P-pad 107 have openings. Fig. 5 is a schematic diagram of an LED chip structure according to yet another exemplary embodiment of the present invention. As shown in fig. 5, in the 18V LED chip manufactured by the method provided in this embodiment, neither the CBL206 nor the transparent conductive layer 203 under the P pad 207 has an opening.
It should be noted that the first, second, third and fourth comparative experiments are few experiments, and the fifth comparative experiment increases the number of the test pieces based on the previous experiment, and makes repeated verification, and the test pieces are related to the model without CBL and the model with CBL.
And selecting 12 epitaxial wafers which are in the same circle with the furnace to manufacture a 08K type chip (with or without CB). The epitaxial wafer has to be in the same circle with the furnace, so that the consistency of the photoelectric parameters of the epitaxial wafer is ensured, and the accuracy of the experimental conclusion is ensured. Specifically, 6 epitaxial wafers were processed by the method for manufacturing LED chips provided in this example (nos. FB08K215L50C08, FB08K215L50C10, FB08K215L50C12, FB08K215L50C16, FB08K215L50C18, and FB08K215L50C20), while the other 6 wafers were processed by the existing process steps (nos. FB08K215L50C07, FB08K215L50C09, FB08K215L50C11, FB08K215L50C15, FB08K215L50C17, and FB08K215L50C19), and the comparison data of the finished core particles manufactured by the two wafers are shown in the following table:
| numbering | Average value of VF | IV mean value | ESD200V yield | IR yield |
| FB08K215L50C07 | 3.42 | 66.3 | 99.4％ | 98.9％ |
| FB08K215L50C09 | 3.39 | 66.3 | 99.3％ | 98.8％ |
| FB08K215L50C11 | 3.40 | 66.2 | 99.4％ | 99.0％ |
| FB08K215L50C15 | 3.42 | 66.4 | 99.2％ | 98.9％ |
| FB08K215L50C17 | 3.42 | 66.2 | 99.2％ | 99.0％ |
| FB08K215L50C19 | 3.40 | 66.1 | 99.5％ | 98.8％ |
| Average data | 3.41 | 66.3 | 99.3％ | 98.9％ |
| FB08K215L50C08 | 3.35 | 66.7 | 99.3％ | 99.2％ |
| FB08K215L50C10 | 3.35 | 66.6 | 99.2％ | 98.8％ |
| FB08K215L50C12 | 3.37 | 66.5 | 99.6％ | 99.0％ |
| FB08K215L50C16 | 3.36 | 66.5 | 99.4％ | 98.8％ |
| FB08K215L50C18 | 3.36 | 66.6 | 99.1％ | 99.1％ |
| FB08K215L50C20 | 3.37 | 66.7 | 99.2％ | 98.8％ |
| Average data | 3.36 | 66.6 | 99.3％ | 99.0％ |
And selecting 12 epitaxial wafers which are in the same circle with the furnace to manufacture the 18V type chip (with CB). The epitaxial wafer has to be in the same circle with the furnace, so that the consistency of the photoelectric parameters of the epitaxial wafer is ensured, and the accuracy of the experimental conclusion is ensured. Specifically, 6 epitaxial wafers were processed by the method for manufacturing LED chips provided in this example (nos. CL18V548K21P17, CL18V548K21P19, CL18V548K21P21, CL18V548K21P24, CL18V548K21P27 and CL18V548K21P30), while the other 6 epitaxial wafers were processed by the existing process steps (nos. CL18V548K21P16, CL18V548K21P18, CL18V548K21P20, CL18V548K21P23, CL18V548K21P25 and CL18V548K21P28), and the comparative data of the finished core particles manufactured by the two epitaxial wafers are shown in the following table:
| numbering | Average value of VF | IV mean value | ESD200V yield | IR yield |
| CL18V548K21P16 | 3.08 | 93.9 | 98.7％ | 99.4％ |
| CL18V548K21P18 | 3.06 | 93.7 | 98.7％ | 99.2％ |
| CL18V548K21P20 | 3.09 | 94.0 | 98.4％ | 99.2％ |
| CL18V548K21P23 | 3.07 | 93.8 | 98.6％ | 99.4％ |
| CL18V548K21P25 | 3.08 | 93.7 | 98.4％ | 99.2％ |
| CL18V548K21P28 | 3.07 | 93.9 | 98.5％ | 99.3％ |
| Average data | 3.08 | 93.8 | 98.6％ | 99.3％ |
| CL18V548K21P17 | 3.06 | 94.0 | 98.6％ | 99.2％ |
| CL18V548K21P19 | 3.05 | 94.1 | 98.6％ | 99.3％ |
| CL18V548K21P21 | 3.04 | 94.3 | 98.5％ | 99.1％ |
| CL18V548K21P24 | 3.05 | 94.2 | 98.4％ | 99.4％ |
| CL18V548K21P27 | 3.06 | 94.1 | 98.7％ | 99.2％ |
| CL18V548K21P30 | 3.04 | 94.1 | 98.5％ | 99.1％ |
| Average data | 3.05 | 94.1 | 98.6％ | 99.2％ |
As can be seen from the above data, after the chip size is increased, the comparative data of the chip with the 08K model (without CBL) and the chip with the 18V model (with CBL) processed by the preparation method of the LED chip provided in this embodiment and the processing performed by the existing process is the same as the conclusion of the few-chip experiment, and is not repeated here.
The five groups of comparative experiments show that: compared with the prior art, the preparation method of the LED chip provided by the embodiment combines the TCL photoetching and the MESA photoetching into one step, so that the productivity of a yellow light workshop and a cleaning workshop is improved. Through verification, compared with the LED chip manufactured by the existing process, the LED chip manufactured by the LED chip manufacturing method provided by the embodiment has the advantages of unchanged performance and reliability, slightly superior brightness and voltage, and capability of improving the epitaxial wafer feeding proportion and the chip shipment proportion.
In addition, the invention also provides an LED chip which is prepared by adopting the preparation method provided by any embodiment.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A preparation method of an LED chip is characterized by comprising the following steps:
after mesa photoetching is carried out, etching the transparent conducting layer by taking the first adhesive layer left by the mesa photoetching as a mask so as to form a gap between the transparent conducting layer and the mesa edge of the epitaxial layer;
and removing the first adhesive layer.
2. The method for manufacturing an LED chip according to claim 1, wherein the etching is wet etching.
3. The method for preparing an LED chip according to claim 1 or 2, further comprising, after the removing the first adhesive layer:
and fusing the transparent conducting layer.
4. The method for preparing an LED chip according to claim 3, further comprising, after the fusing the transparent conductive layer:
and laminating a silicon dioxide protective layer on the transparent conductive layer.
5. The method for manufacturing an LED chip according to claim 4, further comprising, after the silica protective layer is laminated on the transparent conductive layer:
and photoetching is carried out on the silicon dioxide protective layer.
6. The method for manufacturing an LED chip according to claim 5, further comprising, after the step of performing photolithography on the silicon dioxide protective layer:
and evaporating a metal electrode on the silicon dioxide protective layer.
7. The method for manufacturing an LED chip according to claim 6, further comprising, after the metal electrode is evaporated on the silicon dioxide protective layer:
and carrying out metal fusion on the metal electrode.
8. The method for manufacturing an LED chip according to claim 3, wherein before etching the transparent conductive layer by using the remaining first adhesive layer of the mesa lithography as a mask, the method further comprises:
the transparent conducting layer is vapor-plated on the epitaxial layer;
and carrying out the mesa photoetching on the transparent conducting layer.
9. The method for manufacturing an LED chip according to claim 8, further comprising, before evaporating the transparent conductive layer on the epitaxial layer:
and cleaning the epitaxial layer.
10. An LED chip, wherein the LED chip is manufactured by the method of any one of claims 1 to 9.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2003533030A (en) * | 2000-04-26 | 2003-11-05 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Manufacturing method of light emitting diode chip and light emitting diode structure element based on GaN |
| CN102244160A (en) * | 2011-06-30 | 2011-11-16 | 晶能光电（江西）有限公司 | LED preparation method for improving light-emitting efficiency |
| CN102812566A (en) * | 2010-03-23 | 2012-12-05 | 丰田合成株式会社 | Semiconductor light-emitting element manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003533030A (en) * | 2000-04-26 | 2003-11-05 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Manufacturing method of light emitting diode chip and light emitting diode structure element based on GaN |
| CN102812566A (en) * | 2010-03-23 | 2012-12-05 | 丰田合成株式会社 | Semiconductor light-emitting element manufacturing method |
| CN102244160A (en) * | 2011-06-30 | 2011-11-16 | 晶能光电（江西）有限公司 | LED preparation method for improving light-emitting efficiency |
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