CN111061674B - Multiprocessor cross communication device and method - Google Patents
Multiprocessor cross communication device and method Download PDFInfo
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Abstract
The disclosure provides a multiprocessor cross communication device and a method, and belongs to the technical field of communication. The device comprises: a switch controller, a memory, and a plurality of interface controllers, the number of the interface controllers being the same as the number of processors, the ith interface controller being matched with a communication data interface of the ith processor, the switch controller being configured to determine a sender processor of the kth communication from among candidate sender processors of the kth communication, send an permission notification to the sender processor of the kth communication, the permission notification being configured to instruct the sender processor of the kth communication to send the kth data to the corresponding interface controller, the receiver processor being any one of the processors except the sender processor; the exchange controller is further configured to send the kth data stored in the memory to the receiver processor through an interface controller corresponding to the receiver processor of the kth data.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a multiprocessor cross communication device and method.
Background
Processors are the basis of modern computing devices, providing the basic computing power for modern computing devices. In order to meet the requirements of computing facilities on special use scenarios such as computing performance, universality, communication capability, power consumption and the like, processors of various special type architectures such as DSP (Digital Signal Processor ), CPU (Central Processing Unit, central processing unit), ARM (Advanced RISC (Reduced Instruction Set Computing, reduced instruction set computer) Machines, advanced RISC processor), MCU (Microcontroller Unit, micro control unit) and the like have evolved.
Modern computing devices often have complex structures and functions, and single processors cannot meet the function design index, and multiple processors are required to be combined and matched to complete functions together. When the multiple processors are in cross communication, the common design often uses a bus communication technology, so that the rapid interaction of large-batch data among the multiple processors can be realized. However, the software and hardware design of the bus communication technology is complex, the technical requirement is high, and for small batch data interaction among multiple processors, if the bus communication is adopted, the problems of low bus utilization rate, resource waste and the like exist.
Disclosure of Invention
The embodiment of the disclosure provides a multiprocessor cross communication device and a multiprocessor cross communication method, which can ensure that data transmission can be carried out between two processors at the same time, and meet the multiprocessor application scene of small batch data interaction. The technical scheme is as follows:
in one aspect, a multi-processor cross communication apparatus is provided, the multi-processor cross communication apparatus comprising:
the controller is exchanged with the controller to control the switching of the switching devices,
the memory device is used for storing the data,
a plurality of interface controllers, the number of the interface controllers is the same as the number of the processors, the ith interface controller is matched with the communication data interface of the ith processor,
the exchange controller is used for determining a candidate sender processor of the kth communication, determining a sender processor of the kth communication from the candidate sender processors of the kth communication, and sending an allowance notification to the sender processor of the kth communication, wherein the allowance notification is used for instructing the sender processor of the kth communication to send the kth data to the corresponding interface controller, the receiver processor of the kth data is any processor except the sender processor, and i and k are positive integers;
the memory is used for storing kth data received from the corresponding interface controller;
the exchange controller is further configured to send the kth data stored in the memory to the receiver processor through an interface controller corresponding to the receiver processor of the kth data.
Optionally, the switching controller is further configured to,
receiving a communication ending application sent by a sender processor of the kth communication, and removing the processor sending the communication ending application from the candidate sender processors, wherein the communication ending application is sent by the sender processor of the kth communication after sending data;
and after the candidate sender processor of the kth communication is determined, receiving a communication application sent by the processor, and taking the processor sending the communication application as the candidate sender processor.
Optionally, the switching controller is further configured to,
when a communication end application transmitted by the sender processor of the kth communication is received and there is no data in the memory, determining a candidate sender processor of the kth +1 communication,
when the candidate sender processor for the k+1th communication includes at least one processor, determining a sender processor for the k+1th communication from among the candidate sender processors for the k+1th communication,
when the number of at least one of the processors in the k+1th communication candidate sender processor is greater than the number of the k communication sender processor, the k+1th communication sender processor is the first processor sequentially arranged after the k communication sender processor,
when the number of each processor in the k+1th communication candidate sender processor is smaller than the number of the k communication sender processor, the number of the k+1th communication sender processor is the smallest number in the numbers of the processors.
Optionally, the switching controller is further configured to,
and after the candidate sender processor of the kth communication is determined, receiving a communication revocation application sent by the processor, and removing the processor sending the communication revocation application from the candidate sender processor, wherein the communication revocation application is sent by the corresponding processor after the communication application is sent.
Optionally, the kth data includes a source address field, a destination address field, and a valid data field,
the source address field includes the number of the sender processor of the kth communication,
the destination address field includes the number of the recipient processor of the kth data,
the valid data field includes the kth data.
In another aspect, there is provided a multiprocessor cross communication method including:
a candidate sender processor for the kth communication is determined,
determining a sender processor of a kth communication from the candidate sender processors of the kth communication,
transmitting an permission notification to a sender processor of the kth communication, the permission notification being for instructing the sender processor of the kth communication to send kth data to a corresponding interface controller, a receiver processor of the kth data being any one processor other than the sender processor, the number of the interface controllers being the same as the number of the processors, an ith one of the interface controllers being matched with a communication data interface of the ith one of the processors,
and sending the kth data to the receiver processor through an interface controller corresponding to the receiver processor of the kth data.
Optionally, the method further comprises:
receiving a communication ending application sent by a sender processor of the kth communication, and removing the processor sending the communication ending application from the candidate sender processors, wherein the communication ending application is sent by the sender processor of the kth communication after sending data;
and after the candidate sender processor of the kth communication is determined, receiving a communication application sent by the processor, and taking the processor sending the communication application as the candidate sender processor.
Optionally, the method further comprises:
when a communication end application transmitted by the sender processor of the kth communication is received and there is no data in the memory, determining a candidate sender processor of the kth +1 communication,
when the candidate sender processor for the k+1th communication includes at least one processor, determining a sender processor for the k+1th communication from among the candidate sender processors for the k+1th communication,
when the number of at least one of the processors in the k+1th communication candidate sender processor is greater than the number of the k communication sender processor, the k+1th communication sender processor is the first processor sequentially arranged after the k communication sender processor,
when the number of each processor in the k+1th communication candidate sender processor is smaller than the number of the k communication sender processor, the number of the k+1th communication sender processor is the smallest number in the numbers of the processors.
Optionally, after the determining the candidate sender processor for the kth communication, the method further comprises:
and receiving a communication revocation application sent by the processor, and removing the processor sending the communication revocation application from the candidate sender processor, wherein the communication revocation application is sent by the corresponding processor after the communication application is sent.
Optionally, the kth data includes a source address field, a destination address field, and a valid data field,
the source address field includes the number of the sender processor of the kth communication,
the destination address field includes the number of the recipient processor of the kth data,
the valid data field includes the kth data.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that:
by matching the ith interface controller with the communication data interface of the ith processor, a single processor can only provide one idle communication data interface to realize the cross communication of multiple processors; the method comprises the steps of determining a candidate sender processor of the kth communication, determining the sender processor of the kth communication from the candidate sender processors of the kth communication, sending an permission notice to the sender processor of the kth communication, and allowing the sender processor for instructing the kth communication to send the kth data to a corresponding interface controller, storing the kth data in a memory, and then sending the kth data stored in the memory to a receiver processor through the interface controller corresponding to the receiver processor of the kth data.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIGS. 1 and 2 are block diagrams of a multiprocessor cross communication apparatus provided by an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of the format of data provided by an embodiment of the present disclosure;
fig. 4 and 5 are flowcharts of a multiprocessor cross communication method provided by an embodiment of the present disclosure.
Detailed Description
For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.
In the present disclosure, the processor includes processors of various special-purpose type architectures such as DSP (Digital Signal Processor ), CPU (Central Processing Unit, central processing unit), ARM (Advanced RISC (Reduced Instruction Set Computing, reduced instruction set computer) Machines, advanced RISC processor), MCU (Microcontroller Unit, micro control unit), and the like. The processors, although of different architectures, each have a dedicated communication interface, such as UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter), I2C (Inter-Integrated Circuit, integrated circuit), SPI (Serial Peripheral Interface ), and the like. However, the number of communication interfaces of a single processor is limited, and one communication interface only supports communication with one processor, so that if a single processor is connected to each processor in turn, the number of communication interfaces is limited, and difficulty exists in actual implementation.
Considering that the dedicated communication interfaces can be divided into communication control interfaces such as I/O (input/output) interfaces and communication data interfaces such as UART, I2C, SPI, and that the processor is generally provided with general-purpose communication interfaces such as I/O interfaces, UART, I2C, SPI, etc., there are often unused interfaces except for some of the interfaces that are used in the hardware design itself. The method and the device can select unused universal communication interface resources in principle of not influencing the original hardware design, and realize cross communication among multiple CPUs. The method only needs to use one communication data interface (such as UART, I2C or SPI) and one communication control interface (such as I/O interface) for each CPU, and the types of the communication data interfaces are transparent to other CPUs.
Fig. 1 and 2 are block diagrams of a multiprocessor cross communication apparatus according to an embodiment of the present disclosure. In a hardware implementation, the multi-processor cross communication device may employ an FPGA (Field Programmable Gate Array ). Referring to fig. 1 and 2, the multiprocessor cross communication apparatus 100 includes a switching controller 11, a memory 12, and a plurality of interface controllers 13. Wherein the number of interface controllers 13 is the same as the number of processors (processors to be cross-communicated) (assuming n), the ith interface controller 13 is matched with the communication data interface of the ith processor. i is a positive integer.
The switching controller 11 is configured to determine a candidate sender processor for the kth communication, determine a sender processor for the kth communication from among the candidate sender processors for the kth communication, and send an permission notification to the sender processor for the kth communication, the permission notification being for instructing the sender processor for the kth communication to send the kth data to the corresponding interface controller 13, the receiver processor being any one of the processors other than the sender processor. k is a positive integer.
The memory 12 is used for storing kth data received from the corresponding interface controller 13.
The switch controller 11 is further configured to send the kth data stored in the memory 12 to the receiver processor through the interface controller 13 corresponding to the receiver processor of the kth data.
Wherein the switching controller has a number of communication control interfaces (which may be I/O interfaces) equal to the number of processors to be cross-communicated. The ith communication control interface of the switching controller is electrically connected with the communication control interface of the ith processor.
Illustratively, the switch controller 11 transmits the permission notification to the communication control interface of the sender processor of the kth communication through the communication control interface of the present switch controller.
In the embodiment of the disclosure, by matching the ith interface controller 13 with the communication data interface of the ith processor, a single processor can provide only one idle communication data interface to realize cross communication of multiple processors; the method comprises the steps of determining a candidate sender processor of the kth communication, determining the sender processor of the kth communication from the candidate sender processors of the kth communication, sending an permission notice to the sender processor of the kth communication, allowing the sender processor for instructing the kth communication to send the kth data to a corresponding interface controller 13, storing the kth data in a memory 12, and then sending the kth data stored in the memory 12 to a receiver processor through the interface controller 13 corresponding to the receiver processor of the kth data, wherein the interface controllers 13 are cross-connected through the same memory 12, so that data transmission between the two interface controllers 13 can be ensured at the same time, and a multiprocessor application scene of small-batch data interaction can be met.
The types (such as UART, I2C or SPI) of the plurality of interface controllers 13 may be the same or different depending on the CPU application.
The candidate sender processor may be updated continuously over time. The update for the candidate sender processor may include the following three ways.
In the first aspect, the switching controller 11 is further configured to receive a communication end application transmitted from a sender processor of the kth communication, and remove a processor that transmits the communication end application from the candidate sender processors, where the communication end application is transmitted after the sender processor of the kth communication has transmitted the data.
In the second mode, the switching controller 11 is further configured to, after determining the candidate sender processor for the kth communication, receive the communication application transmitted by the processor, and use the processor for transmitting the communication application as the candidate sender processor.
For example, when CPU a transmits data to CPU B, a communication request is first transmitted to the switching controller 11 through the communication control interface, and the line usage right is applied.
In a third mode, the switching controller 11 is further configured to, after determining the candidate sender processor of the kth communication, receive a communication revocation application sent by the processor, and remove the processor that sends the communication revocation application from the candidate sender processors, where the communication revocation application is sent by the corresponding processor after sending the communication application.
Since transmission of data between two of the interface controllers 13 is supported at the same time, in order to secure balance of resources, in the present disclosure, a polling manner is used to allocate communication rights.
Illustratively, the switch controller 11 is also configured to,
when a communication end application transmitted by the sender processor of the kth communication is received and there is no data in the memory 12, the candidate sender processor of the kth+1th communication is determined.
When the candidate sender processor of the k+1th communication includes at least one processor, the sender processor of the k+1th communication is determined from among the candidate sender processors of the k+1th communication.
When the number of at least one processor of the candidate sender processors of the kth communication is greater than the number of the sender processor of the kth communication, the sender processor of the kth+1 communication is determined to be the first processor sequentially arranged after the sender processor of the kth communication.
When the number of each processor in the k+1th communication candidate sender processor is smaller than the number of the k communication sender processor, determining the number of the k+1th communication sender processor as the minimum number in the numbers of each processor.
Illustratively, the exchange controller 11 is further configured to send a receiving notification to the receiver processor of the kth data through the communication control interface to instruct the receiver processor of the kth data to receive the data, and send the kth data stored in the memory 12 to the receiver processor through the interface controller 13 corresponding to the receiver processor of the kth data.
In a specific implementation, the communication control interface between the switch controller 11 and each processor is electrically connected by a data line, which carries an "instruction channel", and different level values may be used to indicate instructions (e.g. a communication application/a communication revocation application/a communication end application/a permission notification/a prohibition notification/a reception notification) between the switch controller 11 and each processor, respectively. Accordingly, a "data channel" is formed between the interface controller 13 and the communication data interface of the corresponding processor for transmitting data.
Since the transmission of data between two of the interface controllers 13 is supported at the same time, in order to ensure balance of resources, in the present disclosure, the data of each communication interaction is transmitted in a fixed format, ensuring that the data length of each communication interaction is the same.
Fig. 3 is a schematic diagram of a format of data provided by an embodiment of the present disclosure. Referring to fig. 3, illustratively, the kth data includes a source address field, a destination address field, and a valid data field.
The source address field includes the number of the sender processor of the kth communication.
The destination address field includes the number of the recipient processor of the kth data.
The valid data field includes the kth time data.
Illustratively, the kth data may further include a length field for indicating the length of the valid data.
Fig. 4 is a flowchart of a method of multi-processor cross communication provided by an embodiment of the present disclosure, the method flow being performed by a multi-processor cross communication device. Referring to fig. 4, the multiprocessor cross communication method flow includes the following steps.
Wherein the notification is allowed to instruct the sender processor for the kth communication to send the kth data to the corresponding interface controller, the receiver processor is any one of the processors except the sender processor, the number of the interface controllers is the same as the number of the processors, and the ith interface controller is matched with the communication data interface of the ith processor.
And step 304, the kth data is sent to the receiver processor through the interface controller corresponding to the receiver processor of the kth data.
Illustratively, step 303 may further comprise: and sending a prohibition notification to other processors except the sender processor of the kth communication in the candidate sender processors of the kth communication to instruct the other processors to continue waiting. After receiving the prohibition notification, the other processor may send a communication revocation application to the switch controller of the multiprocessor cross communication device.
Fig. 5 is a flowchart of a multiprocessor cross communication method provided by an embodiment of the present disclosure. Referring to fig. 5, the method flow may also include the following steps, for example.
In the embodiment of the disclosure, the next communication is triggered by the sender of the last communication sending a communication end application. Based on this, after step 305, the method may further comprise the following steps.
When the candidate sender processor of the k+1th communication includes at least one processor, the sender processor of the k+1th communication is determined from among the candidate sender processors of the k+1th communication.
When the number of at least one processor of the candidate sender processors of the kth communication is greater than the number of the sender processor of the kth communication, the sender processor of the kth+1 communication is the first processor sequentially arranged after the sender processor of the kth communication.
When the number of each processor in the k+1th communication candidate sender processor is smaller than the number of the k communication sender processor, the number of the k+1th communication sender processor is the smallest number in the numbers of each processor.
The specific process of the kth+1th communication may refer to the process of the kth communication (refer to steps 302 to 304), which will not be described herein.
Referring to fig. 3, the kth data includes a source address field, a destination address field, and a valid data field.
The source address field (Destination ADDR) includes the number of the sender processor of the kth communication.
The destination address field (Source ADDR) includes the number of the recipient processor of the kth data.
The valid data field (Payload) includes the kth data.
The multi-processor cross communication device can be applied to cross communication of multiple CPUs between circuit board stages. The multiprocessor cross communication device is assumed to be realized by an FPGA, and the FPGA comprises three parts, namely an interface controller such as UART, I2C, SPI and the like, a switching controller and a data buffer register (memory). The FPGA and the processors to be cross-communicated form a cross-communication system in which all universal interface controllers are assigned a device address which can correspond to the address of the communication data interface of the respective processor, for example from 1 to n. Taking cross communication of multiple CPUs between circuit boards as an example, a method flow comprising the following steps (1) - (9) will be described in detail with reference to fig. 2.
(1) When the CPU A to the CPU B need to communicate, the CPU A groups the data communication frames, and simultaneously sends a communication application to the exchange controller through the communication control interface to apply for the use right of the data channel.
As shown in fig. 3, the transmitted data communication frame format is: the source address is the address of the FPGA interface controller (assumed to be a serial port controller) which is in butt joint with the CPU A, the destination address is the address of the FPGA interface controller (assumed to be an I2C controller) which is in butt joint with the CPU B of the destination processor, and the length of the data segment of the data frame.
The switch controller adds CPU a to the candidate sender processor, which means that the processor is queuing to acquire data channel usage rights.
(2) When the data channel is idle (no processor sends data), the exchange controller arbitrates all the communication applications in the current queuing in a mode of 1-n polling, and the polling initial sequence number is the number of the communication initiating device which completes the communication last time plus 1.
(3) When the polling is not circulated to the CPU A, the sending function of the CPU A is blocked and is not available, and only the receiving function is provided at the moment, so that the data sent by the interface controller of the FPGA can be received.
It should be noted that, during this period, the CPU a may discard the application for the data channel, for example, send the channel revocation application. If so, the poll will skip CPU A.
(4) When the exchange controller arbitrates the data channel to the CPU A, the exchange controller sends an permission notice to the CPU A through the control interface to inform the CPU A of obtaining the use right of the data channel, at the moment, the CPU A has a sending function, and the sending functions of other CPUs are blocked.
(5) After the CPU a obtains the right to use the data channel, it may use the data channel to send no more than one frame of data, and then release the data channel (send a communication end application to the exchange controller) to notify the exchange controller that the use of the data channel is completed.
(6) After the exchange controller finds that the CPU A releases the data channel, checking whether a data frame needs to be processed in the data buffer memory, and if no data needs to be processed, starting a new round of data channel arbitration; if the data frame needs to be processed, starting a new round of data channel arbitration after the data frame is processed.
(7) When the data buffer memory has data frames to be processed, the exchange controller sends a notification signal (a receiving notification) to a CPU (Central processing Unit) in butt joint with the corresponding FPGA interface controller according to the destination address in the data frames, and simultaneously starts the corresponding FPGA interface controller.
(8) After receiving the notification signal, the CPU B starts to read the data frame from the corresponding FPGA interface controller.
(9) When the FPGA finishes transmitting all the data frames in the data buffer memory, the data channel is in an idle state, and the communication exchange controller starts a new round of arbitration at the moment, so that the cycle is circulated.
In the whole communication process, the data channel usage rights are divided according to time slots, and a single CPU only uses a single time slot at a time, so that one data frame can be sent to other CPUs. The data channel usage right rotates rapidly among all CPUs with usage demands, and from the whole, all CPUs can send data to any other CPUs at any moment by using a single communication controller, so that the process of cross communication among multiple CPUs by using a single universal communication interface controller is realized.
In this disclosure, it is an object to achieve cross communication between multiple CPUs at a circuit board level with limited number and types of communication data interfaces. When the CPU A sends data to the CPU B, the line use right is firstly applied to the exchange controller. After inquiring that the communication line is idle, the switching controller implemented on the FPGA distributes the line use right to the CPU A, and simultaneously informs the CPU A that the line can be used. The FPGA receives the data frame using the data interface in communication with CPU a, notifies CPU B of the readiness to receive data based on the destination address of the data frame, and then transmits the buffered data frame to CPU B using the communication data interface with CPU B. When a plurality of CPUs apply for a line at the same time, the switching controller distributes the use right to one CPU. The CPU which does not receive the authorization, the sending function is blocked, and only the receiving function is provided until the CPU is authorized. In this way, cross communication among multiple CPUs at the circuit board level is realized under the condition of limited number and types of communication data interfaces
It should be noted that: the multiprocessor cross communication device provided in the above embodiment only uses the division of the above functional modules to illustrate when triggering the multiprocessor cross communication service, and in practical application, the above functional allocation may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the multiprocessor cross communication device provided in the above embodiment and the multiprocessor cross communication method embodiment belong to the same concept, and specific implementation processes thereof are detailed in the method embodiment, which is not described herein again.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The foregoing description of the preferred embodiments of the present disclosure is not intended to limit the disclosure, but rather to enable any modification, equivalent replacement, improvement or the like, which fall within the spirit and principles of the present disclosure.
Claims (10)
1. A multi-processor cross communication device, the multi-processor cross communication device comprising:
the controller is exchanged with the controller to control the switching of the switching devices,
the memory device is used for storing the data,
a plurality of interface controllers, the number of the interface controllers is the same as the number of the processors, the ith interface controller is matched with the communication data interface of the ith processor,
the exchange controller is used for determining a candidate sender processor of the kth communication, determining a sender processor of the kth communication from the candidate sender processors of the kth communication, and sending an allowance notification to the sender processor of the kth communication, wherein the allowance notification is used for instructing the sender processor of the kth communication to send the kth data to the corresponding interface controller, the receiver processor of the kth data is any processor except the sender processor, and i and k are positive integers;
the memory is used for storing kth data received from the corresponding interface controller;
the exchange controller is further configured to send the kth data stored in the memory to the receiver processor through an interface controller corresponding to the receiver processor of the kth data.
2. The multiprocessor cross communication apparatus of claim 1, wherein the switch controller is further configured to,
receiving a communication ending application sent by a sender processor of the kth communication, and removing the processor sending the communication ending application from the candidate sender processors, wherein the communication ending application is sent by the sender processor of the kth communication after sending data;
and after the candidate sender processor of the kth communication is determined, receiving a communication application sent by the processor, and taking the processor sending the communication application as the candidate sender processor.
3. The multiprocessor cross communication apparatus of claim 2, wherein the switch controller is further configured to,
when a communication end application transmitted by the sender processor of the kth communication is received and there is no data in the memory, determining a candidate sender processor of the kth +1 communication,
when the candidate sender processor for the k+1th communication includes at least one processor, determining a sender processor for the k+1th communication from among the candidate sender processors for the k+1th communication,
when the number of at least one of the processors in the k+1th communication candidate sender processor is greater than the number of the k communication sender processor, the k+1th communication sender processor is the first processor sequentially arranged after the k communication sender processor,
when the number of each processor in the k+1th communication candidate sender processor is smaller than the number of the k communication sender processor, the number of the k+1th communication sender processor is the smallest number in the numbers of the processors.
4. The multiprocessor cross communication apparatus of claim 1, wherein the switch controller is further configured to,
and after the candidate sender processor of the kth communication is determined, receiving a communication revocation application sent by the processor, and removing the processor sending the communication revocation application from the candidate sender processor, wherein the communication revocation application is sent by the corresponding processor after the communication application is sent.
5. The multiprocessor cross communication apparatus of claim 1, wherein the kth data comprises a source address field, a destination address field, and a valid data field,
the source address field includes the number of the sender processor of the kth communication,
the destination address field includes the number of the recipient processor of the kth data,
the valid data field includes the kth data.
6. A multi-processor cross-communication method, the multi-processor cross-communication method comprising:
a candidate sender processor for the kth communication is determined,
determining a sender processor of a kth communication from the candidate sender processors of the kth communication,
transmitting an permission notification to a sender processor of the kth communication, the permission notification being for instructing the sender processor of the kth communication to send kth data to a corresponding interface controller, a receiver processor of the kth data being any one processor other than the sender processor, the number of the interface controllers being the same as the number of the processors, an ith one of the interface controllers being matched with a communication data interface of the ith one of the processors,
and sending the kth data to the receiver processor through an interface controller corresponding to the receiver processor of the kth data.
7. The multiprocessor cross-communication method of claim 6, wherein the method further comprises:
receiving a communication ending application sent by a sender processor of the kth communication, and removing the processor sending the communication ending application from the candidate sender processors, wherein the communication ending application is sent by the sender processor of the kth communication after sending data;
and after the candidate sender processor of the kth communication is determined, receiving a communication application sent by the processor, and taking the processor sending the communication application as the candidate sender processor.
8. The multiprocessor cross-communication method of claim 7, wherein the method further comprises:
when a communication end application transmitted by the sender processor of the kth communication is received and there is no data in the memory, determining a candidate sender processor of the kth +1 communication,
when the candidate sender processor for the k+1th communication includes at least one processor, determining a sender processor for the k+1th communication from among the candidate sender processors for the k+1th communication,
when the number of at least one of the processors in the k+1th communication candidate sender processor is greater than the number of the k communication sender processor, the k+1th communication sender processor is the first processor sequentially arranged after the k communication sender processor,
when the number of each processor in the k+1th communication candidate sender processor is smaller than the number of the k communication sender processor, the number of the k+1th communication sender processor is the smallest number in the numbers of the processors.
9. The multiprocessor cross communication method of claim 6, wherein after said determining a candidate sender processor for a kth communication, the method further comprises:
and receiving a communication revocation application sent by the processor, and removing the processor sending the communication revocation application from the candidate sender processor, wherein the communication revocation application is sent by the corresponding processor after the communication application is sent.
10. The multiprocessor cross communication method of claim 6, wherein the kth data includes a source address field, a destination address field, and a valid data field,
the source address field includes the number of the sender processor of the kth communication,
the destination address field includes the number of the recipient processor of the kth data,
the valid data field includes the kth data.
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