CN111049514A - Level conversion circuit - Google Patents

Level conversion circuit Download PDF

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Publication number
CN111049514A
CN111049514A CN201911256012.XA CN201911256012A CN111049514A CN 111049514 A CN111049514 A CN 111049514A CN 201911256012 A CN201911256012 A CN 201911256012A CN 111049514 A CN111049514 A CN 111049514A
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pmos tube
pull
voltage
circuit
tube
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黄明永
贾敏
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN201911256012.XA priority Critical patent/CN111049514A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a level conversion circuit, comprising: the main circuit comprises a first CMOS inverter and a second CMOS inverter, and a first input circuit and a second input circuit. The main circuit is connected between a first power supply voltage and a second negative voltage. The first input circuit and the second input circuit respectively comprise a pull-up PMOS tube and a control circuit for controlling the drain voltage of the pull-up PMOS tube, and the control circuit controls the voltage difference between electrodes of the corresponding pull-up PMOS tubes to be within the range of the first power supply voltage, so that the pull-up PMOS tubes can be driven well under the first power supply voltage by adopting the PMOS tubes with the working voltage close to the maximum value of the first power supply voltage. The invention can improve the driving capability of the pull-up PMOS tube under the condition of realizing the level conversion of small power supply voltage and negative voltage, and improve the working speed of the circuit.

Description

Level conversion circuit
Technical Field
The present invention relates to a semiconductor Integrated Circuit (IC), and more particularly, to a level shift circuit.
Background
In a flash (flash) IP designed on a 55nm technology, a voltage of-0.4 v is used in a decoding circuit, so a level conversion circuit for operating from a power supply voltage VDD to-0.4 v is required. With the process being more advanced, the power supply voltage is lower, and in the 55nm process, the power supply voltage is as low as 1.2 v. There is a margin left in the design to account for supply voltages as low as 1.05 v.
As shown in fig. 1, it is a circuit diagram of a conventional level shift circuit; the main body circuit comprises a first CMOS phase inverter consisting of an NMOS tube NM101 and a PMOS tube PM101 and a second CMOS phase inverter consisting of an NMOS tube NM102 and a PMOS tube PM 102. The PMOS tubes PM103 and PM104 are pull-up tubes. The main circuit is connected between the power supply voltage VDD and the negative voltage Vneg, and outputs output signals Va and Vab that are opposite in phase to each other.
The input signals VIN and VINN which are in opposite phase to each other are respectively connected to the gates of the PMOS transistors PM103 and PM104, the sources of the PMOS transistors PM103 and PM104 are both connected to the power voltage VDD, and the drains of the PMOS transistors PM103 and PM104 are respectively connected to the corresponding nodes of the output signals Va and Vab.
A capacitor C101 is connected between the output terminal of the first CMOS inverter and ground GND, and the output signal Vab can be output through one CMOS inverter.
The PMOS transistors PM103 and PM104 act as pull-up transistors, and the voltage difference between the source (S), drain (D), gate (G) and substrate electrode (B) is usually larger than the power voltage VDD. Therefore, the voltage endurance of the PMOS transistors PM103 and PM104 needs to be larger than the power supply voltage. When the power supply voltage is reduced to 1.2V, the PMOS transistors PM103 and PM104 cannot be designed with a 1.2V process corner (corner) device (device) structure. Considering low cost and less mask (mask). Generally, a 5V high voltage device is selected to design the level shift circuit, for example, the MOS transistors with 5V resistance of the PMOS transistors PM103 and PM104, including NMOS transistors and PMOS transistors, have threshold voltages higher than 0.8V and-0.8V below ss corner temperature, respectively. And when the power voltage is 1.05V, the 5V high-voltage device is just opened, and the driving capability is very weak. Level-shift works very slowly and the cross (cross) currents are large.
Disclosure of Invention
The invention aims to provide a level conversion circuit which can improve the driving capability of a pull-up PMOS tube and improve the working speed of the circuit under the condition of realizing level conversion of small power supply voltage and negative voltage.
To solve the above technical problem, the level shift circuit provided by the present invention comprises: the main circuit comprises a first CMOS inverter and a second CMOS inverter, and a first input circuit and a second input circuit.
The output end of the first CMOS phase inverter is connected with the input end of the second CMOS phase inverter and outputs a positive phase output signal, and the output end of the second CMOS phase inverter is connected with the input end of the first CMOS phase inverter and outputs an inverted phase output signal.
The main circuit is connected between a first power supply voltage and a second negative voltage, and the positive phase output signal and the reverse phase output signal work between the first power supply voltage and the second negative voltage.
The input end of the first input circuit is connected with a positive phase input signal, and the input end of the second input circuit is connected with an inverse phase input signal.
The output end of the first input circuit is connected with the input end of the first CMOS phase inverter, and the output end of the second input short circuit is connected with the input end of the second CMOS phase inverter.
The non-inverting input signal and the inverting input signal both operate between a first supply voltage and ground.
The first input circuit comprises a first pull-up PMOS tube, and the second input circuit comprises a second pull-up PMOS tube.
And the grid electrode of the first pull-up PMOS tube is used as the input end of the first input circuit, and the grid electrode of the second pull-up PMOS tube is used as the input end of the second input circuit.
The source electrode of the first pull-up PMOS tube is connected with the first power supply voltage, and the source electrode of the second pull-up PMOS tube is connected with the first power supply voltage.
The first input circuit further comprises a first control circuit, the first control circuit enables the drain voltage of the first pull-up PMOS tube to be pulled down to 0V and not lower than 0V when the positive-phase input signal is at a high level, the influence of the second negative voltage on the voltage difference among the source electrode, the drain electrode and the grid electrode of the first pull-up PMOS tube is prevented, the voltage difference among the source electrode, the drain electrode and the grid electrode of the first pull-up PMOS tube is ensured to be within the range of the first power voltage, the first pull-up PMOS tube is enabled to adopt a PMOS tube with the working voltage close to the maximum value of the first power voltage, and the first pull-up PMOS tube can be driven well under the first power voltage.
The second input circuit further comprises a second control circuit, the second control circuit enables the drain voltage of the second pull-up PMOS tube to be pulled down to 0V or not less than 0V when the inverted input signal is at a high level, the influence of the second negative voltage on the voltage difference among the source electrode, the drain electrode and the grid electrode of the second pull-up PMOS tube is prevented, the voltage difference among the source electrode, the drain electrode and the grid electrode of the second pull-up PMOS tube is ensured to be within the range of the first power voltage, the second pull-up PMOS tube adopts a PMOS tube with the working voltage close to the maximum value of the first power voltage, and the threshold voltage of the second pull-up PMOS tube is lower than the first power voltage and can be well driven under the first power voltage.
In a further improvement, the first control circuit comprises a third PMOS transistor and a first NMOS transistor.
The source electrode of the third PMOS tube is connected with the drain electrode of the first pull-up PMOS tube, the grid electrode of the third PMOS tube is grounded, the drain electrode of the third PMOS tube is used as the output end of the first input circuit, and the third PMOS tube is used for preventing the drain electrode voltage of the first pull-up PMOS tube from being pulled down to the second negative voltage when the normal-phase input signal is at a high level.
The grid electrode of the first NMOS tube is connected with the positive phase input signal, the source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is connected with the drain electrode of the first pull-up PMOS tube, and the first NMOS tube is used for enabling the drain electrode voltage of the first pull-up PMOS tube to be pulled down to 0V when the positive phase input signal is at a high level.
In a further improvement, the first control circuit comprises a fourth PMOS transistor and a second NMOS transistor.
The source electrode of the fourth PMOS tube is connected with the drain electrode of the second pull-up PMOS tube, the grid electrode of the fourth PMOS tube is grounded, the drain electrode of the fourth PMOS tube is used as the output end of the second input circuit, and the fourth PMOS tube is used for preventing the drain electrode voltage of the second pull-up PMOS tube from being pulled down to the second negative voltage when the reverse-phase input signal is at a high level.
The grid electrode of the second NMOS tube is connected with the inverted input signal, the source electrode of the second NMOS tube is grounded, the drain electrode of the second NMOS tube is connected with the drain electrode of the second pull-up PMOS tube, and the second NMOS tube is used for enabling the drain electrode voltage of the second pull-up PMOS tube to be pulled down to 0V when the positive-phase input signal is at a high level.
In a further improvement, the first CMOS inverter is formed by connecting a fifth PMOS transistor and a third NMOS transistor.
The source electrode of the fifth PMOS tube is connected with the first power voltage, and the source electrode of the third NMOS tube is grounded.
And the grid electrode of the fifth PMOS tube is connected with the grid electrode of the third NMOS tube and is used as the input end of the first CMOS phase inverter.
And the drain electrode of the fifth PMOS tube is connected with the drain electrode of the third NMOS tube and is used as the output end of the first CMOS phase inverter.
In a further improvement, the second CMOS inverter is formed by connecting a sixth PMOS transistor and a fourth NMOS transistor.
The source electrode of the sixth PMOS tube is connected with the first power voltage, and the source electrode of the fourth NMOS tube is grounded.
And the grid electrode of the sixth PMOS tube is connected with the grid electrode of the fourth NMOS tube and is used as the input end of the second CMOS phase inverter.
And the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fourth NMOS tube and is used as the output end of the second CMOS phase inverter.
In a further improvement, the level shift circuit is used for increasing the level-shifted signal for a decoding circuit of the flash memory.
The further improvement is that the process node of the decoding circuit of the flash memory is below 55 nm.
In a further improvement, the first power supply voltage is designed to be 1.2V in the flash memory.
In a further improvement, the second negative voltage is-0.4V.
In a further improvement, the first power supply voltage in the flash memory has a margin in design, and the actual minimum value of the first power supply voltage is 1.05V.
In a further improvement, the first pull-up PMOS tube and the second pull-up PMOS tube both adopt 1.2V PMOS tubes.
In a further improvement, the inverted input signal is obtained by inverting the non-inverted input signal through an inverter.
In a further improvement, a capacitor is connected between the output end of the first CMOS inverter and the ground.
In a further improvement, a capacitor is connected between the output end of the second CMOS inverter and the ground.
The invention arranges a first input circuit and a second input circuit, and arranges a control circuit for controlling the drain voltage of a pull-up PMOS tube on the basis of comprising the pull-up PMOS tube, the voltage difference between electrodes of the pull-up PMOS tube can be ensured to be within the range of power voltage through the arrangement of the control circuit, so that the working voltage of the pull-up PMOS tube is close to the PMOS tube with the maximum value of the first power voltage, and compared with the structure of the pull-up PMOS tube in the prior art, wherein the withstand voltage of the pull-up PMOS tube is larger than the power voltage, the threshold voltage of the pull-up PMOS tube can be effectively reduced, so that the pull-up PMOS tube can be well driven under the first power voltage, namely the pull-up PMOS tube can be well driven under the regulation of the small first power voltage, so that the driving capability of the pull-up PMOS tube can be improved under the condition of realizing the level conversion of the small power voltage and the negative voltage, and the working speed of the circuit is improved; cross currents can also be reduced.
The invention is particularly suitable for the flash memory with the design value of the first power supply voltage of 1.2V and the second negative voltage of-0.4V.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a circuit diagram of a prior art level shift circuit;
fig. 2 is a circuit diagram of a level shift circuit according to an embodiment of the present invention.
Detailed Description
FIG. 2 is a circuit diagram of a level shift circuit according to an embodiment of the present invention; the level shift circuit of the embodiment of the invention comprises: a main body circuit 1 composed of a first CMOS inverter 2a and a second CMOS inverter 2b, a first input circuit 3a and a second input circuit 3 b.
The output end of the first CMOS inverter 2a is connected to the input end of the second CMOS inverter 2b and outputs a positive phase output signal Vab, and the output end of the second CMOS inverter 2b is connected to the input end of the first CMOS inverter 2a and outputs an inverted phase output signal Va.
The main body circuit 1 is connected between a first power supply voltage VDD and a second negative voltage Vneg, and the positive phase output signal Vab and the negative phase output signal Va are both operated between the first power supply voltage VDD and the second negative voltage Vneg.
The input end of the first input circuit 3a is connected to the positive phase input signal VIN, and the input end of the second input circuit 3b is connected to the negative phase input signal VINN.
The output end of the first input circuit 3a is connected with the input end of the first CMOS inverter 2a, and the output end of the second input short circuit is connected with the input end of the second CMOS inverter 2 b.
The non-inverting input signal VIN and the inverting input signal VINN both operate between a first power voltage VDD and ground GND.
The first input circuit 3a includes a first pull-up PMOS transistor MP1, and the second input circuit 3b includes a second pull-up PMOS transistor MP 2.
The gate of the first pull-up PMOS transistor MP1 is used as the input terminal of the first input circuit 3a, and the gate of the second pull-up PMOS transistor MP2 is used as the input terminal of the second input circuit 3 b.
The source of the first pull-up PMOS transistor MP1 is connected to the first power voltage VDD, and the source of the second pull-up PMOS transistor MP2 is connected to the first power voltage VDD.
The first input circuit 3a further includes a first control circuit 4a, the first control circuit 4a causes the drain voltage of the first pull-up PMOS transistor MP1 to be pulled down to 0V or not less than 0V when the positive-phase input signal VIN is at a high level, so as to prevent the second negative voltage Vneg from affecting the voltage difference between the source, the drain and the gate of the first pull-up PMOS transistor MP1, so as to ensure that the voltage differences between the source, the drain and the gate of the first pull-up PMOS transistor MP1 are all within the range of the first power voltage VDD, and the first pull-up PMOS transistor MP1 employs a PMOS transistor whose operating voltage is close to the maximum value of the first power voltage VDD, so that the first pull-up PMOS transistor MP1 can be driven well at the first power voltage VDD.
The second input circuit 3b further includes a second control circuit 4b, and the second control circuit 4b causes the drain voltage of the second pull-up PMOS transistor MP2 to be pulled down to 0V or not less than 0V when the inverted input signal VINN is at a high level, so as to prevent the second negative voltage Vneg from affecting the voltage differences among the source, the drain, and the gate of the second pull-up PMOS transistor MP2, so as to ensure that the voltage differences among the source, the drain, and the gate of the second pull-up PMOS transistor MP2 are all within the range of the first power voltage VDD, and cause the second pull-up PMOS transistor MP2 to employ a PMOS transistor whose operating voltage is close to the maximum value of the first power voltage VDD, so that the threshold voltage of the second pull-up PMOS transistor MP2 is lower than the first power voltage VDD and can be driven well at the first power voltage VDD.
The first control circuit 4a includes a third PMOS transistor MP3 and a first NMOS transistor MN 1.
The source of the third PMOS transistor MP3 is connected to the drain of the first pull-up PMOS transistor MP1, the gate of the third PMOS transistor MP3 is grounded GND, the drain of the third PMOS transistor MP3 is used as the output terminal of the first input circuit 3a, and the third PMOS transistor MP3 is configured to prevent the drain voltage of the first pull-up PMOS transistor MP1 from being pulled down to the second negative voltage Vneg when the positive-phase input signal VIN is at a high level.
The gate of the first NMOS transistor MN1 is connected to the positive-phase input signal VIN, the source is grounded GND, and the drain is connected to the drain of the first pull-up PMOS transistor MP1, and the first NMOS transistor MN1 is configured to pull down the drain voltage of the first pull-up PMOS transistor MP1 to 0V when the positive-phase input signal VIN is at a high level.
The first control circuit 4a includes a fourth PMOS transistor MP4 and a second NMOS transistor MN 2.
A source of the fourth PMOS transistor MP4 is connected to a drain of the second pull-up PMOS transistor MP2, a gate of the fourth PMOS transistor MP4 is grounded to GND, a drain of the fourth PMOS transistor MP4 is used as an output terminal of the second input circuit 3b, and the fourth PMOS transistor MP4 is configured to prevent the drain voltage of the second pull-up PMOS transistor MP2 from being pulled down to the second negative voltage Vneg when the inverted input signal VINN is at a high level.
The gate of the second NMOS transistor MN2 is connected to the inverted input signal VINN, the source is grounded GND, and the drain is connected to the drain of the second pull-up PMOS transistor MP2, and the second NMOS transistor MN2 is configured to pull down the drain voltage of the second pull-up PMOS transistor MP2 to 0V when the non-inverted input signal VIN is at a high level.
The first CMOS inverter 2a is formed by connecting a fifth PMOS transistor MP5 and a third NMOS transistor MN 3.
The source of the fifth PMOS transistor MP5 is connected to the first power voltage VDD, and the source of the third NMOS transistor MN3 is grounded GND.
The gate of the fifth PMOS transistor MP5 is connected to the gate of the third NMOS transistor MN3 and serves as the input terminal of the first CMOS inverter 2 a.
The drain of the fifth PMOS transistor MP5 is connected to the drain of the third NMOS transistor MN3 and serves as the output terminal of the first CMOS inverter 2 a.
The second CMOS inverter 2b is formed by connecting a sixth PMOS transistor MP6 and a fourth NMOS transistor MN 4.
The source of the sixth PMOS transistor MP6 is connected to the first power voltage VDD, and the source of the fourth NMOS transistor MN4 is grounded GND.
The gate of the sixth PMOS transistor MP6 is connected to the gate of the fourth NMOS transistor MN4 and serves as the input terminal of the second CMOS inverter 2 b.
The drain of the sixth PMOS transistor MP6 is connected to the drain of the fourth NMOS transistor MN4 and serves as the output terminal of the second CMOS inverter 2 b.
The level conversion circuit is used for improving the level-converted signal for the decoding circuit of the flash memory.
Preferably, the process node of the decoding circuit of the flash memory is less than 55 nm. The design value of the first power voltage VDD in the flash memory is 1.2V. The second negative voltage Vneg is-0.4V. The first power voltage VDD in the flash memory has a margin in design, and the actual lowest value of the first power voltage VDD is 1.05V. The first pull-up PMOS transistor MP1 and the second pull-up PMOS transistor MP2 both adopt 1.2V PMOS transistors.
The inverting input signal VINN is obtained by inverting the non-inverting input signal VIN through an inverter.
A capacitor C1 is connected between the output terminal of the first CMOS inverter 2a and ground GND.
And a capacitor is connected between the output end of the second CMOS inverter 2b and the ground GND.
The embodiment of the invention is provided with a first input circuit 3a and a second input circuit 3b, a control circuit for controlling the drain voltage of a pull-up PMOS tube is arranged on the basis of the pull-up PMOS tube, the voltage difference between electrodes of the pull-up PMOS tube can be ensured to be within the range of the power voltage through the arrangement of the control circuit, so that the working voltage of the pull-up PMOS tube is close to the maximum value of the first power voltage VDD, compared with the structure of the pull-up PMOS tube in the prior art, the threshold voltage of the pull-up PMOS tube can be effectively reduced, the pull-up PMOS tube can be well driven under the first power voltage VDD, namely, the pull-up PMOS tube can be well driven under the regulation of the first power voltage VDD, so that the driving capability of the pull-up PMOS tube can be improved under the condition of realizing the level conversion of small power voltage and negative voltage, the working speed of the circuit is improved; cross currents can also be reduced.
The embodiment of the invention is particularly suitable for the flash memory with the design value of the first power supply voltage VDD being 1.2V and the second negative voltage Vneg being-0.4V.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (14)

1. A level shift circuit, comprising: a main body circuit composed of a first CMOS inverter and a second CMOS inverter, a first input circuit and a second input circuit;
the output end of the first CMOS phase inverter is connected with the input end of the second CMOS phase inverter and outputs a positive phase output signal, and the output end of the second CMOS phase inverter is connected with the input end of the first CMOS phase inverter and outputs an inverted phase output signal;
the main circuit is connected between a first power supply voltage and a second negative voltage, and the positive phase output signal and the reverse phase output signal work between the first power supply voltage and the second negative voltage;
the input end of the first input circuit is connected with a positive phase input signal, and the input end of the second input circuit is connected with an inverse phase input signal;
the output end of the first input circuit is connected with the input end of the first CMOS phase inverter, and the output end of the second input short circuit is connected with the input end of the second CMOS phase inverter;
the non-inverting input signal and the inverting input signal both operate between a first supply voltage and ground;
the first input circuit comprises a first pull-up PMOS tube, and the second input circuit comprises a second pull-up PMOS tube;
the grid electrode of the first pull-up PMOS tube is used as the input end of the first input circuit, and the grid electrode of the second pull-up PMOS tube is used as the input end of the second input circuit;
the source electrode of the first pull-up PMOS tube is connected with the first power supply voltage, and the source electrode of the second pull-up PMOS tube is connected with the first power supply voltage;
the first input circuit further comprises a first control circuit, the first control circuit enables the drain voltage of the first pull-up PMOS tube to be pulled down to 0V or not less than 0V when the positive-phase input signal is at a high level, the influence of the second negative voltage on the voltage difference among the source electrode, the drain electrode and the grid electrode of the first pull-up PMOS tube is prevented, the voltage difference among the source electrode, the drain electrode and the grid electrode of the first pull-up PMOS tube is ensured to be within the range of the first power voltage, and the first pull-up PMOS tube adopts a PMOS tube with the working voltage close to the maximum value of the first power voltage, so that the first pull-up PMOS tube can be driven well under the first power voltage;
the second input circuit further comprises a second control circuit, the second control circuit enables the drain voltage of the second pull-up PMOS tube to be pulled down to 0V or not less than 0V when the inverted input signal is at a high level, the influence of the second negative voltage on the voltage difference among the source electrode, the drain electrode and the grid electrode of the second pull-up PMOS tube is prevented, the voltage difference among the source electrode, the drain electrode and the grid electrode of the second pull-up PMOS tube is ensured to be within the range of the first power voltage, the second pull-up PMOS tube adopts a PMOS tube with the working voltage close to the maximum value of the first power voltage, and the threshold voltage of the second pull-up PMOS tube is lower than the first power voltage and can be well driven under the first power voltage.
2. The level shift circuit of claim 1, wherein: the first control circuit comprises a third PMOS tube and a first NMOS tube;
the source electrode of the third PMOS tube is connected with the drain electrode of the first pull-up PMOS tube, the grid electrode of the third PMOS tube is grounded, the drain electrode of the third PMOS tube is used as the output end of the first input circuit, and the third PMOS tube is used for preventing the drain electrode voltage of the first pull-up PMOS tube from being pulled down to the second negative voltage when the normal-phase input signal is at a high level;
the grid electrode of the first NMOS tube is connected with the positive phase input signal, the source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is connected with the drain electrode of the first pull-up PMOS tube, and the first NMOS tube is used for enabling the drain electrode voltage of the first pull-up PMOS tube to be pulled down to 0V when the positive phase input signal is at a high level.
3. The level shift circuit of claim 1, wherein: the first control circuit comprises a fourth PMOS tube and a second NMOS tube;
the source electrode of the fourth PMOS tube is connected with the drain electrode of the second pull-up PMOS tube, the grid electrode of the fourth PMOS tube is grounded, the drain electrode of the fourth PMOS tube is used as the output end of the second input circuit, and the fourth PMOS tube is used for preventing the drain electrode voltage of the second pull-up PMOS tube from being pulled down to the second negative voltage when the reverse-phase input signal is at a high level;
the grid electrode of the second NMOS tube is connected with the inverted input signal, the source electrode of the second NMOS tube is grounded, the drain electrode of the second NMOS tube is connected with the drain electrode of the second pull-up PMOS tube, and the second NMOS tube is used for enabling the drain electrode voltage of the second pull-up PMOS tube to be pulled down to 0V when the positive-phase input signal is at a high level.
4. The level shift circuit of claim 1, wherein: the first CMOS phase inverter is formed by connecting a fifth PMOS tube and a third NMOS tube;
the source electrode of the fifth PMOS tube is connected with the first power supply voltage, and the source electrode of the third NMOS tube is grounded;
the grid electrode of the fifth PMOS tube is connected with the grid electrode of the third NMOS tube and is used as the input end of the first CMOS phase inverter;
and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the third NMOS tube and is used as the output end of the first CMOS phase inverter.
5. The level shift circuit of claim 4, wherein: the second CMOS phase inverter is formed by connecting a sixth PMOS tube and a fourth NMOS tube;
the source electrode of the sixth PMOS tube is connected with the first power supply voltage, and the source electrode of the fourth NMOS tube is grounded;
the grid electrode of the sixth PMOS tube is connected with the grid electrode of the fourth NMOS tube and serves as the input end of the second CMOS phase inverter;
and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fourth NMOS tube and is used as the output end of the second CMOS phase inverter.
6. The level shift circuit of claim 1, wherein: the level conversion circuit is used for improving the level-converted signal for the decoding circuit of the flash memory.
7. The level shift circuit of claim 6, wherein: the process node of the decoding circuit of the flash memory is less than 55 nm.
8. The level shift circuit of claim 7, wherein: the design value of the first power supply voltage in the flash memory is 1.2V.
9. The level shift circuit of claim 8, wherein: the second negative voltage is-0.4V.
10. The level shift circuit of claim 9, wherein: the first power supply voltage in the flash memory has a margin in design, and the actual lowest value of the first power supply voltage reaches 1.05V.
11. The level shift circuit of claim 10, wherein: the first pull-up PMOS tube and the second pull-up PMOS tube both adopt 1.2V PMOS tubes.
12. The level shift circuit of claim 1, wherein: and the reverse phase input signal is obtained by inverting the phase of the normal phase input signal through an inverter.
13. The level shift circuit of claim 1, wherein: and a capacitor is connected between the output end of the first CMOS inverter and the ground.
14. The level shift circuit of claim 1, wherein: and a capacitor is connected between the output end of the second CMOS inverter and the ground.
CN201911256012.XA 2019-12-10 2019-12-10 Level conversion circuit Pending CN111049514A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990024754A (en) * 1997-09-06 1999-04-06 구본준 Input buffer circuit of semiconductor memory
CN103208988A (en) * 2013-04-24 2013-07-17 上海宏力半导体制造有限公司 Level shifting circuit and method for conducting positive voltage level shifting and negative voltage level shifting
US20180034464A1 (en) * 2015-02-12 2018-02-01 Qualinx B.V. Level shifter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990024754A (en) * 1997-09-06 1999-04-06 구본준 Input buffer circuit of semiconductor memory
CN103208988A (en) * 2013-04-24 2013-07-17 上海宏力半导体制造有限公司 Level shifting circuit and method for conducting positive voltage level shifting and negative voltage level shifting
US20180034464A1 (en) * 2015-02-12 2018-02-01 Qualinx B.V. Level shifter

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