CN111026427B - Remote online upgrading method for embedded system containing CPU and FPGA - Google Patents

Abstract

The invention relates to a method for remotely upgrading an embedded system on line, which comprises a CPU and an FPGA, wherein the CPU (which can be a general CPU, a DSP, an MCU and the like) directly or indirectly shares a Flash with the FPGA, and an operating system, application software, logic, a lookup table and the like which are operated on the CPU and the FPGA are stored in the Flash; the FPGA ensures that the access to the Flash is not conflicted by controlling the reset state of the CPU; and after the FPGA completes the logic loading, the access authority of the Flash is given to a CPU, and the CPU realizes the online upgrade of the FPGA through the direct access of the Flash. By using the invention, the upgrading interface of the application software/logic can be unified on the basis of realizing remote online upgrading, the reliability and the upgrading speed are considered, and the upgrading complexity of the system is reduced.

Description

Remote online upgrading method for embedded system containing CPU and FPGA

Technical Field

The invention relates to the technical field of electronics, in particular to the technical field of software and hardware design of an embedded system.

Background

In the design of an embedded system, an FPGA (Field programmable Gate Array) and a CPU are often used simultaneously; the FPGA relates to the online burning of data required by the operation of logic and other logics, and the CPU relates to the online burning of an operating system and application software; there is often a need for remote upgrades.

The existing upgrading mode mainly comprises the following steps:

the CPU and the FPGA are independently upgraded through different interfaces; the upgrading interface of the CPU comprises special interfaces such as JTAG (Joint Test Action Group), serial interfaces such as RS232/422/485 and high-speed data interfaces such as Ethernet and PCIe; the upgrading interface of the FPGA is mainly JTAG;

in addition, a CPU is adopted in a part of embedded systems to carry out programming of FPGA logic and the like; the CPU receives target code data from the outside through an external bus, sends the target code data to the FPGA and completes the programming of FPGA logic by the FPGA;

the main disadvantages of the existing upgrading mode are as follows:

1. the JTAG interface has no uniformly specified level format, is generally LVTTL or LVCMOS, has limited transmission distance (generally not more than 1m) and low transmission bandwidth (generally not more than 10Mbps, and has lower effective bandwidth); moreover, JTAG upgrading usually needs a special programmer, and programmers of different manufacturers and different devices cannot be used in a compatible manner;

2. in the mode that the target code required by the FPGA is sent to the FPGA through the CPU and the FPGA completes the burning, the reliability and the speed of the burning process are low due to the transfer link from the CPU to the FPGA;

3. at present, erasing and writing of Flash, especially erasing and writing of Flash storing FPGA logic, basically completely erases a required target sector and writes new data into the target sector, and whether existing sector data are necessary to be erased or not is not considered; for devices such as Flash, the lifetime of which is calculated by the erasing frequency is not favorable for long-term reliable operation.

Disclosure of Invention

Technical problem to be solved

In order to avoid the defects of the prior art, the invention provides a remote online upgrading method of an embedded system containing a CPU and an FPGA, which realizes online upgrading of a CPU operating system, application software, FPGA logic and the like by sharing Flash, and has simple, flexible and more reliable upgrading process.

Technical scheme

A remote online upgrade method for an embedded system containing a CPU and an FPGA is characterized in that the CPU and the FPGA use the same Flash storage object code, the FPGA and the CPU are directly connected with the Flash, the FPGA ensures that the access of the CPU and the Flash is not conflicted in time by controlling a reset signal of the CPU, and the method is characterized by comprising the following steps:

step 1: after the system is powered on, a DONE signal of the FPGA is pulled low, and the reset signal of the CPU is controlled to be constantly low through the AND gate in the logic loading process of the FPGA;

step 2: after the logic loading of the FPGA is successful, pulling up a DONE signal, simultaneously logically controlling one I/O pin to be low until the FPGA finishes all access operations to the Flash, and continuously controlling the reset signal of the CPU to be low by the I/O pin through an AND gate in the access process of the FPGA to the Flash;

and step 3: if the FPGA logic loading fails, the FPGA jumps to a default address to load the backup logic stored in the area;

and 4, step 4: after the FPGA finishes accessing the Flash, setting a Flash read-write control pin to be in a high resistance state, and then setting an I/O pin for controlling the reset of the CPU to be in a high level;

and 5: the CPU reads the target code from the Flash and starts the target code;

and 7: the CPU obtains an upgrading command through an Ethernet interface and receives a target code file to be updated by adopting a UDP protocol;

and step 8: the CPU stores the completely received target code file to be updated in the memory; acquiring verification information and a file type from header information of the object code file;

and step 9: the CPU carries out size end conversion on the target code file in the memory according to the size end conversion mark in the received upgrading command;

step 10: the CPU writes the target code file after the conversion of the big end and the small end into Flash, the target value is compared with the current data of a certain sector before the writing in by taking the sector as a unit, if the target value is different from the current data of the certain sector, the writing operation is executed, and if the target value is the same as the current data of the certain sector, the erasing and writing operation of the sector is skipped;

step 11: and after completing the Flash erasing operation, the CPU reads back the data in the Flash, compares the data with the target code file in the memory, and sends the result as a written named return value to the source end computer through the Ethernet.

A remote online upgrade method for an embedded system containing a CPU and an FPGA is characterized in that the CPU and the FPGA use the same Flash storage object code, Flash and the CPU are directly connected with the FPGA, but the CPU is not directly connected with the Flash, and the FPGA logically realizes the signal connection from the CPU to the Flash, and is characterized by comprising the following steps:

step 1: in the FPGA loading process after the system is powered on, I/O pins of the FPGA are all in a high-resistance state;

step 2: after the logic loading of the FPGA is successful and all access operations to the Flash are completed, the FPGA connects a Flash read-write pin of the CPU with a response pin of the Flash, and resets the CPU through an I/O pin connected with a CPU reset signal;

and step 3: the CPU reads the target code from the Flash and starts the target code;

and 4, step 4: the CPU obtains an upgrading command through an Ethernet interface and receives a target code file to be updated by adopting a UDP protocol;

and 5: the CPU stores the completely received target code file to be updated in the memory; acquiring verification information and a file type from header information of the object code file;

step 6: the CPU carries out size end conversion on the target code file in the memory according to the size end conversion mark in the received upgrading command;

and 7: the CPU writes the target code file after the conversion of the big end and the small end into Flash, the target value is compared with the current data of a certain sector before the writing in by taking the sector as a unit, if the target value is different from the current data of the certain sector, the writing operation is executed, and if the target value is the same as the current data of the certain sector, the erasing and writing operation of the sector is skipped;

and 8: and after completing the Flash erasing operation, the CPU reads back the data in the Flash, compares the data with the target code file in the memory, and sends the result as a written named return value to the source end computer through the Ethernet.

Advantageous effects

The invention provides a remote online upgrade method of an embedded system containing a CPU and an FPGA, which realizes the remote online upgrade of an operating system, application software, logic and other data required by the operation of the FPGA in the embedded system by a mode that the CPU and the FPGA share a Flash and by adopting the same external interface and a uniform operation mode; the upgrading process is directly controlled by a CPU in the embedded system; by optimizing the strategy of writing in the Flash data, the erasing and writing times of the Flash sector are effectively reduced, and the method has great significance for prolonging the service life of the Flash.

Drawings

FIG. 1 is a system diagram according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a start-up process of an FPGA and a CPU according to a first embodiment of the present invention;

FIG. 3 is a schematic diagram of the upgrading process of the target code after the CPU is started;

FIG. 4 is a system diagram of a second embodiment of the present invention;

fig. 5 is a schematic diagram of a start-up flow of the FPGA and the CPU in the second embodiment of the present invention.

Detailed Description

The invention will now be further described with reference to the following examples and drawings:

in the remote online upgrading method of the embedded system comprising the CPU and the FPGA, the CPU and the FPGA use the same Flash to store an object code; the FPGA and the CPU realize the sharing of Flash through two modes:

1. the FPGA and the CPU are directly connected with the Flash, and the FPGA ensures that the access of the FPGA and the CPU to the Flash is not conflicted in time by controlling a reset signal of the CPU;

2. flash and CPU are directly connected with FPGA, but CPU is not directly connected with Flash, and signal connection from CPU to Flash is realized by FPGA logic.

For the Flash with the parallel interface, the FPGA ensures that the access to the Flash is free from conflict with a CPU in space by controlling a high-order address line after being electrified.

The FPGA is started before the CPU after being electrified, and a DONE signal is continuously low in the starting process of the FPGA; the FPGA uses the DONE signal to carry out phase connection with one I/O pin of the FPGA and then connects with a reset input pin of the control CPU; after the logic loading is finished, the FPGA controls the I/O pin to realize the control of the CPU reset signal;

after the FPGA accesses the Flash memory, the pin for controlling the reading and writing of the Flash is changed into a high-resistance state, and the pin for controlling the reset of the CPU is set to an invalid level;

after the CPU is started, receiving an operating system, application software, FPGA logic object codes and other logic operation required data of the CPU through an external bus (which can be RS232, RS485, FC, PCIe and the like);

the CPU receives the target code according to a specific file transfer protocol (X-Mode, UDP, TCP and the like), stores the data into a memory after checking the target code, and performs large-small end conversion according to requirements;

the CPU judges the validity of the data according to the format of the target file;

the CPU erases the Flash sector by sector; before erasing, the CPU reads out the content in the sector and compares the content with the target data in the memory; according to the comparison result, if the content of the sector does not need to be changed, skipping the erasing and writing operations of the sector;

after finishing the operation of writing the target code into Flash, the CPU reads back the written data and compares the read data with the data in the memory to ensure the correctness and the integrity of the writing operation;

the FPGA adopts a multi-stage starting mode; if the FPGA cannot find the correct logic object code in the fixed position in the Flash after being electrified, a specific object code is started from the other fixed position, and the object code realizes the management of the FPGA and the CPU on the Flash access authority so as to avoid the problem that the logic cannot be upgraded again after the upgrading fails once.

As shown in fig. 1, an embodiment of the upgrading method of the present invention includes an ethernet bus including a CPU device, an FPGA device, a parallel interface NOR Flash device, a remote computer, and a connection between the remote computer and the CPU device.

In this embodiment, the object codes related to the CPU device and the FPGA device include an operating system, application software, and logic, which are all stored in the Flash device.

The starting process of the CPU and the FPGA in the first embodiment of the invention is shown in FIG. 2, and comprises the following steps:

step 1: after the system is powered on, a DONE signal of the FPGA is pulled low, and the reset signal of the CPU is controlled to be constantly low through the AND gate in the logic loading process of the FPGA;

and 2, step: after the logic loading of the FPGA is successful, pulling up a DONE signal, simultaneously logically controlling one I/O pin to be low until the FPGA finishes all access operations to the Flash, and continuously controlling the reset signal of the CPU to be low by the I/O pin through an AND gate in the access process of the FPGA to the Flash;

and step 3: if the FPGA logic loading fails, the FPGA jumps to a default address to load the backup logic stored in the area;

and 4, step 4: after the FPGA finishes accessing the Flash, setting a Flash read-write control pin (comprising an address and a command signal pin, and a data pin is a high-resistance state) to be in a high-resistance state, and then setting an I/O pin for controlling the reset of a CPU to be in a high level;

and 5: and the CPU reads the object code from the Flash and starts the Flash.

FIG. 3 is a flowchart illustrating the operation of updating each object code stored in Flash after the CPU operating system and the application software are run, and includes the following steps:

step 1: the CPU obtains an upgrading command through an Ethernet interface and receives a target code file to be updated by adopting a UDP protocol;

step 2: the CPU stores the completely received target code file to be updated in the memory; acquiring verification information and a file type from header information of the object code file;

and step 3: the CPU carries out size end conversion on the target code file in the memory according to the size end conversion mark in the received upgrading command;

and 4, step 4: the CPU writes the target code file after the conversion of the big end and the small end into Flash, the target value is compared with the current data of a certain sector before the writing in by taking the sector as a unit, if the target value is different from the current data of the certain sector, the writing operation is executed, and if the target value is the same as the current data of the certain sector, the erasing and writing operation of the sector is skipped;

and 5: after finishing Flash erasing operation, the CPU reads back the data in Flash and compares the data with the target code file in the memory, and sends the result as a written-in named return value to the source end computer through the Ethernet.

FIG. 4 is a schematic diagram of a second embodiment of the present invention, which is different from the first embodiment in that both the CPU and the FPGA are directly connected to Flash, and the CPU and the Flash are indirectly connected through the FPGA; the starting flow of the CPU and the FPGA in the second embodiment is shown in fig. 5, and includes the following steps:

step 1: in the FPGA loading process after the system is powered on, I/O pins of the FPGA are all in a high-resistance state;

step 2: after the logic loading of the FPGA is successful and all access operations to the Flash are finished, the FPGA connects a Flash read-write pin of the CPU with a response pin of the Flash, and resets the CPU through an I/O pin connected with a CPU reset signal;

and step 3: and the CPU reads the object code from the Flash and starts the Flash.

Compared with the first embodiment, the first embodiment occupies least FPGA pins, but the reset control of the CPU is more complicated than the second embodiment.

Claims (2)

1. A remote online upgrade method for an embedded system containing a CPU and an FPGA is characterized in that the CPU and the FPGA use the same Flash to store object codes, the FPGA and the CPU are directly connected with the Flash, the FPGA ensures that the access of the CPU and the CPU to the Flash is not conflicted in time by controlling a reset signal of the CPU, and the method is characterized by comprising the following steps:

step 1: after the system is powered on, a DONE signal of the FPGA is pulled low, and the reset signal of the CPU is controlled to be constantly low through the AND gate in the logic loading process of the FPGA;

step 2: after the logic loading of the FPGA is successful, pulling up a DONE signal, simultaneously logically controlling one I/O pin to be low until the FPGA finishes all access operations to the Flash, and continuously controlling the reset signal of the CPU to be low by the I/O pin through an AND gate in the access process of the FPGA to the Flash;

and step 3: if the FPGA logic loading fails, the FPGA jumps to a default address to load the backup logic stored in the area;

and 4, step 4: after the FPGA finishes accessing the Flash, setting a Flash read-write control pin to be in a high resistance state, and then setting an I/O pin for controlling the reset of the CPU to be in a high level;

and 5: the CPU reads the target code from the Flash and starts the target code;

and 7: the CPU obtains an upgrading command through an Ethernet interface and receives a target code file to be updated by adopting a UDP protocol; the target code file to be updated is an operating system, application software, FPGA logic target codes and other data required by logic operation of the CPU;

and 8: the CPU stores the completely received target code file to be updated in the memory; acquiring verification information and a file type from header information of the object code file;

and step 9: the CPU carries out size end conversion on the target code file in the memory according to the size end conversion mark in the received upgrading command;

step 10: the CPU writes the target code file after the conversion of the big end and the small end into Flash, the target value is compared with the current data of a certain sector before the writing in by taking the sector as a unit, if the target value is different from the current data of the certain sector, the writing operation is executed, and if the target value is the same as the current data of the certain sector, the erasing and writing operation of the sector is skipped;

step 11: and after completing the Flash erasing operation, the CPU reads back the data in the Flash, compares the data with the target code file in the memory, and sends the result as a written named return value to the source end computer through the Ethernet.

2. A remote online upgrade method for an embedded system containing a CPU and an FPGA is characterized in that the CPU and the FPGA use the same Flash storage object code, Flash and the CPU are directly connected with the FPGA, but the CPU is not directly connected with the Flash, and the FPGA logically realizes the signal connection from the CPU to the Flash, and is characterized by comprising the following steps:

step 1: in the FPGA loading process after the system is powered on, I/O pins of the FPGA are all in a high-resistance state;

step 2: after the logic loading of the FPGA is successful and all access operations to the Flash are completed, the FPGA connects a Flash read-write pin of the CPU with a response pin of the Flash, and resets the CPU through an I/O pin connected with a CPU reset signal;

and step 3: the CPU reads the target code from the Flash and starts the target code;

and 4, step 4: the CPU obtains an upgrading command through an Ethernet interface and receives a target code file to be updated by adopting a UDP protocol; the target code file to be updated is an operating system, application software, FPGA logic target codes and other data required by logic operation of the CPU;

and 5: the CPU stores the completely received target code file to be updated in the memory; acquiring verification information and a file type from header information of the object code file;

and 6: the CPU carries out size end conversion on the target code file in the memory according to the size end conversion mark in the received upgrading command;

and 7: the CPU writes the target code file after the conversion of the big end and the small end into Flash, the target value is compared with the current data of a certain sector before the writing in by taking the sector as a unit, if the target value is different from the current data of the certain sector, the writing operation is executed, and if the target value is the same as the current data of the certain sector, the erasing and writing operation of the sector is skipped;

and 8: and after completing the Flash erasing operation, the CPU reads back the data in the Flash, compares the data with the target code file in the memory, and sends the result as a written named return value to the source end computer through the Ethernet.

Images