CN111026222A - Voltage reference source circuit based on switched capacitor - Google Patents
Voltage reference source circuit based on switched capacitor Download PDFInfo
- Publication number
- CN111026222A CN111026222A CN201911316730.1A CN201911316730A CN111026222A CN 111026222 A CN111026222 A CN 111026222A CN 201911316730 A CN201911316730 A CN 201911316730A CN 111026222 A CN111026222 A CN 111026222A
- Authority
- CN
- China
- Prior art keywords
- type mos
- mos transistor
- operational amplifier
- capacitor
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 109
- 101710170230 Antimicrobial peptide 1 Proteins 0.000 claims description 46
- 101710170231 Antimicrobial peptide 2 Proteins 0.000 claims description 35
- 238000005070 sampling Methods 0.000 description 5
- 238000009966 trimming Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a voltage reference source circuit based on a switched capacitor, which comprises a triode junction voltage VBE generation circuit, a switched capacitor circuit and an output buffer stage circuit. The reference voltage circuit structure based on the switched capacitor adopts the switched capacitor amplifier with the input offset compensation circuit to reduce the influence of the input offset voltage of the operational amplifier on the temperature coefficient, and simultaneously, the influence degree of the offset voltage and the gain of the operational amplifier on the overall performance of the circuit is lower than that of the conventional reference, so the design difficulty of the operational amplifier is simplified, and the conventional operational amplifier structure can meet the requirement of high performance.
Description
Technical Field
The invention belongs to the technical field of power supplies, and particularly relates to a voltage reference source circuit based on a switched capacitor.
Background
In recent years, the consumer electronics market continues to expand, the field of integrated circuit power supplies also expands rapidly, and along with the increasingly higher performance requirements of products, the performance requirements of power supply ICs are also increasingly strict. The precision and stability of the reference voltage source serving as a core module of the analog circuit directly determine the precision of the whole system, and the design performance of the reference voltage source needs to be further improved in order to better adapt to the development of analog and digital-analog hybrid circuits. The conventional bandgap reference is greatly affected by the input offset voltage of the operational amplifier. The reference voltage can only be readjusted to an output voltage value with a zero temperature coefficient by a trimming process. Therefore, conventional operational amplifiers have not been able to meet the high performance requirements of the integrated circuit power supply field.
Therefore, providing a voltage reference source circuit based on a switched capacitor to ensure that a conventional operational amplifier meets the requirement of satisfying high performance by a structure is a technical problem that needs to be solved urgently by those skilled in the art.
Disclosure of Invention
In order to solve the above problems, the present invention provides a voltage reference source circuit based on a switched capacitor, which includes a triode junction voltage VBE generation circuit, a switched capacitor circuit and an output buffer circuit;
the triode junction voltage VBE generation circuit comprises a 1PNP type triode Q1, a 2PNP type triode Q2, a 1P type MOS tube M1, a 2P type MOS tube M2, a 3P type MOS tube M3 and a bias current source I1, wherein the base electrode and the collector electrode of the triode Q1 are grounded, and the emitter electrode is connected with the source electrode of the MOS tube M1 and a voltage node V1; the base electrode and the collector electrode of the triode transistor Q2 are grounded, and the emitter electrode is connected with the source electrode of the MOS tube M2 and a voltage node V2; the drain of MOS transistor M1 is connected to the drains of MOS transistor M2 and MOS transistor M3 and to power supply VDD, and the gate is connected to the gates of MOS transistor M2 and M3 and the source of MOS transistor M3; the negative end of the bias current source I1 is grounded GND, and the positive end is connected with the source electrode of the MOS tube M3;
the switch capacitor circuit comprises a 1 st operational amplifier AMP1, a 1 st capacitor C1, a 2 nd capacitor C2, a 4 th N-type MOS tube M4, a 5 th N-type MOS tube M5 and a 6 th N-type MOS tube M6; two ends of the capacitor C1 are respectively connected with the positive input end of the 1 st operational amplifier AMP1, one end of the capacitor C2 is connected with the voltage node V2, the other end of the capacitor C2 is connected with the negative input end of the 1 st operational amplifier AMP1, the positive input end of the 1 st operational amplifier AMP1 is connected with the voltage node V1, the gate of the 4 th N-type MOS transistor M4 is connected to the clock control signal CLK11, the source of the 4 th N-type MOS transistor M4 is connected to the positive input terminal of the 1 st operational amplifier AMP1, the drain of the 4 th N-type MOS transistor M4 is connected to the source of the 5 th N-type MOS transistor M5, the gate of the 5N type MOS transistor M5 is connected to the clock control signal CLK12, the drain of the 5N type MOS transistor M5 is connected to the output Vo of the 1 st operational amplifier AMP1, the gate of the 6N type MOS transistor M6 is connected with the clock control signal CLK11, the source of the 6N type MOS transistor M6 is connected with the negative input end of the 1 st operational amplifier AMP1, and the drain of the 6N type MOS transistor M6 is connected with the output end Vo of the 1 st operational amplifier AMP 1;
the output buffer stage circuit comprises a 2 nd operational amplifier AMP2, a 3 rd capacitor C3, a 4 th capacitor C4, a 7 th N-type MOS tube M7, an 8 th N-type MOS tube M8, a 9 th N-type MOS tube M9 and a 10 th N-type MOS tube M10; the gate of the 7 th N-type MOS transistor M7 is connected with the clock control signal CLK21, the source is connected with the output Vo of the 2 nd operational amplifier AMP2, and the drain is connected with the negative input end of the 2 nd operational amplifier AMP 2; one end of the capacitor C3 is connected with the negative input end of the 2 nd operational amplifier AMP2, and the other end of the capacitor C3 is grounded; one end of the capacitor C4 is connected with the negative input end of the 2 nd operational amplifier AMP2, and the other end of the capacitor C4 is connected with the source electrode of the 8 th N-type MOS transistor M8; the gate of the 8 th N-type MOS transistor M8 is connected to the clock control signal CLK23, and the drain of the 8 th N-type MOS transistor M8 is connected to the positive input terminal of the 2 nd operational amplifier AMP 2; the gate of the 9N type MOS transistor M9 is connected with the clock control signal CLK22, the source of the 9N type MOS transistor M9 is connected with the output end Vo1 of the 2 nd operational amplifier AMP2, and the drain of the 9N type MOS transistor M9 is connected with the source of the 8N type MOS transistor M8; the gate of the 10N type MOS transistor M10 is connected to the clock control signal CLK21, the drain of the 10N type MOS transistor M10 is connected to the output Vo1 of the 2 nd operational amplifier AMP2, and the source of the 10N type MOS transistor M10 is connected to the negative input of the 2 nd operational amplifier AMP 2.
In the switch capacitor circuit, two ends of the capacitor C1 are respectively connected to the positive input terminal of the 1 st operational amplifier AMP1, one end of the capacitor C2 is connected to the voltage node V2, the other end of the capacitor C2 is connected to the negative input terminal of the 1 st operational amplifier AMP1, the positive input terminal of the 1 st operational amplifier AMP1 is connected to the voltage node V1, the gate of the 4 th N-type MOS transistor M4 is connected to the clock control signal CLK11, the drain of the 4 th N-type MOS transistor M4 is connected to the positive input terminal of the 1 st operational amplifier AMP1, the source of the 4 th N-type MOS transistor M4 is connected to the drain of the 5 th N-type MOS transistor M5, the gate of the 5 th N-type MOS transistor M5 is connected to the clock control signal CLK12, the source of the 5 th N-type MOS transistor M5 is connected to the output terminal Vo of the 1 st operational amplifier AMP1, the gate of the 6 th N-type MOS transistor M6 is connected to the clock control signal CLK 5, the drain of the 6 th N-type MOS transistor M6 is connected to the negative, the source of the 6N type MOS transistor M6 is connected to the output Vo of the 1 st operational amplifier AMP 1.
In the output buffer stage circuit, the gate of the 7 th N-type MOS transistor M7 is connected to the clock control signal CLK21, the drain of the 7 th N-type MOS transistor M7 is connected to the output Vo of the 2 nd operational amplifier AMP2, and the source of the 7 th N-type MOS transistor M7 is connected to the negative input terminal of the 2 nd operational amplifier AMP 2; one end of the capacitor C3 is connected with the negative input end of the 2 nd operational amplifier AMP2, and the other end of the capacitor C3 is grounded; one end of the capacitor C4 is connected with the negative input end of the 2 nd operational amplifier AMP2, and the other end of the capacitor C4 is connected with the drain electrode of the 8 th N-type MOS transistor M8; the gate of the 8 th N-type MOS transistor M8 is connected to the clock control signal CLK23, and the source of the 8 th N-type MOS transistor M8 is connected to the positive input terminal of the 2 nd operational amplifier AMP 2; the gate of the 9N type MOS transistor M9 is connected to the clock control signal CLK22, the drain 2 of the 9N type MOS transistor M9 is connected to the output end Vo1 of the 2 nd operational amplifier AMP2, the source of the 9N type MOS transistor M9 is connected to the drain of the 8N type MOS transistor M8; the gate of the 10N type MOS transistor M10 is connected to the clock control signal CLK21, the source of the 10N type MOS transistor M10 is connected to the output Vo1 of the 2 nd operational amplifier AMP2, and the drain of the 10N type MOS transistor M10 is connected to the negative input of the 2 nd operational amplifier AMP 2.
The capacitor C2 network comprises capacitors C21-C26, switches S11-S15 and switches S21-S25; two ends of the capacitor C21 are respectively connected with a port V-and a port V2, one ends of the capacitors C22-C26 are connected with a V-, and the other ends are respectively connected with nodes n 1-n 5; one end of each of the switches S11-S15 is connected with V2, and the other end is connected with nodes n 1-n 5 respectively; one end of each of the switches S21-S25 is grounded, and the other end is connected with the nodes n 1-n 5 respectively.
Further, the port V-is the negative input terminal of the 1 st operational amplifier AMP1, and the port V2 is connected to the voltage node V2.
The invention has the beneficial effects that: the reference voltage circuit structure based on the switched capacitor adopts the switched capacitor amplifier with the input offset compensation circuit to reduce the influence of the input offset voltage of the operational amplifier on the temperature coefficient, and simultaneously, the influence degree of the offset voltage and the gain of the operational amplifier on the overall performance of the circuit is lower than that of the conventional reference, so the design difficulty of the operational amplifier is simplified, and the conventional operational amplifier structure can meet the requirement of high performance.
Drawings
FIG. 1: a voltage reference source circuit based on a switched capacitor;
fig. 2 a-2 b: an equivalent circuit;
FIG. 3: an output buffer stage (buffer) circuit;
FIG. 4: controlling the signal timing by a clock;
FIG. 5: a trimming network of a capacitor C2;
Detailed Description
The invention will be further explained with reference to the drawings and the embodiments.
Example 1
As shown in FIG. 1, the present invention provides a switched capacitor based voltage reference source circuit, which comprises a triode junction voltage VBE generation circuit, a switched capacitor circuit and an output buffer stage circuit, wherein the triode junction voltage VBE generation circuit comprises a 1PNP type triode Q1, a 2PNP triode Q2, a 1P type MOS M1, a 2P type MOS M2, a 3P type MOS M3 and a bias current source I1. The connection mode is that the base electrode and the collector electrode of the triode transistor Q1 are grounded, and the emitter electrode is connected with the source electrode of the MOS tube M1 and the voltage node V1; the base electrode and the collector electrode of the triode transistor Q2 are grounded, and the emitter electrode is connected with the source electrode of the MOS tube M2 and a voltage node V2; the drain of MOS transistor M1 is connected to the drains of MOS transistor M2 and MOS transistor M3 and to power supply VDD, and the gate is connected to the gates of MOS transistor M2 and M3 and the source of MOS transistor M3; the negative end of the bias current source I1 is connected to the ground GND, and the positive end is connected to the source of the MOS transistor M3.
The switch capacitor circuit comprises a 1 st operational amplifier AMP1, a 1 st capacitor C1, a 2 nd capacitor C2, a 4 th N-type MOS tube M4, a 5 th N-type MOS tube M5 and a 6 th N-type MOS tube M6; two ends of the capacitor C1 are respectively connected with the positive input end of the 1 st operational amplifier AMP1, one end of the capacitor C2 is connected with the voltage node V2, the other end of the capacitor C2 is connected with the negative input end of the 1 st operational amplifier AMP1, the positive input end of the 1 st operational amplifier AMP1 is connected with the voltage node V1, the gate of the 4 th N-type MOS transistor M4 is connected to the clock control signal CLK11, the source of the 4 th N-type MOS transistor M4 is connected to the positive input terminal of the 1 st operational amplifier AMP1, the drain of the 4 th N-type MOS transistor M4 is connected to the source of the 5 th N-type MOS transistor M5, the gate of the 5N type MOS transistor M5 is connected to the clock control signal CLK12, the drain of the 5N type MOS transistor M5 is connected to the output Vo of the 1 st operational amplifier AMP1, the gate of the 6N type MOS transistor M6 is connected with the clock control signal CLK11, the source of the 6N type MOS transistor M6 is connected with the negative input end of the 1 st operational amplifier AMP1, and the drain of the 6N type MOS transistor M6 is connected with the output end Vo of the 1 st operational amplifier AMP 1;
the output buffer stage circuit comprises a 2 nd operational amplifier AMP2, a 3 rd capacitor C3, a 4 th capacitor C4, a 7 th N-type MOS tube M7, an 8 th N-type MOS tube M8, a 9 th N-type MOS tube M9 and a 10 th N-type MOS tube M10; the gate of the 7 th N-type MOS transistor M7 is connected with the clock control signal CLK21, the source is connected with the output Vo of the 2 nd operational amplifier AMP2, and the drain is connected with the negative input end of the 2 nd operational amplifier AMP 2; one end of the capacitor C3 is connected with the negative input end of the 2 nd operational amplifier AMP2, and the other end of the capacitor C3 is grounded; one end of the capacitor C4 is connected with the negative input end of the 2 nd operational amplifier AMP2, and the other end of the capacitor C4 is connected with the source electrode of the 8 th N-type MOS transistor M8; the gate of the 8 th N-type MOS transistor M8 is connected to the clock control signal CLK23, and the drain of the 8 th N-type MOS transistor M8 is connected to the positive input terminal of the 2 nd operational amplifier AMP 2; the gate of the 9N type MOS transistor M9 is connected with the clock control signal CLK22, the source of the 9N type MOS transistor M9 is connected with the output end Vo1 of the 2 nd operational amplifier AMP2, and the drain of the 9N type MOS transistor M9 is connected with the source of the 8N type MOS transistor M8; the gate of the 10N type MOS transistor M10 is connected to the clock control signal CLK21, the drain of the 10N type MOS transistor M10 is connected to the output Vo1 of the 2 nd operational amplifier AMP2, and the source of the 10N type MOS transistor M10 is connected to the negative input of the 2 nd operational amplifier AMP 2. The branch current of the MOS transistor M2 and the branch current of the MOS transistor M1 mirror the branch current of the MOS transistor M3 mentioned above, the area of the PNP transistor Q2 is n times the area of the PNP transistor Q1, the voltage generated by the emitter V1 of the triode transistor Q1 is VBE1, and the voltage generated by the emitter V2 of the triode transistor Q2 is VBE 2.
The switched capacitor circuit includes an operational amplifier AMP1, a switch composed of N-type MOS transistors M4, M5, and M6, and capacitors C1 and C2. When the clock signal CLK11 is high and CLK12 is low, the circuit is equivalent to FIG. 2 (a). The timing of the clock control signals involved in the circuit is shown in figure 4. At node A: the voltage V2 of V1 is equal, the negative side charge of the 1 st operational amplifier AMP1 is 0,
the existence of the offset voltage of the 1 st operational amplifier AMP1 is ignored when the V2 charges the C2, and because the two ends of the capacitor C1 are respectively connected with the positive and negative input ends of the 1 st operational amplifier AMP1, the input end of the 1 st operational amplifier AMP1 also charges the capacitor C1, and the voltage of the two ends of the C1 is actually the offset voltage of the 1 st operational amplifier AMP 1.
When the clock signal CLK11 is low and CLK12 is high, the circuit is equivalent to FIG. 2(B), at node B:
C2×(VBE2-VBE1)+C1×(Vo-VBE1)＝0
as shown in fig. 2(b), C1 is disconnected, the charge of C1 is transferred to C2, C2 stores the offset voltage of the positive and negative inputs of the 1 st operational amplifier AMP1, and C2 adds the charge of C2 on the basis of the offset voltage, thereby eliminating the offset voltage of the two inputs of the 1 st operational amplifier AMP 1.
The capacitor C2 in the circuit is a capacitor network that can be adjusted by trimming to precisely adjust the temperature coefficient of the reference voltage, and the specific circuit is shown in fig. 5, in which the values of the capacitors C22-C26 are designed to be20、21、22、23、24、25When the branch switch S11-S15 where any capacitor is located is closed and the switches S21-S25 are opened, the capacitor is connected in parallel with the capacitor C21 and coacts with the capacitor C21 to finely adjust the value of the capacitor C2 network; when the switches S11-S15 of the branch in which any capacitor is located are turned off and the switches S21-S25 are turned off, the capacitor is not incorporated into the network of capacitors C2.
The third part is an output buffer stage circuit, which is actually a sample-and-hold circuit, and mainly comprises a switch formed by N-type MOS tubes M7, M8, M9 and M10, an operational amplifier AMP2, a sampling capacitor C3 and a capacitor C4. The function of this part of the circuit is to convert a discontinuous voltage reference source into a continuous voltage reference source. The working principle is as follows: when the clock control signal CLK11 is high, i.e., the output voltage of the output terminal of the operational amplifier AMP1 is the required reference voltage VREF1, the clock CLK21 is high, the capacitor C3 is a sampling capacitor, and the voltage of the negative input terminal of the operational amplifier AMP2 is equal to the voltage of the output terminal Vo1 and VREF 1. When the clock control signal CLK21 is low, CLK22 is high, and CLK23 is low, the voltage at the output Vo1 maintains the previous sampling voltage VREF 1. The continuous stable reference voltage value VREF can be obtained at the output Vo1 of the operational amplifier AMP 2.
The transistor junction voltage VBE generation circuit generates base emitter voltages VBE1 and VBE2 of the transistors at the emitters of the transistors Q1 and Q2, respectively. The switch capacitance circuit controls the on and off of the switch through a clock signal to superpose VBE with positive temperature coefficient and delta VBE (VBE2-VBE1) with negative temperature coefficient to generate a reference voltage with relative temperature coefficient of 0. The output buffer stage circuit can convert discontinuous reference voltage output by the switched capacitor circuit into continuous reference voltage, so that the requirement of high performance can be met by adopting a conventional operational amplifier structure.
Example 2
In embodiment 1, two ends of the capacitor C1 are respectively connected to the positive input terminal of the 1 st operational amplifier AMP1, one end of the capacitor C2 is connected to the voltage node V2, the other end of the capacitor C2 is connected to the negative input terminal of the 1 st operational amplifier AMP1, the positive input terminal of the 1 st operational amplifier AMP1 is connected to the voltage node V1, the gate of the 4 th N-type MOS transistor M4 is connected to the clock control signal CLK11, the drain of the 4 th N-type MOS transistor M4 is connected to the positive input terminal of the 1 st operational amplifier AMP1, the source of the 4 th N-type MOS transistor M4 is connected to the drain of the 5 th N-type MOS transistor M5, the gate of the 5N type MOS transistor M5 is connected to the clock control signal CLK12, the source of the 5N type MOS transistor M5 is connected to the output Vo of the 1 st operational amplifier AMP1, the gate of the 6N type MOS transistor M6 is connected to the clock control signal CLK11, the drain of the 6N type MOS transistor M6 is connected to the negative input terminal of the 1 st operational amplifier AMP1, and the source of the 6N type MOS transistor M6 is connected to the output Vo of the 1 st operational amplifier AMP 1.
In the output buffer stage circuit, the gate of the 7N-type MOS transistor M7 is connected to the clock control signal CLK21, the drain of the 7N-type MOS transistor M7 is connected to the output Vo of the 2 nd operational amplifier AMP2, and the source of the 7N-type MOS transistor M7 is connected to the negative input terminal of the 2 nd operational amplifier AMP 2; one end of the capacitor C3 is connected with the negative input end of the 2 nd operational amplifier AMP2, and the other end of the capacitor C3 is grounded; one end of the capacitor C4 is connected with the negative input end of the 2 nd operational amplifier AMP2, and the other end of the capacitor C4 is connected with the drain electrode of the 8 th N-type MOS transistor M8; the gate of the 8 th N-type MOS transistor M8 is connected to the clock control signal CLK23, and the source of the 8 th N-type MOS transistor M8 is connected to the positive input terminal of the 2 nd operational amplifier AMP 2; the gate of the 9N type MOS transistor M9 is connected to the clock control signal CLK22, the drain 2 of the 9N type MOS transistor M9 is connected to the output end Vo1 of the 2 nd operational amplifier AMP2, the source of the 9N type MOS transistor M9 is connected to the drain of the 8N type MOS transistor M8; the gate of the 10N type MOS transistor M10 is connected to the clock control signal CLK21, the source of the 10N type MOS transistor M10 is connected to the output Vo1 of the 2 nd operational amplifier AMP2, and the drain of the 10N type MOS transistor M10 is connected to the negative input of the 2 nd operational amplifier AMP 2.
The above embodiments can be applied to a general a/D converter circuit, which only requires a stable output reference voltage during a sampling time due to the periodic sampling of the reference voltage by the sample-and-hold circuit, but requires a continuous stable output in other circuits requiring a continuous output of the reference voltage. The invention ensures the continuity of the output reference voltage by adding a first-stage output buffer stage circuit, and realizes that the conventional operational amplifier structure meets the requirement of high performance.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (5)
1. A voltage reference source circuit based on a switched capacitor comprises a triode junction voltage VBE generation circuit, a switched capacitor circuit and an output buffer stage circuit, and is characterized in that:
the triode junction voltage VBE generation circuit comprises a 1PNP type triode Q1, a 2PNP type triode Q2, a 1P type MOS tube M1, a 2P type MOS tube M2, a 3P type MOS tube M3 and a bias current source I1, wherein the base electrode and the collector electrode of the triode Q1 are grounded, and the emitter electrode is connected with the source electrode of the MOS tube M1 and a voltage node V1; the base electrode and the collector electrode of the triode transistor Q2 are grounded, and the emitter electrode is connected with the source electrode of the MOS tube M2 and a voltage node V2; the drain of MOS transistor M1 is connected to the drains of MOS transistor M2 and MOS transistor M3 and to power supply VDD, and the gate is connected to the gates of MOS transistor M2 and M3 and the source of MOS transistor M3; the negative end of the bias current source I1 is grounded GND, and the positive end is connected with the source electrode of the MOS tube M3;
the switch capacitor circuit comprises a 1 st operational amplifier AMP1, a 1 st capacitor C1, a 2 nd capacitor C2, a 4 th N-type MOS tube M4, a 5 th N-type MOS tube M5 and a 6 th N-type MOS tube M6; two ends of the capacitor C1 are respectively connected with the positive input end of the 1 st operational amplifier AMP1, one end of the capacitor C2 is connected with the voltage node V2, the other end of the capacitor C2 is connected with the negative input end of the 1 st operational amplifier AMP1, the positive input end of the 1 st operational amplifier AMP1 is connected with the voltage node V1, the gate of the 4 th N-type MOS transistor M4 is connected to the clock control signal CLK11, the source of the 4 th N-type MOS transistor M4 is connected to the positive input terminal of the 1 st operational amplifier AMP1, the drain of the 4 th N-type MOS transistor M4 is connected to the source of the 5 th N-type MOS transistor M5, the gate of the 5N type MOS transistor M5 is connected to the clock control signal CLK12, the drain of the 5N type MOS transistor M5 is connected to the output Vo of the 1 st operational amplifier AMP1, the gate of the 6N type MOS transistor M6 is connected with the clock control signal CLK11, the source of the 6N type MOS transistor M6 is connected with the negative input end of the 1 st operational amplifier AMP1, and the drain of the 6N type MOS transistor M6 is connected with the output end Vo of the 1 st operational amplifier AMP 1;
the output buffer stage circuit comprises a 2 nd operational amplifier AMP2, a 3 rd capacitor C3, a 4 th capacitor C4, a 7 th N-type MOS tube M7, an 8 th N-type MOS tube M8, a 9 th N-type MOS tube M9 and a 10 th N-type MOS tube M10; the gate of the 7 th N-type MOS transistor M7 is connected with the clock control signal CLK21, the source is connected with the output Vo of the 2 nd operational amplifier AMP2, and the drain is connected with the negative input end of the 2 nd operational amplifier AMP 2; one end of the capacitor C3 is connected with the negative input end of the 2 nd operational amplifier AMP2, and the other end of the capacitor C3 is grounded; one end of the capacitor C4 is connected with the negative input end of the 2 nd operational amplifier AMP2, and the other end of the capacitor C4 is connected with the source electrode of the 8 th N-type MOS transistor M8; the gate of the 8 th N-type MOS transistor M8 is connected to the clock control signal CLK23, and the drain of the 8 th N-type MOS transistor M8 is connected to the positive input terminal of the 2 nd operational amplifier AMP 2; the gate of the 9N type MOS transistor M9 is connected with the clock control signal CLK22, the source of the 9N type MOS transistor M9 is connected with the output end Vo1 of the 2 nd operational amplifier AMP2, and the drain of the 9N type MOS transistor M9 is connected with the source of the 8N type MOS transistor M8; the gate of the 10N type MOS transistor M10 is connected to the clock control signal CLK21, the drain of the 10N type MOS transistor M10 is connected to the output Vo1 of the 2 nd operational amplifier AMP2, and the source of the 10N type MOS transistor M10 is connected to the negative input of the 2 nd operational amplifier AMP 2.
2. The switched capacitor-based voltage reference source circuit as claimed in claim 1, wherein in the switched capacitor circuit, two ends of the capacitor C1 are respectively connected to the positive input terminal of the 1 st operational amplifier AMP1, one end of the capacitor C2 is connected to the voltage node V2, the other end of the capacitor C2 is connected to the negative input terminal of the 1 st operational amplifier AMP1, the positive input terminal of the 1 st operational amplifier AMP1 is connected to the voltage node V1, the gate of the 4 th N-type MOS transistor M4 is connected to the clock control signal CLK11, the drain of the 4 th N-type MOS transistor M4 is connected to the positive input terminal of the 1 st operational amplifier AMP1, the source of the 4 th N-type MOS transistor M4 is connected to the drain of the 5 th N-type MOS transistor M5, the gate of the 5N-type MOS transistor M5 is connected to the clock control signal CLK 8, the source of the 6865 th N-type MOS transistor M6 is connected to the output terminal Vo1, and the gate of the clock control signal CLK11 of the 5 th N-type MOS transistor M6, the drain of the 6N type MOS transistor M6 is connected to the negative input terminal of the 1 st operational amplifier AMP1, and the source of the 6N type MOS transistor M6 is connected to the output Vo of the 1 st operational amplifier AMP 1.
3. The switched capacitor-based voltage reference source circuit as claimed in claim 1, wherein in the output buffer stage circuit, the gate of the 7N-type MOS transistor M7 is connected to the clock control signal CLK21, the drain of the 7N-type MOS transistor M7 is connected to the output Vo of the 2 nd operational amplifier AMP2, and the source of the 7N-type MOS transistor M7 is connected to the negative input terminal of the 2 nd operational amplifier AMP 2; one end of the capacitor C3 is connected with the negative input end of the 2 nd operational amplifier AMP2, and the other end of the capacitor C3 is grounded; one end of the capacitor C4 is connected with the negative input end of the 2 nd operational amplifier AMP2, and the other end of the capacitor C4 is connected with the drain electrode of the 8 th N-type MOS transistor M8; the gate of the 8 th N-type MOS transistor M8 is connected to the clock control signal CLK23, and the source of the 8 th N-type MOS transistor M8 is connected to the positive input terminal of the 2 nd operational amplifier AMP 2; the gate of the 9N type MOS transistor M9 is connected to the clock control signal CLK22, the drain 2 of the 9N type MOS transistor M9 is connected to the output end Vo1 of the 2 nd operational amplifier AMP2, the source of the 9N type MOS transistor M9 is connected to the drain of the 8N type MOS transistor M8; the gate of the 10N type MOS transistor M10 is connected to the clock control signal CLK21, the source of the 10N type MOS transistor M10 is connected to the output Vo1 of the 2 nd operational amplifier AMP2, and the drain of the 10N type MOS transistor M10 is connected to the negative input of the 2 nd operational amplifier AMP 2.
4. The switched capacitor-based voltage reference source circuit as claimed in any one of claims 1-2, wherein the capacitor C2 network comprises capacitors C21-C26, switches S11-S15, S21-S25; two ends of the capacitor C21 are respectively connected with a port V-and a port V2, one ends of the capacitors C22-C26 are connected with a V-, and the other ends are respectively connected with nodes n 1-n 5; one end of each of the switches S11-S15 is connected with V2, and the other end is connected with nodes n 1-n 5 respectively; one end of each of the switches S21-S25 is grounded, and the other end is connected with the nodes n 1-n 5 respectively.
5. The switched-capacitor based voltage reference source circuit as claimed in claim 4, wherein the port V-is a negative input of the 1 st operational amplifier AMP1, and the port V2 is a voltage node V2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911316730.1A CN111026222A (en) | 2019-12-19 | 2019-12-19 | Voltage reference source circuit based on switched capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911316730.1A CN111026222A (en) | 2019-12-19 | 2019-12-19 | Voltage reference source circuit based on switched capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111026222A true CN111026222A (en) | 2020-04-17 |
Family
ID=70209974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911316730.1A Pending CN111026222A (en) | 2019-12-19 | 2019-12-19 | Voltage reference source circuit based on switched capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111026222A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115268540A (en) * | 2021-04-29 | 2022-11-01 | 圣邦微电子（北京）股份有限公司 | Band-gap reference circuit with sampling and holding functions |
| WO2023231828A1 (en) * | 2022-06-02 | 2023-12-07 | 芯海科技（深圳）股份有限公司 | Bandgap reference voltage circuit, integrated circuit, and electronic device |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11122055A (en) * | 1997-10-14 | 1999-04-30 | Nec Corp | Operational amplifier |
| KR20000066565A (en) * | 1999-04-19 | 2000-11-15 | 김영환 | Voltage-controlled oscillator improved in phase noise |
| CN1856940A (en) * | 2003-09-26 | 2006-11-01 | 斯盖沃克斯解决方案有限公司 | Envelope error extraction in IF/RF feedback loops |
| US20090189590A1 (en) * | 2008-01-25 | 2009-07-30 | Elpida Memory, Inc. | Band-gap reference voltage source circuit |
| CN104111683A (en) * | 2014-06-27 | 2014-10-22 | 成都嘉纳海威科技有限责任公司 | Reference source with automatic operational amplifier offset voltage eliminating function |
| CN204065894U (en) * | 2014-07-14 | 2014-12-31 | 深圳市科创达微电子有限公司 | The band-gap reference circuit of switch control rule low maladjustment voltage |
| US20150063419A1 (en) * | 2013-09-02 | 2015-03-05 | Renesas Electronics Corporation | Signal generation circuit and temperature sensor |
| CN107817860A (en) * | 2016-09-14 | 2018-03-20 | 中国科学院微电子研究所 | Low-voltage bandgap reference circuit and voltage generating circuit |
| CN210983126U (en) * | 2019-12-19 | 2020-07-10 | 西安航天民芯科技有限公司 | Voltage reference source circuit based on switched capacitor |
-
2019
- 2019-12-19 CN CN201911316730.1A patent/CN111026222A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11122055A (en) * | 1997-10-14 | 1999-04-30 | Nec Corp | Operational amplifier |
| KR20000066565A (en) * | 1999-04-19 | 2000-11-15 | 김영환 | Voltage-controlled oscillator improved in phase noise |
| CN1856940A (en) * | 2003-09-26 | 2006-11-01 | 斯盖沃克斯解决方案有限公司 | Envelope error extraction in IF/RF feedback loops |
| US20090189590A1 (en) * | 2008-01-25 | 2009-07-30 | Elpida Memory, Inc. | Band-gap reference voltage source circuit |
| US20150063419A1 (en) * | 2013-09-02 | 2015-03-05 | Renesas Electronics Corporation | Signal generation circuit and temperature sensor |
| CN104111683A (en) * | 2014-06-27 | 2014-10-22 | 成都嘉纳海威科技有限责任公司 | Reference source with automatic operational amplifier offset voltage eliminating function |
| CN204065894U (en) * | 2014-07-14 | 2014-12-31 | 深圳市科创达微电子有限公司 | The band-gap reference circuit of switch control rule low maladjustment voltage |
| CN107817860A (en) * | 2016-09-14 | 2018-03-20 | 中国科学院微电子研究所 | Low-voltage bandgap reference circuit and voltage generating circuit |
| CN210983126U (en) * | 2019-12-19 | 2020-07-10 | 西安航天民芯科技有限公司 | Voltage reference source circuit based on switched capacitor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115268540A (en) * | 2021-04-29 | 2022-11-01 | 圣邦微电子（北京）股份有限公司 | Band-gap reference circuit with sampling and holding functions |
| CN115268540B (en) * | 2021-04-29 | 2023-08-11 | 圣邦微电子（北京）股份有限公司 | Band gap reference circuit with sampling and holding functions |
| WO2023231828A1 (en) * | 2022-06-02 | 2023-12-07 | 芯海科技（深圳）股份有限公司 | Bandgap reference voltage circuit, integrated circuit, and electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9285822B2 (en) | Small-circuit-scale reference voltage generating circuit | |
| CN201191822Y (en) | Differential reference voltage source circuit suitable for A/D converter | |
| CN108227819B (en) | Low-voltage band-gap reference circuit with direct-current offset calibration function | |
| CN101561689B (en) | Low voltage CMOS current source | |
| CN109088537B (en) | Charge pump | |
| CN210983126U (en) | Voltage reference source circuit based on switched capacitor | |
| US20200278708A1 (en) | Offset corrected bandgap reference and temperature sensor | |
| CN111026222A (en) | Voltage reference source circuit based on switched capacitor | |
| US7477087B2 (en) | Switch-capacitor techniques for level-shifting | |
| CN104090619A (en) | Digital-analog hybrid circuit reference source with high work stability | |
| CN104076860A (en) | Band-gap reference source for digital-analog hybrid circuit | |
| WO2021196233A1 (en) | Low-dropout linear voltage stabilizing circuit | |
| CN101694963A (en) | High-precision low-voltage voltage/current switching circuit | |
| CN201097250Y (en) | High-power restraint standard source with gap | |
| CN104076857A (en) | Improved mixed-signal circuit | |
| CN110083193A (en) | Bandgap Reference Voltage Generation Circuit | |
| CN101964648B (en) | High-threshold value voltage comparison circuit consisting of high-precision low-voltage comparator | |
| CN115118237A (en) | Fully differential operational amplifier and fully differential operational amplifier circuit | |
| CN104076858A (en) | Improved mixed-signal chip | |
| CN104090620A (en) | High-bandwidth digital-analog hybrid circuit reference source | |
| CN104090617A (en) | Low-dropout linear regulator of improved digital-analog hybrid circuit | |
| CN117060890A (en) | RC relaxation oscillator | |
| CN203950239U (en) | The band gap reference of Digital Analog Hybrid Circuits | |
| CN113885641A (en) | High-low temperature compensation circuit for band gap reference source | |
| CN203950237U (en) | Modified form digital-to-analogue hybrid chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |