CN110995187A - Low-voltage broadband linear equalizer circuit applied to high-speed serial interface - Google Patents
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Abstract
The invention belongs to the technical field of integrated circuits, and particularly relates to a low-voltage broadband linear equalizer circuit applied to a high-speed serial interface, which is used for carrying out equalization processing on an input signal of a receiving end. The circuit adopts a differential structure, and comprises a differential signal input port INP, a differential signal input port INN, a main signal branch, a bandwidth expansion branch, a load shunt branch, a bias branch, a differential signal output port OUTP and a differential signal output port OUTN which are connected in sequence. The main signal branch circuit adopts an active amplifier structure with a source end resistor and capacitor degeneration structure to complete signal equalization processing. The bandwidth expansion branch adopts an active inductance structure, inductance peaking is generated at the output end, and the bandwidth expansion branch is connected with the main signal branch in parallel to effectively expand the bandwidth of the equalization circuit. The load shunt branch adopts a current mirror structure, and shunts the bias current generated by the bandwidth expansion branch, so that the overlarge voltage drop of the load resistor is avoided, and the design requirement under the low power supply voltage is met.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a low-voltage broadband linear equalizer circuit applied to a high-speed serial interface.
Background
The transmitting and receiving channels of high-speed serial data introduce many non-ideal factors in the signal transmission process, such as skin effect and dielectric loss inherent in transmission media such as printed circuit board wiring, backplane wiring and cables. The effects of these non-idealities deteriorate as the serial data rate increases, causing the channel to exhibit a low-pass characteristic in the frequency domain, attenuating high frequency portions of the serial data. In the time domain, Inter-Symbol-Interference (ISI) appears to degrade the performance of the received serial data eye and increase the Bit Error Rate (BER) of the received data. In the same channel, the higher the speed of transmitting serial data is, the greater the high-frequency attenuation is, and the more serious the intersymbol interference is; for serial signals of the same rate, the longer the channel is passed or the worse the channel characteristics are, the greater the high frequency attenuation is, and the more serious the intersymbol interference is.
The linear equalizer circuit is one of important means for solving intersymbol Interference at a high-speed serial data receiving end, and aims at different attenuation of a high-frequency part and a low-frequency part in a received signal caused by channel low-pass characteristics, the high-frequency part of an input signal is amplified or the low-frequency part of the input signal is attenuated, high-frequency attenuation introduced by a channel is compensated, the influence of intersymbol Interference (ISI) is reduced, and the Bit Error Rate (BER) is reduced.
The conventional linear equalizer circuit generally adopts a cml (current Mode logic) structure having a source end negative feedback resistor and a source end negative feedback capacitor, and compensates for high frequency attenuation introduced by a channel by additionally introducing a pair of zero and pole. With the continuous improvement of the transmission rate of serial data, the bandwidth design requirement of the linear equalizer circuit is continuously improved, and meanwhile, the gain requirement for high-frequency compensation of the input signal of the receiving end is also continuously improved, and the compromise between the gain and the bandwidth becomes more and more difficult. In addition, as advanced manufacturing processes are developed, the supply voltage provided by the processes is continuously reduced. And entering a deep submicron process, wherein the power supply voltage is mostly lower than 1V and 20 nm, the power supply voltage is lower than 0.9V, and the design margin is further limited by the requirement of low power supply voltage. Therefore, the current linear equalizer circuit applied to the high-speed serial interface is faced with the design requirement of realizing high bandwidth under low power supply voltage.
Disclosure of Invention
The invention aims to provide a low-voltage broadband linear equalizer circuit applied to a high-speed serial interface, which can realize the equalization compensation of an input signal in a wider bandwidth range under the design requirement of low power supply voltage, thereby achieving the purposes of reducing intersymbol interference jitter (ISI jitter) and reducing the Bit Error Rate (BER).
In order to achieve the above object, the present invention adopts a technical solution that is a low-voltage broadband linear equalizer circuit applied to a high-speed serial interface, and is configured to provide equalization compensation for a differential signal input by a receiving end of the high-speed serial interface, where the low-voltage broadband linear equalizer circuit includes a differential signal input port INP, a differential signal input port INN, a main signal branch, a bandwidth expansion branch, a load splitting branch, a bias branch, a differential signal output port OUTP, and a differential signal output port OUTN;
the differential signal input port INP and the differential signal input port INN are used for input of the differential signal;
the main signal branch circuit performs equalization processing on the differential signal by utilizing negative feedback of a source end negative feedback resistor and negative feedback of a source end negative feedback capacitor;
the bandwidth expansion branch utilizes an inductance peaking principle and adopts a differential active inductance structure to form inductive impedance at the differential signal output port OUTP and the differential signal output port OUTN so as to achieve the purpose of expanding the bandwidth of the equalizer;
the load shunt branch adopts a current mirror structure to shunt part of current of the bandwidth expansion branch, so that overlarge voltage drop of a load resistor of the bandwidth expansion branch is avoided;
the bias branch circuit provides a bias voltage VBN for transistors forming the current source in the main signal branch circuit, the bandwidth expansion branch circuit and the load shunt branch circuit;
the differential signal output port OUTP and the differential signal output port OUTN are used for outputting the differential signal after being equalized by the main signal branch.
Further, the main signal branch comprises an input differential pair transistor NM1, an input differential pair transistor NM2, a load resistor R1, a load resistor R2, and a source-end adjustable negative feedback resistor Rs, wherein the source-end adjustable negative feedback resistor Rs is the source-end negative feedback resistor; the power supply further comprises a transistor NM7 and a transistor NM8 which form the current source, and further comprises a transistor PM1 and a transistor PM2 which form the source end negative feedback capacitor;
the gate terminal of the input differential pair transistor NM1 is connected to the differential signal input port INP, the drain terminal is connected to the differential signal output port OUTN, and the source terminal is connected to the drain terminal of the transistor NM7 that constitutes the current source;
the gate terminal of the input differential pair transistor NM2 is connected to the differential signal input port INN, the drain terminal is connected to the differential signal output port OUTP, and the source terminal is connected to the drain terminal of the transistor NM8 constituting the current source;
one end of the load resistor R1 is connected with the differential signal output port OUTN, and the other end is connected with a first POWER supply 1;
one end of the load resistor R2 is connected with the differential signal output port OUTP, and the other end of the load resistor R2 is connected with a first POWER supply POWER 1;
the source end adjustable negative feedback resistor Rs is connected between the source end of the input differential pair transistor NM1 and the source end of the input differential pair transistor NM2 in a bridge mode;
the gate terminal of the transistor PM1 is connected with the source terminal of the input differential pair transistor NM1, and the source terminal and the drain terminal of the transistor PM1 are both connected with a second POWER supply 2;
the gate terminal of the transistor PM2 is connected with the source terminal of the input differential pair transistor NM2, and the source terminal and the drain terminal of the transistor PM2 are both connected with a POWER supply second POWER supply 2;
the drain terminal of the transistor NM7 is connected to the source terminal of the input differential pair transistor NM1, the gate terminal is connected to the bias voltage VBN provided by the bias branch, and the source terminal is connected to ground;
the drain terminal of the transistor NM8 is connected to the source terminal of the input differential pair transistor NM2, the gate terminal is connected to the bias voltage VBN provided by the bias branch, and the source terminal is connected to ground.
Further, the bandwidth extension branch comprises a transistor NM3, a transistor NM4, a transistor NM9 constituting the current source, a resistor R3, a resistor R4, a transistor NM5 and a transistor NM6 constituting a capacitor;
the drain terminal of the transistor NM3 is connected to the differential signal output port OUTN, the gate terminal is connected to the gate terminal of the transistor NM5, and the source terminal is connected to the drain terminal of the transistor NM 9;
the drain terminal of the transistor NM4 is connected to the differential signal output port OUTP, the gate terminal is connected to the gate terminal of the transistor NM6, and the source terminal is connected to the drain terminal of the transistor NM 9;
one end of the resistor R3 is connected to the differential signal output port OUTN, and the other end is connected to the gate terminal of the transistor NM 5;
one end of the resistor R4 is connected to the differential signal output port OUTP, and the other end is connected to the gate terminal of the transistor NM 6;
the grid end of the transistor NM5 is connected with the grid end of the transistor NM3, and the source end and the drain end are both connected with the ground;
the grid end of the transistor NM6 is connected with the grid end of the transistor NM4, and the source end and the drain end are both connected with the ground;
the drain terminal of the transistor NM9 is connected to the source terminal of the transistor NM3 and the source terminal of the transistor NM4, the gate terminal is connected to the bias voltage VBN provided by the bias branch, and the source terminal is connected to ground.
Further, the load shunt branch adopts a current mirror structure, and comprises a transistor PM3, a transistor PM4, a transistor PM5 and a transistor NM10, wherein the transistors form a current drain;
the drain terminal of the transistor PM3 is connected to the differential signal output port OUTN, the gate terminal is connected to the gate terminal of the transistor PM5, and the source terminal is connected to the first POWER supply 1;
the drain terminal of the transistor PM4 is connected to the differential signal output port OUTP, the gate terminal is connected to the gate terminal of the transistor PM5, and the source terminal is connected to the first POWER supply 1;
the gate terminal and the drain terminal of the transistor PM5 are connected with the drain terminal of the transistor NM10, and the source terminal of the transistor PM5 is connected with a first POWER supply 1;
the drain terminal of the transistor NM10 is connected to the source terminal and the drain terminal of the transistor PM5, the gate terminal is connected to the bias voltage VBN provided by the bias branch, and the source terminal is connected to ground.
Further, the bias branch comprises a bias current source IBIAS and a diode-connected transistor NM 11;
the drain terminal and the gate terminal of the transistor NM11 are connected to the bias current source IBIAS and provide the bias voltage VBN of the whole equalization circuit, and the source terminal of the transistor NM11 is grounded;
one end of the current source IBIAS is connected to the drain terminal and the gate terminal of the transistor NM11, and the other end is connected to a third POWER supply 3.
The invention has the beneficial effects that:
1. the low-voltage broadband linear equalizer circuit applied to the high-speed serial interface can realize the linear equalization of high-speed serial signals at a receiving end under the design requirement of low power supply voltage, provides a broadband gain adjustable function, effectively eliminates intersymbol interference jitter (ISI jitter) introduced into a channel, and reduces the Bit Error Rate (BER) of the signals at the receiving end.
2. On the basis of the traditional linear balancing circuit, the bandwidth of the balancing circuit is effectively expanded and the voltage drop introduced by the load resistance is reduced by adding the bandwidth expansion branch and the load shunt branch.
3. The bandwidth expansion branch adopts an active inductance structure, inductance peaking is generated at the output end, and the bandwidth expansion branch is connected with the main signal branch in parallel to effectively expand the bandwidth of the equalization circuit.
4. The load shunt branch adopts a current mirror structure, and shunts the bias current generated by the bandwidth expansion branch, so that the overlarge voltage drop of the load resistor is avoided, and the design requirement under the low power supply voltage is met.
Drawings
FIG. 1 is a schematic diagram of a low-voltage wideband linear equalizer circuit applied to a high-speed serial interface according to an embodiment of the present invention
Fig. 2 is a schematic structural diagram of a single-ended active inductor equivalent circuit according to an embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the figures and examples.
Fig. 1 is a schematic diagram of an embodiment of a low-voltage wideband linear equalizer circuit applied to a high-speed serial interface according to the present invention. As shown in fig. 1, the low-voltage wideband linear equalizer circuit applied to the high-speed serial interface according to the present invention adopts a differential circuit structure, where the differential signal input ports are INP and INN, and the differential signal output ports are OUTP and OUTN. As shown in fig. 1, the entire equalization circuit includes a main signal branch, a bandwidth expansion branch, a load splitting branch, and a bias branch.
The main signal branch adopts a CML (Current Mode logic) structure with a source-end degeneration resistor/capacitor, and comprises an input differential pair transistor NM1, an input differential pair transistor NM2, a load resistor R1, a load resistor R2, a transistor NM7 and a transistor NM8 which form a current source, a source-end adjustable negative feedback resistor Rs (namely a source-end negative feedback resistor), a transistor PM1 and a transistor PM2 which form a source-end negative feedback capacitor. By additionally introducing a pair of zero points omegazAnd pole ωp1Providing the required equalization functions. Selecting zero omega according to the high-frequency gain range and frequency range of equalizer circuitzAnd pole ωp1And determining the adjustable negative feedback resistor R of the source end according to the formula (1) and the formula (2)sAnd transconductance g provided by the input differential pair transistor NM1 and the input differential pair transistor NM2m1/2Size and required source end negative feedback capacitance (C)s) The range of (1). According to the required source end negative feedback capacitance (C)s) The sizes of the transistor PM1 and the transistor PM2 constituting the source side degeneration capacitance are selected.
In the formula (1) and the formula (2):
ωzthe zero values of the high-frequency gain range and the frequency range to be adjusted on the receiving end of the high-speed serial interface are represented by the following units: radians per second (rad/s);
ωp1the high-frequency gain range and the pole value of the frequency range which are needed to be adjusted on the receiving end of the high-speed serial interface have the following units: radians per second (rad/s);
Rsthe unit is the value of the source end adjustable negative feedback resistor Rs: ohm;
Csthe unit is the value of the negative feedback capacitor at the source end: faraday;
gmthe values of the transconductances provided for the input differential pair transistors NM1/NM2 are given in units of: siemens (S).
The bandwidth extension branch comprises a transistor NM3, a transistor NM4, a transistor NM9 forming a current source, a resistor R3, a resistor R4, a transistor NM5 forming a capacitor, and a transistor NM 6. The bandwidth expansion branch utilizes an inductance peaking principle and adopts a differential active inductance structure to form inductive impedance at an output end, so that the purpose of expanding the bandwidth of the equalizer is achieved.
The differential active inductance structure in the bandwidth extension branch comprises two sets of single-ended active inductance equivalent circuits (the single-ended active inductance equivalent circuit is shown in figure 2),
one group is composed of a transistor NM3 (as the transistor NMOS in fig. 2), a resistor R3 (as the resistor R in fig. 2), and a transistor NM5 (as the capacitor C in fig. 2), and the output terminal OUT is the output port OUTN;
the other group is composed of a transistor NM4 (as a transistor NMOS in fig. 2), a resistor R4 (as a resistor R in fig. 2), and a transistor NM6 (as a capacitor in fig. 2), and the output terminal OUT is an output port OUTP;
in a single-ended active inductor equivalent circuit (as shown in fig. 2), the transconductance of the transistor NMOS is denoted as gmThe output impedance is represented as ro. The equivalent output impedance Z seen at the output terminal OUToutExpressed by equation (3):
in equation (3):
Zoutrefers to the value of the equivalent output impedance seen at the output terminal OUT, in units of: ohm;
gmthe unit is the transconductance value of the NMOS of the transistor: siemens (S);
rothe output impedance of the transistor NMOS is given by: ohm;
sRC is the product of the resistance of the resistor R and the capacitance of the capacitor C, which can be expressed as the capacitance sC of the resistor R and the capacitor C respectively, and the unit is ohm;
sC is the capacitive reactance of the capacitor C in ohms.
At low frequency the output impedance is (1/g)m)//roThe output impedance is R/R at high frequencyoSelecting the size of NMOS, the size of IBIAS and the resistance value of resistor R to ensure 1/gm<R, i.e. it can be ensured that an inductive impedance is present at the output. The equivalent inductance value is expressed by equation (4):
in equation (4):
l is the equivalent inductance value of the single-ended active inductor equivalent circuit, and the unit is: henry (H);
gmthe values of the transconductances provided for the transistors NM3/NM4 are given in units of: siemens (S);
r is the value of resistance R in the single-ended active inductance equivalent circuit, and the unit is: ohm;
c is the value of the capacitor C in the single-ended active inductor equivalent circuit, and the unit is as follows: and (4) carrying out Faraday.
And determining the frequency range of the required inductance peaking according to the bandwidth design requirement of the equalizing circuit, and further selecting the value of the required inductance L. Determining the transconductance g of the transistor NM3 and the transistor NM4m3/4Resistance R3, resistance R4, and capacitance C. According to the range of values of the required capacitance C, selectingThe sizes of the transistor NM5 and the transistor NM6 constituting the capacitance. In addition, the influence of the bandwidth expansion branch on the output end load needs to be comprehensively considered, and 1/g is designedm3/4And the resistance R3 and the resistance R4 are larger than 10 times of the resistance of the load resistor R1 and the load resistor R2, so that the gain of the balancing circuit is prevented from being influenced. According to transconductance gm3/4The current of the bandwidth-extended branch is selected to size the transistor NM9 constituting the current source.
The load shunt branch comprises a transistor PM3, a transistor PM4, a transistor PM5 and a transistor NM10, wherein the transistors PM3, PM4 and PM5 form a current drain, and the transistor NM10 forms a current source. By selecting the size ratio of the transistor NM10 and the transistor NM9 which form a current source and the size ratio of the transistor PM3, the transistor PM4 and the transistor PM5 which form a current drain, the static current introduced by the bandwidth expansion branch is shunted at the differential signal output port OUTP and the differential signal output port OUTN, so that the voltage drop of the load resistor is avoided from being too large. The size selection of the transistor PM3 and the transistor PM4 needs to consider the influence on the loads of the differential signal output port OUTP and the differential signal output port OUTN, the channel length selection considers the proportional relation between the output resistance and the load resistance, and only the transistor output resistance is ensured to be greater than 10 times of the resistance values of the load resistance R1 and the load resistance R2, so that the influence on the gain of the balancing circuit is avoided. In the design of the high-speed serial interface linear equalization circuit, generally, due to the design consideration of bandwidth, the load resistor R1 and the load resistor R2 select resistors with small resistance values, so the size selection of the transistor PM3 and the transistor PM4 is not too large, and the introduction of too large parasitic capacitance is avoided.
The bias branch comprises a transistor NM11 and a bias current source IBIAS. The drain terminal and the gate terminal of the transistor NM11 are connected with a bias current source IBIAS and provide a bias voltage VBN of the whole equalizing circuit, and the source terminal is grounded; the current source IBIAS has one end connected to the drain terminal and the gate terminal of the transistor NM11, and the other end connected to the third POWER supply 3. The size of the transistor NM11 is selected to ensure that the output bias voltage VBN is appropriate, and the whole linear equalization circuit works stably.
The device according to the present invention is not limited to the embodiments described in the specific embodiments, and those skilled in the art can derive other embodiments according to the technical solutions of the present invention, and also belong to the technical innovation scope of the present invention.
Claims (5)
1. A low-voltage broadband linear equalizer circuit applied to a high-speed serial interface is used for providing equalization compensation for differential signals input by a receiving end of the high-speed serial interface, and is characterized in that: the device comprises a differential signal input port INP, a differential signal input port INN, a main signal branch, a bandwidth expansion branch, a load shunt branch, a bias branch, a differential signal output port OUTP and a differential signal output port OUTN;
the differential signal input port INP and the differential signal input port INN are used for input of the differential signal;
the main signal branch circuit performs equalization processing on the differential signal by utilizing negative feedback of a source end negative feedback resistor and negative feedback of a source end negative feedback capacitor;
the bandwidth expansion branch utilizes an inductance peaking principle and adopts a differential active inductance structure to form inductive impedance at the differential signal output port OUTP and the differential signal output port OUTN so as to achieve the purpose of expanding the bandwidth of the equalizer;
the load shunt branch adopts a current mirror structure to shunt part of current of the bandwidth expansion branch, so that overlarge voltage drop of a load resistor of the bandwidth expansion branch is avoided;
the bias branch circuit provides a bias voltage VBN for transistors forming the current source in the main signal branch circuit, the bandwidth expansion branch circuit and the load shunt branch circuit;
the differential signal output port OUTP and the differential signal output port OUTN are used for outputting the differential signal after being equalized by the main signal branch.
2. The low voltage wideband linear equalizer circuit as claimed in claim 1, wherein: the main signal branch comprises an input differential pair transistor NM1, an input differential pair transistor NM2, a load resistor R1, a load resistor R2 and a source end adjustable negative feedback resistor Rs, wherein the source end adjustable negative feedback resistor Rs is the source end negative feedback resistor; the power supply further comprises a transistor NM7 and a transistor NM8 which form the current source, and further comprises a transistor PM1 and a transistor PM2 which form the source end negative feedback capacitor;
the gate terminal of the input differential pair transistor NM1 is connected to the differential signal input port INP, the drain terminal is connected to the differential signal output port OUTN, and the source terminal is connected to the drain terminal of the transistor NM7 that constitutes the current source;
the gate terminal of the input differential pair transistor NM2 is connected to the differential signal input port INN, the drain terminal is connected to the differential signal output port OUTP, and the source terminal is connected to the drain terminal of the transistor NM8 constituting the current source;
one end of the load resistor R1 is connected with the differential signal output port OUTN, and the other end is connected with a first POWER supply 1;
one end of the load resistor R2 is connected with the differential signal output port OUTP, and the other end of the load resistor R2 is connected with a first POWER supply POWER 1;
the source end adjustable negative feedback resistor Rs is connected between the source end of the input differential pair transistor NM1 and the source end of the input differential pair transistor NM2 in a bridge mode;
the gate terminal of the transistor PM1 is connected with the source terminal of the input differential pair transistor NM1, and the source terminal and the drain terminal of the transistor PM1 are both connected with a second POWER supply 2;
the gate terminal of the transistor PM2 is connected with the source terminal of the input differential pair transistor NM2, and the source terminal and the drain terminal of the transistor PM2 are both connected with a POWER supply second POWER supply 2;
the drain terminal of the transistor NM7 is connected to the source terminal of the input differential pair transistor NM1, the gate terminal is connected to the bias voltage VBN provided by the bias branch, and the source terminal is connected to ground;
the drain terminal of the transistor NM8 is connected to the source terminal of the input differential pair transistor NM2, the gate terminal is connected to the bias voltage VBN provided by the bias branch, and the source terminal is connected to ground.
3. The low voltage wideband linear equalizer circuit as claimed in claim 1, wherein: the bandwidth expansion branch comprises a transistor NM3, a transistor NM4, a transistor NM9 forming the current source, a resistor R3, a resistor R4, a transistor NM5 forming a capacitor and a transistor NM 6;
the drain terminal of the transistor NM3 is connected to the differential signal output port OUTN, the gate terminal is connected to the gate terminal of the transistor NM5, and the source terminal is connected to the drain terminal of the transistor NM 9;
the drain terminal of the transistor NM4 is connected to the differential signal output port OUTP, the gate terminal is connected to the gate terminal of the transistor NM6, and the source terminal is connected to the drain terminal of the transistor NM 9;
one end of the resistor R3 is connected to the differential signal output port OUTN, and the other end is connected to the gate terminal of the transistor NM 5;
one end of the resistor R4 is connected to the differential signal output port OUTP, and the other end is connected to the gate terminal of the transistor NM 6;
the grid end of the transistor NM5 is connected with the grid end of the transistor NM3, and the source end and the drain end are both connected with the ground;
the grid end of the transistor NM6 is connected with the grid end of the transistor NM4, and the source end and the drain end are both connected with the ground;
the drain terminal of the transistor NM9 is connected to the source terminal of the transistor NM3 and the source terminal of the transistor NM4, the gate terminal is connected to the bias voltage VBN provided by the bias branch, and the source terminal is connected to ground.
4. The low voltage wideband linear equalizer circuit as claimed in claim 1, wherein: the load shunt branch adopts a current mirror structure and comprises a transistor PM3, a transistor PM4 and a transistor PM5 which form a current drain, and further comprises a transistor NM10 which forms the current source;
the drain terminal of the transistor PM3 is connected to the differential signal output port OUTN, the gate terminal is connected to the gate terminal of the transistor PM5, and the source terminal is connected to the first POWER supply 1;
the drain terminal of the transistor PM4 is connected to the differential signal output port OUTP, the gate terminal is connected to the gate terminal of the transistor PM5, and the source terminal is connected to the first POWER supply 1;
the gate terminal and the drain terminal of the transistor PM5 are connected with the drain terminal of the transistor NM10, and the source terminal of the transistor PM5 is connected with a first POWER supply 1;
the drain terminal of the transistor NM10 is connected to the source terminal and the drain terminal of the transistor PM5, the gate terminal is connected to the bias voltage VBN provided by the bias branch, and the source terminal is connected to ground.
5. The low voltage wideband linear equalizer circuit as claimed in claim 1, wherein: the bias branch comprises a bias current source IBIAS and a diode-connected transistor NM 11;
the drain terminal and the gate terminal of the transistor NM11 are connected to the bias current source IBIAS and provide the bias voltage VBN of the whole equalization circuit, and the source terminal of the transistor NM11 is grounded;
one end of the current source IBIAS is connected to the drain terminal and the gate terminal of the transistor NM11, and the other end is connected to a third POWER supply 3.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040119536A1 (en) * | 2002-12-12 | 2004-06-24 | Kwon Chong Ki | Variable gain amplifier |
| CA2480608A1 (en) * | 2003-09-09 | 2005-03-09 | Gennum Corporation | Elevated front-end transimpedance amplifier |
| US8200179B1 (en) * | 2008-10-07 | 2012-06-12 | Lattice Semiconductor Corporation | Combined variable gain amplifier and analog equalizer circuit |
| CN103346778A (en) * | 2013-07-04 | 2013-10-09 | 北京大学 | Broadband linear equalization circuit |
| CN106209709A (en) * | 2016-07-15 | 2016-12-07 | 中国电子科技集团公司第五十八研究所 | A kind of linear equalizer being applicable to HSSI High-Speed Serial Interface |
| US9621136B1 (en) * | 2015-11-12 | 2017-04-11 | Nxp Usa, Inc. | Data sampler circuit with equalization function and method for sampling data |
| CN107147369A (en) * | 2017-03-29 | 2017-09-08 | 电子科技大学 | Temperature gain balanced device |
| CN107395164A (en) * | 2017-07-10 | 2017-11-24 | 东南大学 | The continuously adjustable Real-time Delay line circuit of high-precision wide band |
-
2019
- 2019-11-15 CN CN201911119532.6A patent/CN110995187A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040119536A1 (en) * | 2002-12-12 | 2004-06-24 | Kwon Chong Ki | Variable gain amplifier |
| CA2480608A1 (en) * | 2003-09-09 | 2005-03-09 | Gennum Corporation | Elevated front-end transimpedance amplifier |
| US8200179B1 (en) * | 2008-10-07 | 2012-06-12 | Lattice Semiconductor Corporation | Combined variable gain amplifier and analog equalizer circuit |
| CN103346778A (en) * | 2013-07-04 | 2013-10-09 | 北京大学 | Broadband linear equalization circuit |
| US9621136B1 (en) * | 2015-11-12 | 2017-04-11 | Nxp Usa, Inc. | Data sampler circuit with equalization function and method for sampling data |
| CN106209709A (en) * | 2016-07-15 | 2016-12-07 | 中国电子科技集团公司第五十八研究所 | A kind of linear equalizer being applicable to HSSI High-Speed Serial Interface |
| CN107147369A (en) * | 2017-03-29 | 2017-09-08 | 电子科技大学 | Temperature gain balanced device |
| CN107395164A (en) * | 2017-07-10 | 2017-11-24 | 东南大学 | The continuously adjustable Real-time Delay line circuit of high-precision wide band |
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