CN110993597A - Package stacking structure capable of reducing package volume - Google Patents
Package stacking structure capable of reducing package volume Download PDFInfo
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- CN110993597A CN110993597A CN201911271817.1A CN201911271817A CN110993597A CN 110993597 A CN110993597 A CN 110993597A CN 201911271817 A CN201911271817 A CN 201911271817A CN 110993597 A CN110993597 A CN 110993597A
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- crystal grain
- controller
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- packaging
- flash storage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention relates to a package stacking structure for reducing package volume, which comprises: the packaging structure comprises a packaging substrate, a controller crystal grain, an insulating support gasket, a bonding wire of the controller crystal grain, a Flash storage crystal grain and a bonding wire of the Flash storage crystal grain; pasting the controller crystal grain on the packaging substrate; electrically connecting the controller crystal grain and the packaging substrate through a bonding wire by a bonding process; two insulating gaskets are respectively adhered to the packaging substrates on two sides of the controller crystal grain; two Flash storage crystal grains are respectively stacked on the insulating gasket; the Flash storage crystal grain is electrically connected with the packaging substrate through a bonding wire, the Flash storage crystal grain is a large-size crystal grain, and the controller crystal grain is a small-size crystal grain. The packaging stack structure adopted by the invention can effectively reduce the packaging volume and improve the reliability of the chip.
Description
Technical Field
The present invention relates to a memory chip package technology, and more particularly, to a package stack structure with a reduced package volume.
Background
With the continuous development of technologies such as internet of things, 5G communication, artificial intelligence and the like, the market demand for high-reliability, small-sized and large-capacity memory chips is increasing. The SiP three-dimensional stacking packaging technology with high integration and small packaging volume rapidly becomes the market focus.
In view of the above background, how to design a package stacking scheme capable of effectively reducing the package volume and increasing the storage capacity of a single chip, and simultaneously ensuring the reliability of a chip device is a technical difficulty and a problem to be solved herein. Existing package structures include die tiling, 3D stacking, Through Silicon Vias (TSVs), and other techniques. The package structure with the tiled die has high reliability, but the tiled die makes the package bulky. The TSV stacking technology can greatly reduce the package volume, but the production cost is expensive.
Fig. 1 is a diagram showing a stacking structure in which a small-sized die is stacked on a lower layer and a large-sized die is stacked on an upper layer in the prior art, and fig. 2 is a diagram showing a stacking structure in which a large-sized die is stacked on a lower layer and a small-sized die is stacked on an upper layer in the prior art. Firstly, controller crystal grains are adhered to a packaging substrate, and Flash crystal grains are stacked on the controller, so that the large-size Flash crystal grains on the upper layer are suspended, the crystal grains are easy to break, and the problem of chip failure is caused; and secondly, the Flash crystal grain is adhered to the packaging substrate, the controller crystal grain is stacked on the Flash crystal grain, and due to the small size of the controller crystal grain, the bonding wire connecting the controller crystal grain to the substrate is too long, and the bonding wires are easy to touch, so that the problems of short circuit and the like are caused. Therefore, only a tiled package structure can be used, but the chip package is bulky.
Therefore, a new package stacking structure is needed to solve the problem of stacking memory chip packages with large grain size difference.
Disclosure of Invention
The invention aims to provide a packaging stacking structure capable of reducing the packaging volume, which is used for solving the problem that the packaging volume is large because the existing packaging stacking technology cannot be suitable for stacking of crystal grains with larger size difference.
The invention relates to a packaging stack structure for reducing packaging volume, which comprises: the packaging structure comprises a packaging substrate, a controller crystal grain, an insulating support gasket, a bonding wire of the controller crystal grain, a Flash storage crystal grain and a bonding wire of the Flash storage crystal grain; pasting the controller crystal grain on the packaging substrate; electrically connecting the controller crystal grain and the packaging substrate through a bonding wire by a bonding process; two insulating gaskets are respectively adhered to the packaging substrates on two sides of the controller crystal grain; two Flash storage crystal grains are respectively stacked on the insulating gasket; the Flash storage crystal grain is electrically connected with the packaging substrate through a bonding wire, the Flash storage crystal grain is a large-size crystal grain, and the controller crystal grain is a small-size crystal grain.
According to an embodiment of the package stack structure with reduced package volume of the present invention, the height of the insulating spacer is greater than 250um of the small-sized die, and the height of the bonding wire loop of the small-sized die is controlled within 35 um.
According to an embodiment of the package stack structure with a reduced package volume of the present invention, two large-sized Flash memory dies are supported by two supporting pads to protect the underlying controller die and the bonding wire.
According to an embodiment of the package stack structure with reduced package volume of the present invention, the spacer is a semiconductor Silicon On Insulator (SOI) chip.
According to an embodiment of the package stack structure with reduced package volume of the present invention, the thickness of the spacer is greater than the small-sized die 50 um.
According to an embodiment of the package stack structure with reduced package volume of the present invention, the large-sized die cannot press against the bonding wires on the small-sized die.
The invention relates to the fields of Internet of things, communication, artificial intelligence and the like, and the fields have small requirements on a storage chip, large storage capacity and high reliability. The packaging stack structure adopted by the invention can effectively reduce the packaging volume and improve the reliability of the chip. The problem of current encapsulation pile up the technique and can't be applicable to the size and differ great stacking between the grain and lead to the encapsulation bulky is solved.
Drawings
FIG. 1 is a diagram illustrating a stacking structure of a small-sized die stacked on a lower layer and a large-sized die stacked on an upper layer in the prior art;
fig. 2 is a diagram illustrating a stacking structure of a large-sized die stacked on a lower layer and a small-sized die stacked on an upper layer in the prior art;
fig. 3 is a diagram illustrating a package stack structure according to the present invention.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
Fig. 3 is a diagram showing a package stack structure of the present invention, and as shown in fig. 3, the package stack structure of the present invention includes a package substrate 5, a controller die 2, an insulating support pad 6, a bonding wire 4 of the controller die, a Flash memory die 1, and a bonding wire 3 of the Flash memory die. Referring to fig. 3, specific packages are stacked as follows:
the small-sized controller die 2 is first attached to the package substrate 5.
The controller die 2 and the package substrate 5 are electrically connected through a bonding wire 4 by a bonding process technology.
Two insulating gaskets 6 are respectively adhered to the packaging substrates at two sides of the controller crystal grain 2.
Two large-size Flash memory crystal grains 1 are respectively stacked on the insulating gasket 6.
The Flash storage crystal grain 1 is electrically connected with the packaging substrate 5 through a bonding wire 3.
The large-size crystal grain 1 is prevented from being pressed against the bonding wire 4, the height of the insulating gasket 6 is larger than that of the small-size crystal grain 250um, and the wire arc height of the bonding wire 4 of the small-size crystal grain 2 is controlled within 35 um. As shown in fig. 3, two supporting pads 6 support two large-sized Flash storage dies 1 on the upper side, so that the controller die 2 and the bonding wire 4 on the lower side are protected from being pressed and bumped, and the reliability is improved.
The invention provides a packaging stacked structure which comprises two crystal grains with large size difference (a large-size Flash storage crystal grain and a small-size controller crystal grain), a packaging substrate and a supporting gasket. The gasket can support the large-size crystal grains stacked on the upper layer and ensure that the bonding wires on the small-size crystal grains on the lower layer are not pressed and bumped.
Preferably, the spacer is a semiconductor silicon-on-insulator (wafer dummy without circuit).
Preferably, the small-sized die is attached to a package substrate.
Preferably, the spacer thickness is greater than the small-sized grains 50 um.
Preferably, the insulating spacers are adhered to the substrate on both sides of the small-sized die.
Preferably, the large-sized grains are stacked on the spacer.
Preferably, the large-sized die cannot press against the bonding wire on the small-sized die.
As described above, the package stack structure of the present invention has the following advantages:
the present invention generally achieves a new package stacking method. By the novel stacking method, the three-dimensional stacking among crystal grains with large size difference can be realized, and the packaging volume is effectively reduced. Through the novel packaging and stacking structure, the problem that the chip packaging with large grain size difference cannot be stacked can be solved, compared with the traditional crystal grain tiling packaging scheme, the packaging volume of the chip is effectively reduced, and the reliability is improved.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (6)
1. A package stack structure for reducing a package volume, comprising: the packaging structure comprises a packaging substrate, a controller crystal grain, an insulating support gasket, a bonding wire of the controller crystal grain, a Flash storage crystal grain and a bonding wire of the Flash storage crystal grain;
pasting the controller crystal grain on the packaging substrate;
electrically connecting the controller crystal grain and the packaging substrate through a bonding wire by a bonding process;
two insulating gaskets are respectively adhered to the packaging substrates on two sides of the controller crystal grain;
two Flash storage crystal grains are respectively stacked on the insulating gasket;
the Flash storage crystal grain is electrically connected with the packaging substrate through a bonding wire, the Flash storage crystal grain is a large-size crystal grain, and the controller crystal grain is a small-size crystal grain.
2. The reduced package volume package stack of claim 1, wherein the insulating spacer height is greater than 250um for the small-sized die, and the bond wire loop height for the small-sized die is controlled to be within 35 um.
3. The package stack structure with reduced package volume of claim 1, wherein two support pads support two large-sized Flash memory dies, protecting an underlying controller die and bonding wires.
4. The reduced package volume package stack of claim 1, wherein the spacer is a silicon-on-semiconductor wafer.
5. The reduced package volume package stack of claim 1, wherein the spacer thickness is greater than 50um for small-sized die.
6. The reduced package volume package stack structure of claim 1, wherein the large-sized die is unable to press against bond wires on the small-sized die.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911271817.1A CN110993597A (en) | 2019-12-12 | 2019-12-12 | Package stacking structure capable of reducing package volume |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911271817.1A CN110993597A (en) | 2019-12-12 | 2019-12-12 | Package stacking structure capable of reducing package volume |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110993597A true CN110993597A (en) | 2020-04-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201911271817.1A Pending CN110993597A (en) | 2019-12-12 | 2019-12-12 | Package stacking structure capable of reducing package volume |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1531085A (en) * | 2003-03-12 | 2004-09-22 | ��ʽ���������Ƽ� | Semiconductor devices |
| CN102110678A (en) * | 2009-12-31 | 2011-06-29 | 日月光半导体制造股份有限公司 | Semiconductor package and manufacturing method thereof |
| US20130056882A1 (en) * | 2011-09-06 | 2013-03-07 | Samsung Electronics Co., Ltd. | Semiconductor package having support member |
| US20150155265A1 (en) * | 2012-10-08 | 2015-06-04 | Qualcomm Incorporated | Stacked multi-chip integrated circuit package |
| US20180277529A1 (en) * | 2017-03-23 | 2018-09-27 | Toshiba Memory Corporation | Semiconductor package |
-
2019
- 2019-12-12 CN CN201911271817.1A patent/CN110993597A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1531085A (en) * | 2003-03-12 | 2004-09-22 | ��ʽ���������Ƽ� | Semiconductor devices |
| CN102110678A (en) * | 2009-12-31 | 2011-06-29 | 日月光半导体制造股份有限公司 | Semiconductor package and manufacturing method thereof |
| US20130056882A1 (en) * | 2011-09-06 | 2013-03-07 | Samsung Electronics Co., Ltd. | Semiconductor package having support member |
| US20150155265A1 (en) * | 2012-10-08 | 2015-06-04 | Qualcomm Incorporated | Stacked multi-chip integrated circuit package |
| US20180277529A1 (en) * | 2017-03-23 | 2018-09-27 | Toshiba Memory Corporation | Semiconductor package |
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Application publication date: 20200410 |