CN110989815A - Power supply monitoring method and system based on development board - Google Patents
Power supply monitoring method and system based on development board Download PDFInfo
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- CN110989815A CN110989815A CN201911247035.4A CN201911247035A CN110989815A CN 110989815 A CN110989815 A CN 110989815A CN 201911247035 A CN201911247035 A CN 201911247035A CN 110989815 A CN110989815 A CN 110989815A
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
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Abstract
The invention discloses a power supply monitoring method and a system based on a development board, wherein the method comprises the following steps: step S1, adding a development board to be monitored, connecting the development board to be monitored to a computer and confirming normal work and normal Ethernet connection; s2, adopting multiple chips to manage the power supply of the development board, wherein different rails on the development board are responsible for managing different FPGA power supply inputs, the chips automatically monitor the power supply inputs, and a user selects a power supply channel to be monitored; step S3, monitoring the power supply by the user according to the selected monitoring power supply channel, selecting different development boards through the display interface, and checking the power supply condition of the development boards; and step S4, timely early warning dangerous conditions according to user monitoring results, monitoring abnormal data of the background in real time, feeding back the abnormal data, and presenting normal data.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a power supply monitoring method and system based on a development board.
Background
The development board is a circuit board for developing an embedded system, and comprises a series of hardware components such as a central processing unit, a memory, an input device, an output device, a data path/bus, an external resource interface and the like. The development board is generally customized by an embedded system developer according to development requirements, and can also be researched and designed by a user. The development board is used for a beginner to know and learn hardware and software of the system, and meanwhile, a part of the development board also provides a basic integrated development environment, software source codes, a hardware schematic diagram and the like. Common development boards include 51, ARM, FPGA and DSP development boards.
Problems easily occur when a power supply of a development board on the market is used, wherein the problems include voltage, current and temperature conditions, if the conditions are not found in time, the FPGA development board is damaged, and the use and development of the development board are influenced.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a power supply monitoring method and system based on a development board, which can monitor the power supply condition of a user chip development board in real time, can detect the working performance indexes of one or more FPGAs at the same time, has great help in observing and debugging the physical performance parameters of the development board during design and operation, and can effectively solve the problems provided by the background technology.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a power supply monitoring method based on a development board comprises the following steps:
step S1, adding a development board to be monitored, connecting the development board to be monitored to a computer and confirming normal work and normal Ethernet connection;
s2, adopting multiple chips to manage the power supply of the development board, wherein different rails on the development board are responsible for managing different FPGA power supply inputs, the chips automatically monitor the power supply inputs, and a user selects a power supply channel to be monitored;
step S3, monitoring the power supply by the user according to the selected monitoring power supply channel, selecting different development boards through the display interface, and checking the power supply condition of the development boards;
and step S4, timely early warning dangerous conditions according to the monitoring results of the user, monitoring abnormal data of the background in real time, feeding back the abnormal data, and presenting normal data.
Further, the UCD90124 chip is adopted as the chip in step S2, the UCD90124 chip has a built-in temperature control algorithm, the fan speed based on the 5 configurable temperature regions can be automatically adjusted, and a designer can adjust the desired fan speed through an I2C command by using the temperature control algorithm running on an external host processor.
Further, a configuration interface bus of the UCD90124 chip adopts a PMBus structure, and the UCD90124 chip can generate up to 8 clocks with configurable frequency range between 15.259kHz and 125MHz and phase shift range between 0 and 360 degrees, so as to simplify the power supply of a synchronous power supply in a switch mode.
Further, the data condition displayed by the display interface in the step S3 includes voltage, current and temperature data of the power supply of the development board.
Further, in step S4, the specific process of monitoring the result by the user and timely warning the dangerous situation is as follows:
dividing a display interface into two yellow and red intervals, wherein the data of the display interface is positioned in the yellow interval to show that the power supply data is at a normal value;
when the data of the display interface exceeds the yellow area, the data of the power supply exceeds a normal value, an electrical error may occur, and early warning is needed;
when the data of the display interface exceeds the red area, indicating that a serious error occurs, the operation must be terminated and the development board power supply is disconnected.
Further, the yellow and red intervals on the display interface are obtained through calculation of development boards selected by a user, and the display interval ranges of different development boards are different.
A power monitoring system based on a development board comprises
The development board type number selection module is used for adding a development board to be monitored by a user, connecting the development board to be monitored to a computer and confirming normal work and normal Ethernet connection;
the power supply management and selection module is used for managing the power supply of the development board by a user through a plurality of chips, different rails on the development board are responsible for managing different FPGA chip power supply inputs, the chips automatically monitor the power supply inputs, and the user selects a power supply channel to be monitored;
the power supply monitoring module is used for monitoring the power supply according to the selected monitoring power supply channel by a user, selecting different development boards through a display interface and checking the power supply condition of the development boards;
and the monitoring and early warning module is used for timely early warning dangerous conditions according to the monitoring result of the user, monitoring abnormal data of the background in real time, feeding back the abnormal data and presenting normal data.
Compared with the prior art, the invention has the beneficial effects that:
the invention monitors the power supply condition of the user chip development board in real time, can simultaneously detect the working performance indexes of one or more chips such as FPGA and the like, can effectively protect the chip development boards such as FPGA and the like from being damaged, accelerates the FPGA design flow, and has great help in observing and debugging the physical performance parameters when the development boards are designed and operated.
Drawings
FIG. 1 is a schematic diagram of the working flow of the power monitoring method of the present invention;
FIG. 2 is a schematic diagram of an internal register structure of the UCD90124 chip of the present invention;
fig. 3 is a schematic diagram of an electrical connection structure of the UCD90124 chip on the TAILM board.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 to 3, the present invention provides a power monitoring method based on a development board, including:
step S1, adding the model of the development board to be monitored, connecting the development board to be monitored to the computer and confirming the normal work and the normal connection of the Ethernet;
s2, adopting multiple chips to manage the power supply of the development board, wherein different rails on the development board are responsible for managing different FPGA power supply inputs, the chips automatically monitor the power supply inputs, and a user selects a power supply channel to be monitored;
step S3, monitoring the power supply by the user according to the selected monitoring power supply channel, selecting different development boards through the display interface, and checking the power supply condition of the development boards;
and step S4, timely early warning dangerous conditions according to the monitoring results of the user, monitoring abnormal data of the background in real time, feeding back the abnormal data, and presenting normal data.
Preferably, the development board in the present scheme is selected as a TAILM development board.
Furthermore, the chip in step S2 is a UCD90124 chip, the UCD90124 chip has a built-in temperature control algorithm, and can automatically adjust the fan speed based on 5 configurable temperature regions, a designer can adjust the desired fan speed by using the temperature control algorithm running on the external host processor and through an I2C command, and can further control the temperature of the power module by adjusting the fan speed, so that the risk of the power module being over-high in temperature can be reduced, and a good protection effect can be achieved.
The UCD90124 chip can generate up to 8 clocks with configurable frequency range between 15.259kHz and 125MHz and phase shift range between 0 and 360 degrees, and is used for simplifying synchronous power supply in a switch mode.
The UCD90124 chip has the following characteristics:
up to 12 power supplies can be sequenced and monitored, and margin adjustment can be carried out on up to 10 groups of power supply rails;
power management and monitoring can be performed on up to 4 fans in a single device;
the UCD90124 has a built-in temperature control algorithm that automatically adjusts fan speed based on 5 configurable temperature zones, or the designer can use a temperature control algorithm running on an external host processor and command an adjustment of the desired fan speed via I2C. The intelligent system heat dissipation management is beneficial to reducing system noise and prolonging the service life of the fan;
the automatic calibration function can automatically determine the opening and closing of the fan and improve the duty ratio to the maximum extent, so that a designer can calculate the running speed and simultaneously cope with the environmental change affecting the rotating speed of the fan;
the UCD90124 chip can also generate up to 8 clocks with configurable frequency range between 15.259kHz and 125MHz and phase shift range between 0 and 360 degrees, and further simplifies synchronous power supply in a switch mode.
The external instruction program operates by configuring a register inside the UCD90124 chip, and a structure diagram of the register inside the UCD90124 chip is shown in fig. 2.
The electrical connection structure of the UCD90124 chip on the TAILM board is shown in figure 3.
The configuration interface bus of the UCD90124 chip adopts a PMBus bus structure, and the PMBus (power management bus) is an open standard digital power management protocol. Communication with a power converter or other device may be facilitated by defining transport and physical interfaces and command languages.
The PMBus transport layer is based on low-cost SMBus, SMBus is widely applied to a server based on Intel technology, a physical layer and a transport layer of an Intelligent Peripheral Management Interface (IPMI) are provided for system management, the SMBus is provided with a third signal line SMBASERT, and slave equipment (such as a load point converter) can interrupt control of a system host or a bus, the arrangement is more flexible than a mode that the system uses the host to continuously poll slaves, and the load of the system on a host processor is smaller, so designers can more easily realize an event-driven closed-loop control scheme. Furthermore, the PMBus protocol provides that all slave devices must either save their default configuration data in persistent memory or use pin programming so that they do not need to communicate with the bus any more when powered up. The system start-up time is thus much less than other digital control solutions on the market.
The physical address of each slave device is defined by a dedicated pin. Silicon manufacturers can offer a variety of innovative solutions, such as 3-state pin and resistor resistance programming. In addition to the SMBus clock, data and interrupt lines, the PMBus protocol specifies two hardware signals for use with the power conversion device, one being a control signal for use with commands issued by the bus for enabling and disabling individual slave devices: the other is an optional "write protect" signal that can be used to prevent alteration of the data in the memory.
The communication of the PMBus is according to a simple command set. Each packet contains an address byte, a command byte, zero, one or more data bytes, and an optional Packet Error Code (PEC) byte. A typical master-to-slave message transfer, the master uses separate "start" and "stop" to indicate the start and end of a process. While the slave uses a separate bit to acknowledge each byte received. In order to reduce response time and processor overhead, the slave immediately processes and executes commands upon receiving a "stop" signal, unlike many other bus protocols, the PMBus is not forced to wait for a separate "execute" command.
While the one-byte command code of the protocol indicates that there may be as many as 256 commands available, this does not indicate that the PMBus device is to support all of the commands, and in fact many devices need only use a small subset of the commands to achieve the intended purpose.
The rich command set of the PMBus protocol allows designers to write simple and efficient power management programs that allow them to easily and quickly implement design solutions. Voltage timing control of point-of-load converters provides one ideal example.
The data condition displayed by the display interface in the step S3 includes voltage, current and temperature data of the power supply of the development board.
In step S4, the specific process of monitoring the result by the user and timely warning the dangerous situation is as follows:
dividing a display interface into two yellow and red intervals, wherein the data of the display interface is positioned in the yellow interval to show that the power supply data is at a normal value;
when the data of the display interface exceeds the yellow area, the data of the power supply exceeds a normal value, an electrical error may occur, and early warning is needed;
when the data of the display interface exceeds the red area, indicating that a serious error occurs, the operation must be terminated and the development board power supply is disconnected.
The yellow and red intervals on the display interface are obtained through calculation of development boards selected by a user, and the display interval ranges of different development boards are different.
The power management chip can be used for synchronously monitoring a plurality of power modules, monitoring abnormal data in real time, and controlling the temperature of the power modules through the heat dissipation system while monitoring;
meanwhile, the adoption of the SMBus to interrupt the control of the system host or the bus is more flexible than the mode that the system uses the host to continuously poll the slave, and the burden on the host processor is smaller, so that designers can more easily realize an event-driven closed-loop control scheme.
The invention also provides a power supply monitoring system based on the development board, which comprises:
the development board selection module is used for adding a development board to be monitored by a user, connecting the development board to be monitored to a computer and confirming normal work and normal Ethernet connection;
the power supply management and selection module is used for managing the power supply of the development board by a user through a plurality of chips, different rails on the development board are responsible for managing different FPGA power supply inputs, the chips automatically monitor the power supply inputs, and the user selects a power supply channel to be monitored;
the power supply monitoring module is used for monitoring the power supply according to the selected monitoring power supply channel by a user, selecting different development boards through a display interface and checking the power supply condition of the development boards;
and the monitoring and early warning module is used for timely early warning dangerous conditions according to the monitoring result of the user, monitoring abnormal data of the background in real time, feeding back the abnormal data and presenting normal data.
The working mode and the monitoring method of the system are the same, and are not described again here.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (7)
1. A power supply monitoring method based on a development board is characterized by comprising the following steps:
step S1, adding a development board to be monitored, connecting the development board to be monitored to a computer and confirming normal work and normal Ethernet connection;
s2, adopting multiple chips to manage the power supply of the development board, wherein different rails on the development board are responsible for managing different FPGA power supply inputs, the chips automatically monitor the power supply inputs, and a user selects a power supply channel to be monitored;
step S3, monitoring the power supply by the user according to the selected monitoring power supply channel, selecting different development boards through the display interface, and checking the power supply condition of the development boards;
and step S4, timely early warning dangerous conditions according to the monitoring results of the user, monitoring abnormal data of the background in real time, feeding back the abnormal data, and presenting normal data.
2. The power supply monitoring method based on the development board as claimed in claim 1, wherein the chip in step S2 employs a UCD90124 power management chip, the UCD90124 chip has a built-in temperature control algorithm, the fan speed based on 5 configurable temperature zones can be automatically adjusted, and a designer can adjust the desired fan speed by using the temperature control algorithm running on an external host processor and through an I2C command common in the industry.
3. The power supply monitoring method based on the development board as claimed in claim 2, wherein the configuration interface bus of the UCD90124 chip adopts a PMBus structure, and the UCD90124 chip can generate up to 8 clocks with configurable frequency range between 15.259kHz to 125MHz and phase shift range between 0 to 360 degrees, for simplifying the synchronous power supply in the switch mode.
4. The power supply monitoring method based on the development board as claimed in claim 1, wherein the data condition displayed by the display interface in step S3 includes voltage, current and temperature data of the power supply of the development board.
5. The power supply monitoring method based on the development board as claimed in claim 4, wherein in the step S4, the specific process of timely pre-warning the dangerous situation based on the user monitoring result is as follows:
dividing a display interface into two yellow and red intervals, wherein the data of the display interface is positioned in the yellow interval to show that the power supply data is at a normal value;
when the data of the display interface exceeds the yellow area, the data of the power supply exceeds a normal value, an electrical error may occur, and early warning is needed;
when the data of the display interface exceeds the red area, indicating that a serious error occurs, the operation must be terminated and the development board power supply is disconnected.
6. The power supply monitoring method based on the development board as claimed in claim 5, wherein the yellow and red regions on the display interface are calculated by the development board selected by the user, and the display region ranges of different development boards are different.
7. A power supply monitoring system based on a development board is characterized by comprising
The development board type number selection module is used for adding a development board to be monitored by a user, connecting the development board to be monitored to a computer and confirming normal work and normal Ethernet connection;
the power supply management and selection module is used for managing the power supply of the development board by a user through a plurality of chips, different rails on the development board are responsible for managing different FPGA power supply inputs, the chips automatically monitor the power supply inputs, and the user selects a power supply channel to be monitored;
the power supply monitoring module is used for monitoring the power supply according to the selected monitoring power supply channel by a user, selecting different development boards through a display interface and checking the power supply condition of the development boards;
and the monitoring and early warning module is used for timely early warning dangerous conditions according to the monitoring result of the user, monitoring abnormal data of the background in real time, feeding back the abnormal data and presenting normal data.
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| WO2022041088A1 (en) * | 2020-08-26 | 2022-03-03 | 江苏省瑞宝特科技发展有限公司 | Apparatus for power connection of internal devices of intelligent lamp pole and working method therefor |
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