CN110971237B

CN110971237B - Correction method and correction circuit for delta-sigma modulator

Info

Publication number: CN110971237B
Application number: CN201811147970.9A
Authority: CN
Inventors: 陈志龙; 赖杰帆; 陈昱璋; 黄诗雄
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2018-09-29
Filing date: 2018-09-29
Publication date: 2023-04-07
Anticipated expiration: 2038-09-29
Also published as: CN110971237A

Abstract

The application discloses a correction method and a correction circuit of a delta-sigma modulator. The delta-sigma modulator includes a loop filter, a quantizer and a digital-to-analog converter. The correction method comprises the following steps: controlling the digital-to-analog converter not to receive the output of the quantizer; controlling the sigma-delta modulator to stop receiving signals; inputting a test signal to the digital-to-analog converter; converting the output of the loop filter into a digital signal; comparing the digital signal with a preset value; and adjusting the loop filter according to the comparison result of the digital signal and the preset value.

Description

Correction method and correction circuit for delta-sigma modulator

Technical Field

The present invention relates to a sigma-delta modulator (SDM), and more particularly, to a method and circuit for calibrating a SDM.

Background

One of the disadvantages of the delta-sigma modulator, which can be used as an analog-to-digital converter (ADC), is that it is easily affected by process, voltage and temperature (temperature), resulting in poor resolution or even error of the ADC. Therefore, a calibration method and a calibration circuit are needed to calibrate the sigma-delta modulator to ensure the performance and accuracy of the sigma-delta modulator.

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide a calibration method and a calibration circuit for a delta-sigma modulator, which can reduce or avoid the influence of process, voltage and temperature on the delta-sigma modulator.

The application discloses a method for calibrating a sigma-delta modulator. The delta-sigma modulator includes a loop filter, a quantizer, and a digital-to-analog converter. The correction method comprises the following steps: controlling the digital-to-analog converter not to receive the output of the quantizer; controlling the sigma-delta modulator to stop receiving signals; inputting a test signal to the digital-to-analog converter; converting the output of the loop filter into a digital signal; comparing the digital signal with a preset value; and adjusting the loop filter according to the comparison result of the digital signal and the preset value.

The application further discloses a correction circuit for a delta-sigma modulator. The delta-sigma modulator includes a loop filter, a quantizer and a digital-to-analog converter. The correction circuit comprises a memory, a control circuit and an analog-digital converter. The memory stores a plurality of program instructions and a default value. The control circuit executes the program instructions to calibrate the sigma delta modulator. The analog-to-digital converter is coupled between the loop filter and the control circuit. The calibration procedure of the delta-sigma modulator comprises: controlling the digital-to-analog converter not to receive the output of the quantizer; controlling the sigma-delta modulator to stop receiving signals; inputting a test signal to the digital-to-analog converter; the analog-digital converter converts the output of the loop filter into a digital signal; comparing the digital signal with the preset value; and adjusting the loop filter according to the comparison result of the digital signal and the preset value.

The correction method and the correction circuit of the delta-sigma modulator can correct the delta-sigma modulator when a chip is delivered from a factory or before the circuit is operated. Compared with the conventional technology, the present application can make the actual circuit (continuous time delta-sigma modulator) and the simulated or designed circuit (discrete time delta-sigma modulator) have similar or even substantially the same performance as possible, and the effect of the process, voltage and temperature on the delta-sigma modulator can be greatly reduced by performing the correction in real time according to the current operating environment.

The features, operation and functions of the present application will be described in detail with reference to the accompanying drawings.

Drawings

FIG. 1 is a flowchart illustrating an embodiment of a calibration method for a sigma-delta modulator of the present application;

FIG. 2 is a block diagram of a calibration circuit for a sigma-delta modulator according to an embodiment of the present invention;

fig. 3A to 3B are graphs showing the relationship between the digital signal Dct and the predetermined digital signal Ddt and time;

FIG. 4 is a circuit diagram of one embodiment of a loop filter;

FIG. 5 is a block diagram of another embodiment of a calibration circuit for a sigma delta modulator according to the present application;

FIG. 6 is a flowchart illustrating another embodiment of a calibration method for a sigma delta modulator of the present application;

FIG. 7 is a circuit diagram of one embodiment of an ELD compensation circuit; and

FIG. 8 is a block diagram of another embodiment of a calibration circuit for a delta-sigma modulator according to the present invention.

Detailed Description

The technical terms in the following description refer to the conventional terms in the technical field, and some terms are explained or defined in the specification, and the explanation of the some terms is based on the explanation or the definition in the specification.

The disclosure of the present application includes a calibration method and a calibration circuit for a delta-sigma modulator to reduce or prevent the delta-sigma modulator from process, voltage and temperature effects. Since some of the components included in the calibration circuit of the delta-sigma modulator of the present application may be known components alone, the following description will omit details of the known components without affecting the full disclosure and the feasibility of the embodiments of the apparatus. Furthermore, part or all of the flow of the calibration method of the delta-sigma modulator of the present application may be in the form of software and/or firmware, and may be performed by the calibration circuit of the delta-sigma modulator of the present application or an equivalent thereof, and the following description of the method embodiments will focus on the content of steps rather than hardware without affecting the full disclosure and feasibility of the method embodiments.

Fig. 1 is a flowchart of an embodiment of a calibration method of a delta-sigma modulator according to the present application, and fig. 2 is a functional block diagram of an embodiment of a calibration circuit for a delta-sigma modulator. The calibration circuit includes an analog-to-digital converter 220, a memory 230, a control circuit 240, and a switch 250. The control circuit 240 may be a circuit having program execution capabilities, such as a central processing unit, microcontroller, microprocessor, or digital signal processor. The memory 230 stores a plurality of program codes or program instructions, and the control circuit 240 executes the program codes or program instructions to calibrate the sigma-delta modulator 210. The delta-sigma modulator 210 includes a summing circuit 212, a loop filter 214, a quantizer 216, and a digital-to-analog converter (DAC) 218. The following description refers to both fig. 1 and fig. 2.

When the calibration is started, the control circuit 240 transmits the control signal Csw to control the switch 250, so that the quantizer 216 and the digital-analog converter 218 are not electrically connected (step S110). The purpose of step S110 is to disconnect the connection between the quantizer 216 and the digital-to-analog converter 218, in other words, the control circuit 240 switches the switch 250 to make the digital-to-analog converter 218 not receive or temporarily not receive the output Dout of the quantizer 216 (i.e. the output of the quantizer 216 is the output of the delta-sigma modulator 210).

Next, the control circuit 240 controls the delta-sigma modulator 210 to stop receiving the signal (step S120), for example, controls the input signal Vin to be 0 or controls the adder circuit 212 to receive only the output signal of the digital-to-analog converter 218.

Next, the control circuit 240 inputs the test signal Dp to the digital-to-analog converter 218 (step S130). The test signal Dp is processed by the digital-to-analog converter 218, the adder circuit 212, and the loop filter 214 correspondingly outputs the signal Vc. In some embodiments, the test signal Dp may be a digital pulse.

Next, the output signal Vc of the loop filter 214 is converted into a digital signal Dct (step S140). More specifically, the present application utilizes an additional adc 220 (the adc 220 is not part of the sigma-delta modulator 210) to receive the output signal Vc of the loop filter 214, and uses the output of the adc 220 as the digital signal Dct (step S145). In some embodiments, the adc 220 belongs to other systems or circuits in the chip where the delta-sigma modulator 210 is located, which may be, for example, part of a Long Term Evolution (LTE) transceiver. When the receiving or transmitting circuit of the lte transceiver is idle, the control circuit 240 may utilize the adc of the idle receiving or transmitting circuit as the adc 220. After obtaining the digital signal Dct, the control circuit 240 may store the digital signal Dct in its own memory circuit (e.g., a register) or to the memory 230. In some embodiments, the resolution of the adc 220 is greater than the resolution of the quantizer 216, and the correction accuracy may be improved by using a higher resolution adc 220 to convert the signal Vc.

Next, the control circuit 240 determines whether or not the k digital signals Dct, k being positive integers, have been obtained (step S150). If not, the control circuit 240 repeats steps S130 to S145 until k digital signals Dct are obtained; if yes, go to step S160.

Next, the control circuit 240 compares the digital signal Dct with the preset digital signal Ddt to obtain a comparison result (step S160). In some embodiments, the preset digital signal Ddt is preset by k (k is an adjustable positive integer), and the control circuit 240 calculates a Least Mean Square (LMS) of a difference between the k digital signals Dct and the k preset digital signals Ddt. Fig. 3A and 3B are graphs of the digital signal Dct and the predetermined digital signal Ddt versus time, in which non-continuous segments (sawtooth segments) represent the predetermined digital signal Ddt and continuous segments represent the digital signal Dct. The predetermined digital signal Ddt can be regarded as an ideal output value of the delta-sigma modulator 210. The smaller the least mean square represents the closer the continuous line segment is to the discontinuous line segment, i.e. the closer the output of the sigma-delta modulator 210 is to the ideal value (in other words, the closer the sigma-delta modulator 210 is to the originally designed circuit). After obtaining the comparison result (e.g., the aforementioned least mean square) in step S160, the control circuit 240 may store the comparison result in its own memory circuit (e.g., a register) or store the comparison result in the memory 230.

The control circuit 240 next determines whether all the parameter combinations of the loop filter 214 have been performed (step S170). If not, executing step S180; if yes, go to step S190.

Fig. 4 is a circuit diagram of one embodiment of loop filter 214. The loop filter 214 is a fourth order loop filter comprising four integrators 410 (410-a-410-d), four amplifiers 420 (420-a-420-d), and a summing circuit 430. The operation principle of the loop filter of fig. 4 is well known to those skilled in the art, and therefore, will not be described herein. In some embodiments, the amplification factors (a, b, c, and d, respectively) of the amplifiers 420-a, 420-b, 420-c, and 420-d are controlled by control signals Ctrl 1-Ctrl 4 (which may be collectively represented by control signal Ctrl of FIG. 1) generated by the control circuit 240, respectively. If 5 choices are made for each of the magnifications a, b, c and d, then the loop filter 214 has 5 ⁴ =625 parameter combinations. In some embodiments, the resistors and capacitors of the integrators 410-a, 410-b, 410-c, and 410-d may also be used as parameters for adjusting the loop filter 214. In some embodiments, the control circuit 240 uses an exhaustive method to list all parameter combinations, but the application is not limited thereto. The following description is by way of example of an exhaustive enumeration.

Returning to fig. 1, when the determination result of step S170 is no, the control circuit 240 adjusts the loop filter 214 by selecting a parameter combination that has not been performed by the loop filter 214 in step S180. After the adjustment, the control circuit 240 performs steps S130 to S170 again.

When the determination in step S170 is yes, the representative control circuit 240 has obtained the comparison result for each parameter combination. Next, in step S190, the control circuit 240 determines the parameters of the loop filter 214 according to all the comparison results. More specifically, when the least mean square of the difference between the k digital signals Dct and the k preset digital signals Ddt is used as the comparison result in step S160, the control circuit 240 selects the parameter combination corresponding to the minimum value of the comparison results as the parameter of the loop filter 214 in step S190. After the parameters of the loop filter 214 are determined, the control circuit 240 switches the switch 250 to electrically connect the quantizer 216 and the digital-to-analog converter 218, thereby ending the calibration process of the delta-sigma modulator 210 (step S195).

As shown in fig. 3A or 3B, after the correction is completed, the output of the delta-sigma modulator 210 is relatively close to the ideal value. The discontinuous line segments (i.e. the predetermined digital signal dt) of fig. 3A or fig. 3B may be, for example, the simulation or calculation results of a discrete-time delta-sigma modulator. More specifically, when designing the delta-sigma modulator 210, a software tool may be used to create a discrete-time delta-sigma modulator having a structure similar to or substantially equal to that of the delta-sigma modulator 210, and similarly, the quantizer of the discrete-time delta-sigma modulator is disconnected from the digital-to-analog converter, and then the test signal is input to the digital-to-analog converter and the digital value of the output of the loop filter is obtained as the predetermined digital signal Ddt. The predetermined digital signal Ddt is an ideal output of the delta-sigma modulator 210 in an actual circuit (i.e. continuous time) when the same test signal is input. In other words, although the delta-sigma modulator 210 may be affected by the process, voltage and temperature during actual operation, if the calibration process shown in fig. 1 can be used to calibrate the delta-sigma modulator 210 before the wafer is shipped or each operation, the performance of the delta-sigma modulator 210 will be comparable to the designed circuit. The corrected delta-sigma modulator 210 and the discrete-time delta-sigma modulator have an approximate Noise Transfer Function (NTF), that is, NFTc(s) NTFd (z), where NFTc(s) is the noise transfer function of the delta-sigma modulator 210, NTFd (z) is the noise transfer function of the discrete-time delta-sigma modulator, NFTc(s) = 1/(1 DACc(s) · Hc (s)), NFTd (z) = 1/(1 DACd (z) × Hd (z)), DACc(s) is the transfer function of the digital-to-analog converter 218, hc(s) is the transfer function of the loop filter 214, DACd (z) is the transfer function of the discrete-time digital-to-analog converter, and Hd (z) is the transfer function of the discrete-time loop filter.

The aforementioned adjusting the amplification factor of the loop filter 214 can be achieved by adjusting the ratio of the resistors. More specifically, in some embodiments, the summing circuit 430 and the amplifier 420 may be formed by an operational amplifier and a plurality of resistors, and the ratio of the resistors may be adjusted to adjust the amplification factor. The operational amplifier 420 and the summing circuit 430 are well known to those skilled in the art, and therefore will not be described in detail.

It can be seen from fig. 3A that after the calibration method of fig. 1 is completed, the output of the delta-sigma modulator 210 may still be slightly different from the ideal value for the first few operation cycles (as shown in the block area 310), because the integrator 410 in the loop filter 214 causes signal delay. However, if the signal delay of the loop filter 214 is small or the number of stages is low, the delta-sigma modulator 210 can overcome the process, voltage and temperature effects even during the first few operation cycles after the calibration procedure of fig. 1.

In some circuits, in order to overcome the signal delay caused by the loop filter 214, an Extra Loop Delay (ELD) compensation circuit is usually implemented in the delta-sigma modulator, which is the delta-sigma modulator 510 of fig. 5. The delta-sigma modulator 510 is similar to the delta-sigma modulator 210, except that the delta-sigma modulator 510 further comprises an adder circuit 512 and an ELD compensation circuit 514. The present application also provides a calibration method and a corresponding calibration circuit for a delta-sigma modulator operating an extra loop delay compensation circuit. Fig. 5 is a functional block diagram of another embodiment of a calibration circuit for a delta-sigma modulator, and fig. 6 is a flowchart of another embodiment of a calibration method for a delta-sigma modulator according to the present application. The calibration circuit includes an analog-to-digital converter 220, a memory 230, a control circuit 540, and a switch 250. The control circuit 540 may be a circuit with program execution capabilities, such as a central processing unit, microcontroller, microprocessor, or digital signal processor. The memory 230 stores a plurality of program codes or program instructions that are executed by the control circuit 540 to calibrate the sigma-delta modulator 510. The following description refers to fig. 5 and 6.

The calibration process of fig. 6 is similar to that of fig. 1, before the parameters of the loop filter 214 are determined (no in step S610), the control circuit 540 performs steps S110 to S190 to determine the parameters of the loop filter 214, and after the parameters of the loop filter 214 are determined (yes in step S610), the control circuit 540 adjusts the ELD compensation circuit 514 (steps S620 and S630).

FIG. 7 shows a circuit diagram of one embodiment of the ELD compensation circuit 514. The ELD compensation circuit 514 includes a delay circuit 710, a delay circuit 720, and digital-to-

analog converters

730, 740, and 750. The operation of the ELD compensation circuit 514 is well known to those skilled in the art and will not be described herein. The digital-to-

analog converters

730, 740, and 750 are respectively controlled by the control signals Ctrl _ E1, ctrl _ E2, and Ctrl _ E3 (which can be collectively represented by the control signal Ctrl _ E in fig. 5). The control circuit 540 adjusts the currents of the digital-to-analog converters 730-750 in step S620, and more specifically, the control circuit 540 performs step S620 three times before the ELD compensation circuit 514 in fig. 7 is determined as yes in step S630: a first adjustment digital-to-analog converter 730, a second adjustment digital-to-analog converter 740, and a third adjustment digital-to-analog converter 750. When the digital signal Dct is smaller than the predetermined digital signal Ddt, the current of the digital-to-

analog converters

730, 740, and 750 should be increased (as shown in the block area 310 of fig. 3A); conversely, when the digital signal Dct is greater than the predetermined digital signal Ddt, the current of the digital-to-

analog converters

730, 740, and 750 should be reduced. The means for adjusting the current of the digital-to-analog converter is well known to those skilled in the art, and therefore will not be described herein.

After the calibration process of fig. 6 is completed, the delta-sigma modulator 510 behaves more closely to the originally designed circuit (i.e., it can overcome the process, voltage, and temperature effects), and the delta-sigma modulator 510 is modified for the first few cycles.

FIG. 8 is a block diagram of another embodiment of a correction circuit for a delta-sigma modulator. The calibration circuit of fig. 8 is similar to the calibration circuit of fig. 2, with the difference that the calibration circuit of fig. 8 further includes a digital-to-analog converter 810, and the digital-to-analog converter 810 is coupled between the control circuit 240 and the adder circuit 212. In the embodiment of fig. 8, the control circuit 240 outputs the test signal Dp to the digital-to-analog converter 810 instead of the digital-to-analog converter 218, i.e. the digital-to-analog converter 218 does not operate during calibration. The digital-to-analog converter 810 may be designed to have a smaller current than the digital-to-analog converter 218 to avoid saturation (saturrate) or overload (overload) of the loop filter 214 during calibration.

In some embodiments, the current of the digital-to-analog converter 218 or the digital-to-analog converter 810 may be further adjusted down during calibration to further avoid saturation or overload of the loop filter 214. The calibration method of the present application may also use simultaneous equations to find the combination of parameters for the loop filter 214. When the calibration method of the present application is performed, the delta-sigma modulator 210 or the delta-sigma modulator 510 can be operated at full speed or at reduced speed.

Because the implementation details and variations of the method embodiments of the present application can be understood by those of ordinary skill in the art from the disclosure of the apparatus embodiments of the present application, repeated descriptions are omitted herein for the sake of brevity and so as not to obscure the disclosure of the method embodiments and the feasibility of the embodiments. It should be noted that the shapes, sizes, proportions, and sequence of steps of the elements and steps shown in the drawings are illustrative only and are not intended to be limiting, since those skilled in the art will understand the present application.

Although the embodiments of the present application have been described above, these embodiments are not intended to limit the present application, and those skilled in the art can apply variations to the technical features of the present application according to the explicit or implicit contents of the present application, and all such variations may fall within the scope of the patent protection sought by the present application, in other words, the scope of the patent protection sought by the present application should be subject to the claims of the present application.

Description of the reference numerals

210. 510 delta-sigma modulator

212. 430, 512 addition circuit

214. Loop filter

216. Quantizer

218. 730, 740, 750, 810 digital-to-analog converter

220. Analog-to-digital converter

230. Memory device

240. 540 control circuit

250. Switch with a switch body

410-a, 410-b, 410-c, 410-d integrators

420-a, 420-b, 420-c, 420-d amplifier

310. Selection area

ELD extra loop delay

514 ELD compensation circuit

710. 720 delay circuit

Csw, ctrl _ E1, ctrl _ E2, ctrl _ E3, ctrl _ E4 control signals

S110 to S195 and S610 to S630.

Claims

1. A method for calibrating a sigma-delta modulator, the sigma-delta modulator comprising a loop filter, a quantizer and a digital-to-analog converter, the method comprising:

controlling the digital-to-analog converter not to receive the output of the quantizer;

controlling the sigma-delta modulator to stop receiving signals;

inputting a test signal to the digital-to-analog converter;

converting the output of the loop filter into a digital signal by using an analog-to-digital converter;

comparing the digital signal with a preset value; and

and adjusting the loop filter according to the comparison result of the digital signal and the preset value.

2. The calibration method of claim 1, wherein said sigma delta modulator further comprises an additional loop delay compensation circuit, said method further comprising:

adjusting the extra loop delay compensation circuit according to a comparison result of the digital signal and the preset value.

3. The calibration method of claim 1, wherein the step of adjusting the loop filter according to the comparison result of the digital signal and the predetermined value is adjusting a parameter of the loop filter.

4. A correction circuit for a delta-sigma modulator, the delta-sigma modulator comprising a loop filter, a quantizer and a digital-to-analog converter, the correction circuit comprising:

a memory for storing a plurality of program instructions and a default value;

a control circuit, coupled to the memory, for executing the program instructions to calibrate the sigma-delta modulator; and

an analog-to-digital converter coupled between the loop filter and the control circuit;

wherein the calibration procedure of the delta-sigma modulator comprises:

controlling the sigma-delta modulator to stop receiving signals;

inputting a test signal to the digital-to-analog converter;

the analog-digital converter converts the output of the loop filter into a digital signal;

comparing the digital signal with the preset value; and

5. The calibration circuit of claim 4, wherein the sigma delta modulator further comprises an additional loop delay compensation circuit, the calibration procedure of the sigma delta modulator further comprises:

adjusting the extra loop delay compensation circuit according to the comparison result of the digital signal and the preset value.

6. The calibration circuit of claim 4, wherein the step of adjusting the loop filter according to the comparison of the digital signal with the predetermined value is adjusting a parameter of the loop filter.