CN110970364A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN110970364A CN110970364A CN201811150343.0A CN201811150343A CN110970364A CN 110970364 A CN110970364 A CN 110970364A CN 201811150343 A CN201811150343 A CN 201811150343A CN 110970364 A CN110970364 A CN 110970364A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, forming a gate structure on the substrate, forming a source-drain doping layer in the substrate on two sides of the gate structure, forming an interlayer dielectric layer on the substrate exposed out of the gate structure, and covering the source-drain doping layer with the interlayer dielectric layer; forming a first contact hole exposing the source-drain doping layer in the interlayer dielectric layer; forming a metal layer at the bottom of the first contact hole; forming a barrier layer on the metal layer at the bottom of the first contact hole and on the side wall of the first contact hole; after the barrier layer is formed, annealing the substrate to convert the metal layer at the bottom of the first contact hole into a metal silicide layer; after annealing treatment, performing surface treatment on the barrier layer by adopting reducing gas; after the surface treatment, a contact hole plug is formed in the first contact hole. The reducing gas adopted by the surface treatment of the invention can carry out reduction reaction with the oxide layer material on the surface of the barrier layer, thereby improving the performance of the device.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In a semiconductor manufacturing process, after semiconductor devices are formed on a substrate, it is necessary to connect the semiconductor devices together to form a circuit using a plurality of metal layers including interconnection lines and contact hole plugs (CTs) formed in contact holes, the contact hole plugs in the contact holes connecting the semiconductor devices, and the interconnection lines connecting the contact hole plugs on different semiconductor devices to form a circuit. For example: the contact hole plug formed on the fin field effect transistor comprises a contact hole plug electrically connected with the grid structure and a contact hole plug electrically connected with the source drain doping layer.
With the continuous development of integrated circuit manufacturing technology, the critical dimension of the device becomes smaller, and accordingly, many problems occur. For example, the contact resistance between the contact hole plug and the source-drain doping layer is increased, so that the response speed of the device is reduced, signals are delayed, the driving current is reduced, and the performance of the semiconductor device is degraded.
In order to reduce the contact resistance between the contact hole plug and the source-drain doped layer, a metal Silicide (Silicide) process is introduced, wherein the metal Silicide has lower resistivity, so that the contact resistance can be obviously reduced, and the driving current is improved.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of a device.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a gate structure is formed on the substrate, active drain doping layers are formed in the substrate on two sides of the gate structure, an interlayer dielectric layer is formed on the substrate exposed out of the gate structure, and the interlayer dielectric layer covers the source drain doping layers; forming a first contact hole exposing the source-drain doping layer in the interlayer dielectric layer; forming a metal layer at the bottom of the first contact hole; forming a barrier layer on the metal layer at the bottom of the first contact hole and on the side wall of the first contact hole; after the barrier layer is formed, annealing the substrate, and converting the metal layer at the bottom of the first contact hole into a metal silicide layer; after the annealing treatment, performing surface treatment on the barrier layer by adopting reducing gas; and forming a contact hole plug in the first contact hole with the barrier layer after the surface treatment.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the grid structure is positioned on the substrate; the source-drain doping layer is positioned in the substrate at two sides of the grid structure; the interlayer dielectric layer is positioned on the substrate exposed out of the grid structure and covers the source-drain doping layer; the first contact hole is positioned in the interlayer dielectric layer and exposes the source-drain doping layer; the metal silicide layer is positioned at the bottom of the first contact hole; the barrier layer is positioned on the metal silicide layer at the bottom of the first contact hole and on the side wall of the first contact hole, the barrier layer is subjected to surface treatment after the metal silicide layer is formed, and gas adopted by the surface treatment is reducing gas; and the contact hole plug is positioned in the first contact hole and is in contact with the barrier layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
after the metal silicide layer is formed, the surface of the barrier layer is treated by reducing gas; in the process of forming the semiconductor structure, materials with partial thickness on the surface of the barrier layer are easily converted into an oxide layer, and the gas adopted by the surface treatment can perform reduction reaction with the materials of the oxide layer, so that the materials of the oxide layer are reduced into the materials of the barrier layer; compared with the oxide layer, the density of the barrier layer is higher, so that in the subsequent process of forming the contact hole plug, the barrier layer has higher barrier property to easily diffused atoms in reaction gas used for forming the contact hole plug, the surface flatness of the barrier layer after surface treatment is higher, the forming quality of the contact hole plug in the first contact hole can be correspondingly improved, and the performance of a device is improved.
In an alternative, in the step of forming the barrier layer, the barrier layer is a nitrogen-containing layer (for example, the material of the barrier layer is TiN or TaN), and therefore, in the step of performing the surface treatment on the barrier layer, the reducing gas is a gas containing a nitrogen element and a hydrogen element; in the case where the material of the partial thickness of the barrier layer surface is converted into an oxide layer (for example, when the material of the barrier layer is TiN, the material of the partial thickness of the barrier layer surface is converted into TiO2) Through the surface treatment, the hydrogen element reacts with the oxygen element in the oxide layer to form water vapor, the water vapor is discharged out of the surface treatment chamber in a gas mode, and the nitrogen element reacts with the rest elements in the oxide layer, so that the material of the oxide layer is reduced to the material of the barrier layer, the material and the thickness of the barrier layer can meet the process requirements, and the performance of the device is improved.
Drawings
Fig. 1 to 2 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
fig. 3 to fig. 11 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of the devices currently still needs to be improved. There are reasons why the performance of a semiconductor structure is still to be improved when analyzed in conjunction with a method of forming the semiconductor structure. Referring to fig. 1 to 2, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate (not labeled) is provided, and the substrate includes a substrate 10 and a fin portion 11 protruding from the substrate 10, a gate structure 12 crossing the fin portion 11 is formed on the substrate 10, an active drain doping layer 13 is formed in the fin portion 11 on both sides of the gate structure 12, an interlayer dielectric layer 14 is formed on the substrate 10 exposed by the gate structure 12, the interlayer dielectric layer 14 covers the source drain doping layer 13 and exposes the top of the gate structure 12, and a contact hole 15 exposing the source drain doping layer 13 is formed in the interlayer dielectric layer 14 on both sides of the gate structure 12.
Referring to fig. 2, a metal layer 16 is formed on the bottom and sidewalls of the contact hole 15, the metal layer 16 also covering the top of the interlayer dielectric layer 14; a barrier layer (barrier layer)17 is formed on the metal layer 16.
The subsequent process further comprises: annealing the substrate to enable the metal layer 16 at the bottom of the contact hole 15 to react with the source-drain doping layer 13, and converting the metal layer 16 at the bottom of the contact hole 15 into a metal silicide layer; after the metal silicide layer is formed, a conductive material is filled into the contact hole 15, thereby forming a contact hole plug in the contact hole 15.
Currently, in order to improve the leakage current problem caused by the piping defect, the material of the metal silicide layer is usually TiSi, so the material of the metal layer 16 is usually Ti, and the material of the barrier layer is usually TiN. However, in the actual process, a certain waiting time (Q-time) is required between each step (step), so that after the barrier layer 17 is formed and before the contact hole plug is formed, the barrier layer 17 is prone to surface oxidation due to an excessively long waiting time, and during the annealing process for forming the metal silicide layer, the surface of the barrier layer 17 is oxidized more frequently and more highly under the high-temperature environment of the annealing process, so that the material with partial thickness on the surface of the barrier layer 17 is converted into an oxide layer, for example, when the material of the barrier layer 17 is TiN, the material with partial thickness on the surface of the barrier layer 17 is converted into TiO2。
After the surface of the barrier layer 17 is oxidized, the interface of the barrier layer 17 is damaged, the surface flatness of the formed oxide layer is poor, when the contact hole 15 is filled with a conductive material, the nucleation difficulty of the conductive material is correspondingly improved, and a void (void) defect is easily formed in the contact hole plug; the formation of the oxide layer also reduces the thickness of the remaining barrier layer 17, and compared with the barrier layer 17, the density of the oxide layer is poorer, so that easily diffusible atoms (for example, F atoms) in the reaction gas used for forming the conductive material easily penetrate through the barrier layer 17 and enter the metal layer 16, the metal silicide layer or the interlayer dielectric layer 14; in conclusion, after the surface of the barrier layer 17 is oxidized, the performance of the device is easily reduced.
In order to solve the technical problem, in the embodiment of the invention, after the metal silicide layer is formed, the barrier layer is subjected to surface treatment by using reducing gas; in the process of forming the semiconductor structure, the surface of the barrier layer is easy to oxidize, and the material of the oxide layer is reduced into the material of the barrier layer by carrying out surface treatment on the barrier layer by adopting reducing gas; compared with the oxide layer, the density of the barrier layer is higher, so that in the subsequent process of forming the contact hole plug, the barrier layer has higher barrier property to easily diffused atoms in reaction gas used for forming the contact hole plug, the surface flatness of the barrier layer after surface treatment is higher, the forming quality of the contact hole plug in the first contact hole can be correspondingly improved, and the performance of a device is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 3 to fig. 11 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 3, a substrate (not labeled) is provided, a gate structure 120 is formed on the substrate, a source-drain doping layer 140 is formed in the substrate on two sides of the gate structure 120, an interlayer dielectric layer 102 is formed on the substrate exposed by the gate structure 120, and the source-drain doping layer 140 is covered by the interlayer dielectric layer 102.
In this embodiment, the base includes a substrate 100 and a plurality of discrete fins 110 on the substrate 100. In other embodiments, when the semiconductor structure formed is a planar transistor structure, the base is correspondingly a planar substrate.
The substrate 100 may be used to form one or both of an NMOS device and a PMOS device. In this embodiment, the substrate 100 includes a first region I for forming an NMOS device and a second region II for forming a PMOS device.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the initial substrate may also be a silicon-on-insulator substrate or other types of substrates such as a germanium-on-insulator substrate.
In this embodiment, the material of the fin portion 110 is the same as that of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.
Accordingly, in the present embodiment, the gate structure 120 crosses over the fin 110 and covers a portion of the top and a portion of the sidewall of the fin 110; the source-drain doping layer 140 is formed in the fin portion 110 at two sides of the gate structure 120.
In this embodiment, the gate structure 120 is a metal gate structure, and the gate structure 120 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) on the gate dielectric layer.
The gate dielectric layer is made of a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the gate dielectric layer is made of HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3And the like.
In this embodiment, the material of the gate electrode layer is W. In other embodiments, the material of the gate electrode layer may also be Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.
In other embodiments, the gate structure may also be a polysilicon gate structure, the gate structure includes a gate layer, and the gate layer is made of polysilicon.
The substrate 100 comprises a first region I for forming an NMOS device and a second region II for forming a PMOS device, so that the source-drain doping layer 140 of the first region I is made of Si or SiC doped with N-type ions, the N-type ions are P, As or Sb, the source-drain doping layer 140 of the second region II is made of Si or SiGe doped with P-type ions, and the P-type ions are B, Ga or In.
In this embodiment, the source-drain doping layer 140 of the first region I is made of Si doped with P ions, and the source-drain doping layer 140 of the second region II is made of SiGe doped with B ions.
According to the process requirement, the source-drain doping layer 140 may be square, Sigma-shaped, or U-shaped along the direction perpendicular to the sidewall of the gate structure 120. In this embodiment, the source-drain doping layer 140 of the first region I is square, and the source-drain doping layer 140 of the second region II is Sima-shaped.
The interlayer dielectric layer 102 is used for isolating adjacent devices. The interlayer dielectric layer 102 is made of an insulating material. In this embodiment, the interlayer dielectric layer 102 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of a dielectric material such as silicon nitride or silicon oxynitride.
In this embodiment, the interlayer dielectric layer 102 also covers the top of the gate structure 120. In other embodiments, the top of the interlayer dielectric layer may be flush with the top of the gate structure according to practical situations.
In this embodiment, the gate structure 120 is formed by a high-k back metal gate (high-k back metal gate). In other embodiments, the gate structure may also be formed by first raising k and then forming a metal gate (high k first metal gate first) or by first raising k and then forming a metal gate (high k first metal gate first).
It should be further noted that a sidewall 130 is formed on a sidewall of the gate structure 120. The sidewall spacer 130 is used to define a formation region of the source-drain doping layer 140, and the sidewall spacer 130 can also protect the sidewall of the gate structure 120 in a subsequent process.
The material of the sidewall 130 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride, and the sidewall 130 may have a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacer 130 has a single-layer structure, and the material of the sidewall spacer 130 is silicon nitride.
In this embodiment, an isolation structure 101 is formed on the substrate 100 where the fin 110 is exposed, the isolation structure 101 covers a portion of a sidewall of the fin 110, and a top of the isolation structure 101 is lower than a top of the fin 110.
The isolation structure 101 is used as a Shallow Trench Isolation (STI) structure, and the isolation structure 101 is used for isolating adjacent devices. In this embodiment, the isolation structure 101 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
Referring to fig. 4, a first contact hole 112 exposing the source-drain doping layer 140 is formed in the interlayer dielectric layer 102.
The first contact hole 112 is used for providing a spatial position for the subsequent formation of a contact hole plug electrically connected with the source-drain doping layer 140.
Specifically, the interlayer dielectric layer 102 above the source-drain doping layer 140 is etched by using a dry etching process. The dry etching method is favorable for improving the etching efficiency of forming the first contact hole 112, and the dry etching process has the characteristic of anisotropic etching, so that the improvement of the appearance quality of the first contact hole 112 is also favorable.
With reference to fig. 5, after the first contact hole 112 is formed, the method further includes: a Pre-amorphization (PAI) process 141 is performed on the source/drain doping layer 140 exposed by the first contact hole 112.
Through the pre-amorphization 141, the source-drain doping layer 140 with a partial thickness at the bottom of the first contact hole 112 is converted into an amorphous layer (not shown), so that the formation quality and quality uniformity of a subsequent metal silicide layer are improved, and the performance of the device is improved. Moreover, after the source-drain doping layer 140 material with the thickness of the bottom part of the first contact hole 112 is converted into the amorphous layer, when the metal silicide layer is formed by annealing treatment, the process time of the annealing treatment or the process temperature is reduced.
In this embodiment, the pre-amorphization 141 is an ion implantation process. Specifically, neutral ions with large atomic mass are injected into the source-drain doping layer 140 exposed out of the first contact hole 112, so that lattice damage occurs to the source-drain doping layer 140 with a partial thickness, and the source-drain doping layer 140 is converted into an amorphous layer.
Therefore, in this embodiment, the implanted ions of the ion implantation process are Ge ions. In other embodiments, the implanted ions of the ion implantation process may also be Si ions.
The implantation energy of the ion implantation process is not too small or too large. The thickness of the amorphous layer can be controlled by implantation energy, if the implantation energy is too small, the thickness of the amorphous layer is correspondingly too small, and the effect of improving the formation quality and quality uniformity of a subsequent metal silicide layer is correspondingly reduced; if the implantation energy is too large, problems such as implantation contamination and particle scattering are easily caused, and the thickness of the amorphous layer is also too large, which may adversely affect the quality and performance of the source/drain doping layer 140, thereby degrading the device performance. For this reason, in this embodiment, the implantation energy of the ion implantation process is 0.5KeV to 3.0KeV
The implantation dosage of the ion implantation process is not required to be too small or too large. If the injection dosage is too small, the damage degree of the crystal lattice of the source-drain doping layer 140 is easily reduced, and the effects of improving the formation quality and quality uniformity of the subsequent metal silicide layer are correspondingly deteriorated; if the implantation dosage is too large, the content of Ge in the source-drain doping layer 140 is easily too high, thereby affecting the formation quality of the subsequent metal silicide layer. For this reason, in this embodiment, the implantation dose of the ion implantation process is 1E14atom/cm2To 3E15atom/cm2。
Referring to fig. 6 in combination, after the pre-amorphization 141 (shown in fig. 5), the method further includes: and forming a second contact hole 122 in the interlayer dielectric layer 102 above the gate structure 120, wherein the second contact hole 122 exposes the top of the gate structure 120.
The second contact hole 122 is used to provide a space location for the subsequent formation of a contact hole plug electrically connected to the gate structure 120.
Specifically, the step of forming the second contact hole 122 includes: forming a filling layer (not shown) in the first contact hole 112, wherein the filling layer also covers the top of the interlayer dielectric layer 102; forming a photoresist layer (not shown) on the filling layer; etching the filling layer 210 and the interlayer dielectric layer 102 above the gate structure 120 by using the photoresist layer as a mask, and forming the second contact hole 122 in the interlayer dielectric layer 102 above the gate structure 120; after the second contact hole 122 is formed, the photoresist layer and the filling layer are removed.
In this embodiment, the material of the filling layer may be an organic dielectric material, a bottom anti-reflection layer material, a deep ultraviolet light absorbing silicon oxide material, or amorphous carbon.
In this embodiment, the second contact hole 122 is formed after the pre-amorphization 141. In the process of the pre-amorphization 141, the interlayer dielectric layer 102 protects the gate structure 120, so that the pre-amorphization 141 does not affect the top of the gate structure 120, and the process complexity of the pre-amorphization 141 is also simplified.
Referring to fig. 7, a metal layer 210 is formed at the bottom of the first contact hole 112.
The metal layer 210 is used to provide a process base for the subsequent formation of a metal silicide layer.
In this embodiment, the metal layer 210 is also formed on the sidewall of the first contact hole 112. The metal layer 210 is also used as an adhesion layer, and the metal layer 210 has good adhesion on the bottom and the side wall of the first contact hole 112, so that the adhesion of a subsequent barrier layer in the first contact hole 112 is improved.
In this embodiment, the metal layer 210 is made of Ti. The Ti material is good in adhesion with silicon and silicon oxide, so that the adhesion of the metal layer 210 in the first contact hole 112 is favorably improved by selecting the Ti material, the metal layer 210 at the bottom of the first contact hole 112 is converted into a metal silicide layer after the metal layer 210 reacts with the source-drain doping layer 140, the formed metal silicide layer is made of TiSi correspondingly, the contact resistance between a subsequent contact hole plug and the source-drain doping layer 140 can be obviously reduced, and the tubular drilling defect of the metal silicide is favorably improved.
It should be noted that a second contact hole 122 exposing the top of the gate structure 120 is further formed in the interlayer dielectric layer 102, and therefore the metal layer 210 is further formed on the bottom and the sidewall of the second contact hole 122.
In this embodiment, the metal layer 210 is formed by a physical vapor deposition process, so that the metal layer 210 conformally covers the bottom and the sidewall of the first contact hole 112 and the bottom and the sidewall of the second contact hole 122, and the metal layer 210 also covers the top of the interlayer dielectric layer 102. In other embodiments, the process of forming the metal layer may also be a chemical vapor deposition process or an atomic layer deposition process.
With continued reference to fig. 7, a barrier layer 220 is formed on the metal layer 210 at the bottom of the first contact hole 112 and on the sidewalls of the first contact hole 112.
The barrier layer 220 functions to: in one aspect, the barrier layer 220 is a reactive gas (e.g., WF) for subsequent formation of contact plugs6) The easy-to-diffuse atoms in the contact hole plug have a blocking effect, so that the easy-to-diffuse atoms are prevented from entering the metal layer 210 or the interlayer dielectric layer 102, and the reaction gas is prevented from reacting with the source-drain doping layer 140 or the formed metal silicide layer, so that the contact resistance between the subsequent contact hole plug and the source-drain doping layer 140 is favorably reduced; on the other hand, when the contact hole plug is formed later, the barrier layer 220 may function as a contact hole liner layer, thereby improving adhesion of a conductive material in the first contact hole 112.
In this embodiment, the blocking layer 220 is a nitrogen-containing layer, which is beneficial to improving the compactness of the blocking layer 220. Specifically, the material of the barrier layer 220 is TiN. The blocking effect of TiN is good, and the adhesion of the conductive material in the first contact hole 112 can be obviously improved; in addition, the materials of the barrier layer 220 and the metal layer 210 both contain Ti, which is advantageous for improving the adhesion of the barrier layer 220 on the surface of the metal layer 210. In other embodiments, the material of the barrier layer may also be TaN.
The thickness (not labeled) of the barrier layer 220 should not be too small, nor too large. If the thickness is too small, the blocking effect of the blocking layer 220 is relatively poor, and the step coverage of the blocking layer 220 is also easily reduced; since the material of the blocking layer 220 also has a relatively high resistance, if the thickness is too large, the contact resistance between the subsequent contact hole plug and the source-drain doping layer 140 may be increased. For this reason, in the present embodiment, the thickness of the barrier layer 220 is 1nn to 5 nm.
In this embodiment, the metal layer 210 is further formed on the bottom and the sidewall of the second contact hole 122, and therefore the barrier layer 220 is further formed on the metal layer 210 at the bottom of the second contact hole 122 and on the metal layer 210 at the sidewall of the second contact hole 122.
Specifically, the barrier layer 220 is formed using a physical vapor deposition process, and thus, the barrier layer 220 conformally covers the surface of the metal layer 210. In other embodiments, the process of forming the metal layer may also be a chemical vapor deposition process, an atomic layer deposition process, or a metal organic chemical vapor deposition process.
It should be noted that the deposition of the metal layer 210 and the barrier layer 220 is completed in steps by two deposition processes in this embodiment. In other embodiments, the metal layer and the barrier layer may be formed in the same deposition process, and the barrier layer may be formed on the metal layer by adding nitrogen gas to the reaction gas at a later stage of the deposition process.
Referring to fig. 8 and 9 in combination, fig. 8 is a schematic structural diagram based on fig. 7, and fig. 9 is a partially enlarged view within a dashed-line frame a in fig. 8, after the barrier layer 220 is formed, the substrate (not labeled) is subjected to an annealing process 142 to convert the metal layer 210 at the bottom of the first contact hole 112 into the metal silicide layer 150.
The metal silicide layer 150 is used to reduce contact resistance between the subsequent contact hole plug and the source-drain doping layer 140.
In this embodiment, in the annealing process 142, the metal layer 210 reacts with the material of the source/drain doping layer 140, so as to convert the metal layer 210 into the metal silicide layer 150. Specifically, in the annealing process 142, Ti atoms in the metal layer 210 and Si atoms in the source-drain doping layer 140 are diffused and react with each other, so that the metal silicide layer 150 made of TiSi is formed on the top surface of the source-drain doping layer 140.
In this embodiment, the annealing treatment is laser annealing treatment. In other embodiments, the annealing process may also be a rapid thermal annealing process. In order to ensure the reaction effect of the metal layer 210 and the source-drain doping layer 140, the thickness and quality of the metal silicide layer 150 meet the process requirements, and the probability of adverse effect on the device performance is reduced, wherein the annealing temperature is 600 to 1000 ℃.
In this embodiment, since the metal layer 210 only reacts with the source-drain doping layer 140, after the annealing treatment 142, only the metal layer 210 at the bottom of the first contact hole 112 is converted into the metal silicide layer 150, and the metal layer 210 at the sidewall of the first contact hole 112, the bottom and the sidewall of the second contact hole 122, and the top of the interlayer dielectric layer 102 is retained. In other embodiments, when the gate structure is a polysilicon gate, in the annealing step, the metal layer at the bottom of the second contact hole may also react with the gate structure, so as to convert the metal layer at the top of the gate structure into the metal silicide layer.
Note that, as shown in fig. 9, after the barrier layer 220 is formed, a certain waiting time is required between each step before the annealing treatment 142, and thus the barrier layer is formedAfter the barrier layer 220, the barrier layer 220 is prone to surface oxidation due to long waiting time, and the probability and degree of oxidation of the surface of the barrier layer 220 are higher under the high temperature environment of the annealing treatment 142, so that the material of the partial thickness of the surface of the barrier layer 220 is converted into the oxide layer 225. In this embodiment, the barrier layer 220 is made of TiN, and the oxide layer 225 is made of TiO2。
As can be seen from the foregoing, after the surface of the barrier layer 220 is oxidized, the quality of the contact hole plug formed subsequently is easily reduced, and the barrier effect of the barrier layer 220 is also reduced, which easily results in the performance degradation of the device.
For this, referring to fig. 10, after the annealing process 142 (shown in fig. 8), the barrier layer 220 is subjected to a surface treatment 250 using a reducing gas.
The reducing gas used in the surface treatment 250 is capable of performing a reduction reaction with the material of the oxide layer 225 (shown in fig. 9), so as to reduce the material of the oxide layer 225 to the material of the barrier layer 220; compared with the oxide layer 225, the density of the barrier layer 220 is higher, so that in the subsequent process of forming the contact hole plug, the barrier layer 220 has higher barrier property to easily diffused atoms in the reaction gas used for forming the contact hole plug, and the surface flatness of the barrier layer 220 after the surface treatment 250 is higher, so that the forming quality of the contact hole plug in the first contact hole 112 and the second contact hole 122 can be correspondingly improved, and further the performance of the device can be improved.
In this embodiment, the barrier layer 220 is a nitrogen-containing layer, and correspondingly, in the step of performing the surface treatment 250 on the barrier layer 220, the reducing gas is a gas containing a nitrogen element and a hydrogen element.
In the surface treatment 250 process, the hydrogen element reacts with the oxygen element in the oxide layer 225 to form water vapor, and the water vapor is discharged out of the chamber of the surface treatment 250 in a gas manner, and the nitrogen element reacts with the remaining elements in the oxide layer 225, so that the material of the oxide layer 225 is reduced to the material of the barrier layer 220, and further, the material and the thickness of the barrier layer 220 can meet the process requirements, so that the performance of the device is improved.
Moreover, after the hydrogen element reacts with the oxygen element in the oxide layer 225 to form water vapor, the water vapor is exhausted out of the surface treatment chamber 250 in a gas manner, and accordingly, the formation of byproducts on the surface of the barrier layer 220 can be avoided, and the process risk is low.
Specifically, in the surface treatment 250, after hydrogen reacts with oxygen in the oxide layer 225, nitrogen reacts with titanium in the oxide layer 225, so that TiO on the surface of the remaining barrier layer 220 is removed2The material is converted to a TiN material and the oxide layer 225 is removed accordingly.
For this reason, in the present embodiment, after the surface treatment 250, the thickness of the barrier layer 220 is still 1nn to 5nm, and the thickness of the barrier layer 220 can ensure that the performance of the barrier layer 220 meets the process requirements.
In this embodiment, the reducing gas used for the surface treatment 250 is NH3。NH3The oxide layer 225 can be reduced to the material of the barrier layer 220 by using a reaction gas, which is beneficial to reducing the process cost and simplifying the process complexity.
In other embodiments, the surface treatment may be performed by using a mixed gas containing a nitrogen element and a hydrogen element. For example: the reducing gas is N2And NH3The mixed gas of (3); alternatively, the reducing gas is H2And NH3The mixed gas of (3); alternatively, the reducing gas is H2And N2The mixed gas of (1).
Specifically, the step of surface treating 250 the barrier layer 220 includes: the barrier layer 220 is plasma treated with a reducing gas. In the plasma treatment process, the reducing gas is ionized under the excitation of the excitation source to generate plasma, and the plasma bombards the surface of the oxide layer 225, so that the chemical bonds of the material of the oxide layer 225 can be damaged, the reduction reaction of the oxide layer 225 is performed, and the process efficiency is high. Wherein, the excitation source can be a microwave source or a radio frequency source.
In this embodiment, the reaction gas for plasma treatment is NH3. Wherein NH3The gas flow rate should not be too small, nor too large. If the gas flow rate is too small, the plasma density is low, which not only reduces the effect of the surface treatment 250, makes it difficult to reduce the material of the oxide layer 225 to the material of the barrier layer 220, but also easily reduces the uniformity of the reduction reaction; if the gas flow is too large, the reduction reaction speed is too fast, so that the process stability is easily reduced, the distribution uniformity of the plasma is also easily reduced, and the uniformity of the reduction reaction is also reduced correspondingly. For this purpose, in this embodiment, NH3The gas flow rate of (a) is 100 to 1000 standard ml/min.
In this embodiment, the excitation source for plasma processing is a radio frequency source. Wherein, the radio frequency power is not suitable to be too small and not suitable to be too large. If the radio frequency power is too low, the dissociation of the reaction gas is easy to be insufficient, so that the reduction reaction is insufficient, and the material of the oxide layer 225 is difficult to be reduced into the material of the barrier layer 220; if the rf power is too high, plasma damage is easily caused, thereby adversely affecting device performance. For this reason, in this embodiment, the rf power is 200 kw to 2000 kw.
The process temperature of the plasma treatment is not suitable to be too low or too high. If the process temperature is too low, the rate of the reduction reaction is easily reduced, and it is even difficult to reduce the material of the oxide layer 225 to the material of the barrier layer 220; if the process temperature is too high, the device performance is easily adversely affected. For this reason, in this embodiment, the process temperature of the plasma treatment is 100 to 500 degrees celsius.
The process time of the plasma treatment is not short enough or long enough. If the process time is too short, the reduction reaction is easily insufficient, and it is difficult to reduce the material of the oxide layer 225 to the material of the barrier layer 220; if the process time is too long, the process time is wasted, thereby reducing the manufacturing efficiency. For this reason, in the present embodiment, the process time of the plasma treatment is 10 seconds to 5 minutes.
In the actual process, the parameters of the plasma treatment are reasonably set and matched with each other, so that the reduction reaction is fully carried out and the generation of side effects is reduced.
Referring to fig. 11, after the surface treatment 250 (shown in fig. 10), a contact hole plug 240 is formed in the first contact hole 112 (shown in fig. 10) in which the barrier layer 220 is formed.
The contact hole plug 240 is electrically connected to the source-drain doping layer 140, and is used for electrically connecting the source-drain doping layer 140 to an external circuit.
In this embodiment, the material of the contact hole plug 240 is W. W has the advantages of high melting point, good thermal stability, good conductivity, strong step coverage capability, strong electromigration resistance and the like, and the performance of the device is favorably improved by selecting the W material, and moreover, the thermal expansion coefficient of W is close to that of Si, so that the stress in the contact hole plug 240 is favorably reduced. In other embodiments, the material of the contact hole plug may also be a conductive material such as Al, Cu, Ag, or Au.
In the present embodiment, the process of forming the contact hole plug 240 in the first contact hole 112 includes a chemical vapor deposition process. By using the chemical vapor deposition process, it is advantageous to improve the step coverage of the conductive material used to form the contact hole plug 240 and to reduce the stress in the contact hole plug 240. In other embodiments, the contact hole plug may also be formed through a physical vapor deposition process, a sputtering process, or an electroplating process.
Specifically, the step of forming the contact hole plug 240 includes: filling a conductive material into the first contact hole 112, wherein the conductive material also covers the top of the interlayer dielectric layer 102; and performing planarization treatment on the conductive material, removing the conductive material higher than the top of the interlayer dielectric layer 102, and keeping the conductive material in the first contact hole 112 as the contact hole plug 240.
Accordingly, the process of filling the first contact hole 112 with the conductive material is a chemical vapor deposition process. Specifically, the material of the contact hole plug 240 is W, and thus, the reaction gas of the chemical vapor deposition process includes WF6、B2H6And H2。
Because the interface quality of the barrier layer 220 is good, when a conductive material is filled into the first contact hole 112, nucleation of the conductive material on the surface of the barrier layer 220 is easily realized, so that the formation quality and the adhesion of the contact hole plug 240 in the first contact hole 112 are improved; the density of the barrier layer 220 is high, and the thickness of the barrier layer 220 can meet the process requirements, so that the barrier effect of the barrier layer 220 is guaranteed; in conclusion, the performance of the device formed by the present embodiment can be improved.
In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material, so that the top of the contact hole plug 240 is flush with the top of the interlayer dielectric layer 102.
When the first contact hole 112 is filled with a conductive material, the conductive material is also filled in the second contact hole 122, and thus the contact hole plug 240 is also formed in the second contact hole 122. Wherein the contact hole plug 240 in the second contact hole 122 is used for electrically connecting the gate structure 120 with an external circuit.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 11, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate (not labeled); a gate structure 120 on the substrate; the source-drain doping layer 140 is positioned in the substrate at two sides of the gate structure 120; the interlayer dielectric layer 102 is positioned on the substrate exposed out of the gate structure 120, and the interlayer dielectric layer 102 covers the source-drain doping layer 140; a first contact hole 112 (shown in fig. 6) located in the interlayer dielectric layer 102 and exposing the source-drain doping layer 140; a metal silicide layer 150 at the bottom of the first contact hole 112; a barrier layer 220 located on the metal silicide layer 150 at the bottom of the first contact hole 112 and on the sidewall of the first contact hole 112, wherein the barrier layer 220 is subjected to a surface treatment after the metal silicide layer 150 is formed, and a gas used for the surface treatment is a reducing gas; a contact hole plug 240 located in the first contact hole 112 and contacting the barrier layer 220.
In this embodiment, the base includes a substrate 100 and a plurality of discrete fins 110 on the substrate 100. In other embodiments, when the semiconductor structure is a planar transistor structure, the base is a planar substrate, respectively.
The semiconductor structure may be one or both of an NMOS device and a PMOS device. In this embodiment, the substrate 100 includes a first region I in which NMOS devices are formed and a second region II in which PMOS devices are formed.
In this embodiment, the substrate 100 is made of silicon, and the fin 110 is also made of silicon. For the detailed description of the substrate 100 and the fin 110, reference may be made to the corresponding description in the foregoing embodiments, and further description is omitted here.
In addition, the semiconductor structure further includes: and the isolation structure 101 is located on the substrate 100 where the fin portion 110 is exposed, the isolation structure 101 covers a part of the sidewall of the fin portion 110, and the top of the isolation structure 101 is lower than the top of the fin portion 110. The isolation structure 101 is used to isolate adjacent devices. In this embodiment, the isolation structure 101 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
The gate structure 120 crosses the fin 110 and covers a portion of the top and a portion of the sidewalls of the fin 110. In this embodiment, the gate structure 120 is a metal gate structure, and therefore the gate structure 120 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) on the gate dielectric layer.
In this embodiment, the gate dielectric layer is made of HfO2The material of the gate electrode layer is W. In other embodiments, the gate structure may also be a polysilicon gate structure, the gate structure includes a gate layer, and the gate layer is made of polysilicon. For the specific description of the gate structure 120, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated herein.
A sidewall spacer 130 is formed on the sidewall of the gate structure 120. The sidewall spacer 130 is used to define a formation region of the source-drain doping layer 140, and the sidewall spacer 130 is further used to protect the sidewall of the gate structure 120 during the formation process of the semiconductor structure. In this embodiment, the sidewall spacer 130 is made of silicon nitride. For the specific description of the side wall 130, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated herein.
In this embodiment, the source-drain doping layer 140 is formed in the fin portion 110 on both sides of the gate structure 120.
The substrate 100 includes a first region I formed with an NMOS device and a second region II formed with a PMOS device, so that the source-drain doping layer 140 of the first region I is made of Si or SiC doped with N-type ions, the N-type ions are P, As or Sb, the source-drain doping layer 140 of the second region II is made of Si or SiGe doped with P-type ions, and the P-type ions are B, Ga or In.
In this embodiment, the source-drain doping layer 140 of the first region I is made of Si doped with P ions, and the source-drain doping layer 140 of the second region II is made of SiGe doped with B ions.
According to the actual process requirement, the source-drain doping layer 140 may be square, Sigma-shaped, or U-shaped along the direction perpendicular to the sidewall of the gate structure 120. In this embodiment, the source-drain doping layer 140 of the first region I is square, and the source-drain doping layer 140 of the second region II is Sima-shaped.
The interlayer dielectric layer 102 is used for isolating adjacent devices. The interlayer dielectric layer 102 is made of an insulating material. In this embodiment, the interlayer dielectric layer 102 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of a dielectric material such as silicon nitride or silicon oxynitride.
In this embodiment, the interlayer dielectric layer 102 also covers the top of the gate structure 120. In other embodiments, the top of the interlayer dielectric layer may be flush with the top of the gate structure according to process requirements.
The first contact hole 112 is used for providing a spatial position for the formation of the contact hole plug 240, and the metal silicide layer 150 is located on the surface of the source-drain doping layer 140 exposed by the first contact hole 112 and used for reducing the contact resistance between the contact hole plug 240 and the source-drain doping layer 140.
In this embodiment, the material of the metal silicide layer 150 is TiSi, and by selecting the TiSi material, the contact resistance between the contact hole plug 240 and the source-drain doping layer 140 can be significantly reduced, and the tubular drilling defect of the metal silicide can be improved.
In this embodiment, the semiconductor structure further includes: and the metal layer 210 is positioned on the side wall of the first contact hole 112, namely, between the barrier layer 220 and the interlayer dielectric layer 102. In the forming process of the semiconductor structure, the metal layer 210 is formed by a deposition process, so that after the metal layer 210 is formed, the metal layer 210 is located at the bottom and on the side wall of the first contact hole 112, and the metal layer 210 at the bottom of the first contact hole 112 reacts with the source drain doping layer 140 under the action of annealing treatment, so that the metal layer 210 at the bottom of the first contact hole 112 is converted into the metal silicide layer 150, and the metal layer 210 on the side wall of the first contact hole 112 is retained.
In this embodiment, the material of the metal silicide layer 150 is TiSi, and the material of the metal layer 210 is Ti accordingly. The adhesion between Ti and silicon, silicon oxide is better, so the adhesion of the metal layer 210 on the sidewall of the first contact hole 112 is better.
Accordingly, in the present embodiment, the barrier layer 220 is located on the metal silicide layer 150 at the bottom of the first contact hole 112 and on the metal layer 210 at the sidewall of the first contact hole 112. Wherein the metal layer 210 is also used as an adhesion layer to improve the adhesion of the barrier layer 220 in the first contact hole 112.
In this embodiment, the blocking layer 220 is a nitrogen-containing layer, which is beneficial to improving the compactness of the blocking layer 220.
Specifically, the material of the barrier layer 220 is TiN. TiN has a good barrier effect, and both the barrier layer 220 and the metal layer 210 contain Ti, which is also beneficial to improving the adhesion of the barrier layer 220 on the surface of the metal layer 210. In other embodiments, the material of the barrier layer may also be TaN.
The thickness of the barrier layer 220 should not be too small, nor too large. If the thickness of the barrier layer 220 is too small, the barrier effect of the barrier layer 220 is relatively poor, and the step coverage of the barrier layer 220 is also easily reduced; since the material of the blocking layer 220 also has a relatively high resistance, if the thickness of the blocking layer 220 is too large, the contact resistance between the contact hole plug 240 and the source/drain doping layer 140 may be increased. For this reason, in the present embodiment, the thickness of the barrier layer 220 is 1nn to 5 nm.
In this embodiment, the barrier layer 220 is subjected to a surface treatment after the formation of the metal silicide layer 150, and a gas used for the surface treatment is a reducing gas.
In the process of forming the semiconductor structure, a certain waiting time is required between each step, so that after the barrier layer 220 is formed, the problem of surface oxidation of the barrier layer 220 is easily caused due to the excessively long waiting time, and in the process of forming the metal silicide layer 150, under the high-temperature environment of annealing treatment, the probability and degree of surface oxidation of the barrier layer 220 are higher, so that a material with a partial thickness on the surface of the barrier layer 220 is converted into an oxide layer, and after the surface oxidation of the barrier layer 220, the quality of the contact hole plug 240 is easily reduced, and the blocking effect of the barrier layer 220 is also reduced, so that the performance of the device is easily reduced.
The reducing gas used for the surface treatment can perform a reduction reaction with the oxide layer material, so as to reduce the oxide layer material into the material of the barrier layer 220; compared with an oxide layer, the density of the barrier layer 220 is higher, so that the barrier effect of the barrier layer 220 is better, the surface flatness of the surface-treated barrier layer 220 is higher, the formation quality of the contact hole plug 240 in the first contact hole 112 can be correspondingly improved, and the performance of the device is further improved.
In this embodiment, the barrier layer 220 is a nitrogen-containing layer, and correspondingly, the reducing gas is a gas containing nitrogen and hydrogen. In the surface treatment 250 process, the hydrogen element reacts with the oxygen element in the oxide layer to form water vapor, and the water vapor is discharged out of the surface treatment chamber in a gas manner, and the nitrogen element reacts with the remaining elements in the oxide layer to reduce the material of the oxide layer to the material of the barrier layer 220, so that the material and thickness of the barrier layer 220 can meet the process requirements, and the performance of the device is improved. Moreover, after the hydrogen element reacts with the oxygen element in the oxide layer to form water vapor, the water vapor is discharged out of the surface treatment chamber in a gas manner, so that by-products can be prevented from being formed on the surface of the barrier layer 220, and the process risk is low.
Specifically, the material of the barrier layer 220 is TiN, and the material of the oxide layer is correspondingly TiO2Therefore, in the surface treatment process, after the hydrogen element reacts with the oxygen element in the oxide layer, the nitrogen element reacts with the titanium element in the oxide layer, so as to react TiO2The material is converted to a TiN material and the oxide layer is removed accordingly.
In this embodiment, the reducing gas is NH3。NH3The oxide layer 225 can be reduced to the barrier layer 220 by using a reaction gas, which is beneficial to reducing the process cost and simplifying the process complexity. In other embodiments, the reducing gas may also be a mixed gas of nitrogen-containing elements and hydrogen elements, such as: the reducing gas is N2And NH3The mixed gas of (3); alternatively, the reducing gas is H2And NH3The mixed gas of (3); alternatively, the reducing gas is H2And N2The mixed gas of (1).
In this embodiment, the surface treatment is plasma treatment. In the plasma treatment process, the reducing gas is ionized to generate plasma, the plasma bombards the surface of the oxidation layer and can damage the chemical bonds of the oxidation layer material, so that the oxidation layer is subjected to reduction reaction, and the process efficiency is high.
The contact hole plug 240 is electrically connected to the source-drain doping layer 140, and is used for electrically connecting the source-drain doping layer 140 to an external circuit.
In this embodiment, the material of the contact hole plug 240 is W. In other embodiments, the material of the contact hole plug may also be a conductive material such as Al, Cu, Ag, or Au.
Because the interface quality of the barrier layer 220 is good, the formation quality and adhesion of the contact hole plug 240 in the first contact hole 112 are improved, and the density of the barrier layer 220 is high, and the thickness of the barrier layer 220 can meet the process requirements, so that the barrier effect of the barrier layer 220 is ensured; in conclusion, the performance of the device formed by the present embodiment can be improved.
In addition, the semiconductor structure further includes: and a second contact hole 122 (shown in fig. 6) located in the interlayer dielectric layer 102 above the gate structure 120, wherein the second contact hole 122 exposes the top of the gate structure 120.
Accordingly, the metal layer 210 is further located on the bottom and the sidewall of the second contact hole 122, the barrier layer 220 is further located on the metal layer 210 on the bottom and the sidewall of the second contact hole 122, and the contact hole plug 240 is further located in the second contact hole 122 and contacts the barrier layer 220. Wherein the contact hole plug 240 in the second contact hole 122 is used for electrically connecting the gate structure 120 with an external circuit.
In other embodiments, when the gate structure is a polysilicon gate, the metal layer at the bottom of the second contact hole may also react with the gate structure during the formation of the semiconductor structure, so that the metal silicide layer is also located at the bottom of the second contact hole, the metal layer is located on the sidewall of the second contact hole, and the barrier layer is correspondingly located on the metal silicide layer at the bottom of the second contact hole and the sidewall of the second contact hole.
The semiconductor structure of this embodiment may be formed by the formation method described in the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a gate structure is formed on the substrate, active drain doping layers are formed in the substrate on two sides of the gate structure, an interlayer dielectric layer is formed on the substrate exposed out of the gate structure, and the interlayer dielectric layer covers the source drain doping layers;
forming a first contact hole exposing the source-drain doping layer in the interlayer dielectric layer;
forming a metal layer at the bottom of the first contact hole;
forming a barrier layer on the metal layer at the bottom of the first contact hole and on the side wall of the first contact hole;
after the barrier layer is formed, annealing the substrate, and converting the metal layer at the bottom of the first contact hole into a metal silicide layer;
after the annealing treatment, performing surface treatment on the barrier layer by adopting reducing gas;
and forming a contact hole plug in the first contact hole with the barrier layer after the surface treatment.
2. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming a barrier layer on the metal layer at the bottom of the first contact hole and on the sidewall of the first contact hole, the barrier layer is a nitrogen-containing layer;
in the step of surface-treating the barrier layer, the reducing gas is a gas containing a nitrogen element and a hydrogen element.
3. The method of claim 2, wherein the reducing gas is NH3(ii) a Or, the reducing gas is N2And NH3The mixed gas of (3); alternatively, the reducing gas is H2And NH3The mixed gas of (3); alternatively, the reducing gas is H2And N2The mixed gas of (1).
4. The method of forming a semiconductor structure of claim 1, wherein the step of surface treating the barrier layer with a reducing gas comprises: and carrying out plasma treatment on the surface of the barrier layer by adopting reducing gas.
5. The method of forming a semiconductor structure according to claim 4, wherein in the step of forming a barrier layer on the metal layer at the bottom of the first contact hole and on the sidewall of the first contact hole, the barrier layer is a nitrogen-containing layer;
the reducing gas is NH3The parameters of the plasma treatment include: NH (NH)3The gas flow rate is 100 standard ml/min to 1000 standard ml/min, the radio frequency power is 200 kilowatt to 2000 kilowatt, the process temperature is 100 ℃ to 500 ℃, and the process time is 10 seconds to 5 minutes.
6. The method of forming a semiconductor structure of claim 1, wherein a material of the barrier layer is TiN or TaN.
7. The method according to claim 1, wherein in the step of forming the barrier layer on the metal layer at the bottom of the first contact hole and on the sidewall of the first contact hole, the barrier layer has a thickness of 1nn to 5 nm.
8. The method of claim 1, wherein the annealing the substrate is performed at a process temperature of 600 to 1000 degrees celsius.
9. The method of claim 1, wherein the contact plug is made of W, Al, Cu, Ag, or Au.
10. The method of claim 1, wherein the contact plug is made of W, and the forming of the contact plug in the first contact hole comprises a chemical vapor deposition process, wherein a reaction gas of the chemical vapor deposition process comprises WF6、B2H6And H2。
11. The method of forming a semiconductor structure according to claim 1, wherein after forming the first contact hole and before forming a metal layer at a bottom of the first contact hole, the method further comprises: and performing pre-amorphization treatment on the source-drain doping layer exposed out of the first contact hole.
12. The method of claim 11, wherein the pre-amorphization process is an ion implantation process;
the parameters of the ion implantation process include: the implanted ions are Ge ions or Si ions, and the implantation energy is 0.5KeV to3.0KeV, implant dose 1E14atom/cm2To 3E15atom/cm2。
13. The method of forming a semiconductor structure of claim 11, wherein the interlevel dielectric layer covers a top portion of the gate structure;
after the pre-amorphization treatment, before forming a metal layer at the bottom of the first contact hole, the method further includes: forming a second contact hole in the interlayer dielectric layer above the grid structure, wherein the second contact hole exposes the top of the grid structure;
in the step of forming the metal layer, the metal layer is also formed at the bottom of the second contact hole;
in the step of forming the barrier layer, the barrier layer is also formed on the metal layer at the bottom of the second contact hole and on the side wall of the second contact hole;
in the step of forming a contact hole plug in the first contact hole, the contact hole plug is also formed in the second contact hole.
14. A semiconductor structure, comprising:
a substrate;
the grid structure is positioned on the substrate;
the source-drain doping layer is positioned in the substrate at two sides of the grid structure;
the interlayer dielectric layer is positioned on the substrate exposed out of the grid structure and covers the source-drain doping layer;
the first contact hole is positioned in the interlayer dielectric layer and exposes the source-drain doping layer;
the metal silicide layer is positioned at the bottom of the first contact hole;
the barrier layer is positioned on the metal silicide layer at the bottom of the first contact hole and on the side wall of the first contact hole, the barrier layer is subjected to surface treatment after the metal silicide layer is formed, and gas adopted by the surface treatment is reducing gas;
and the contact hole plug is positioned in the first contact hole and is in contact with the barrier layer.
15. The semiconductor structure of claim 14, wherein the barrier layer is a nitrogen-containing layer and the reducing gas is a gas containing a nitrogen element and a hydrogen element.
16. The semiconductor structure of claim 15, wherein the reducing gas is NH3(ii) a Or, the reducing gas is N2And NH3The mixed gas of (3); alternatively, the reducing gas is H2And NH3The mixed gas of (3); alternatively, the reducing gas is H2And N2The mixed gas of (1).
17. The semiconductor structure of claim 14, wherein the surface treatment is a plasma treatment.
18. The semiconductor structure of claim 14, wherein the material of the barrier layer is TiN or TaN.
19. The semiconductor structure of claim 14, wherein the barrier layer has a thickness of 1nn to 5 nm.
20. The semiconductor structure of claim 14, wherein a material of the contact hole plug is W, Al, Cu, Ag, or Au.
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