CN110958018A - Design method for generating multi-frequency synchronous clock system - Google Patents
Design method for generating multi-frequency synchronous clock system Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
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Abstract
The invention discloses a design method for generating a multi-frequency synchronous clock system, wherein the multi-frequency synchronous clock system consists of a phase-locked loop, an FPGA chip and a clock chip; the input end of the clock chip is connected with the output end of an external clock, the multi-stage clock chips are connected through a phase-locked loop, the output end of the first-stage clock chip is connected with the input end of the FPGA chip, and the output end of the FPGA chip is connected with the input end of the last-stage clock chip. The invention has the beneficial effects that: the clock chip, the phase-locked loop and the FPGA are matched, multi-channel clock output with different frequencies is achieved, all the clock output is kept synchronous, the front-end clock adopts low-frequency transmission, the extensible number of clock channels and the clock stability are greatly improved, the synchronous state can be kept among the clocks with different frequencies, and therefore the number and the flexibility of the software-based radar arrays can be greatly improved.
Description
Technical Field
The invention relates to a clock system design method, in particular to a design method for generating a multi-frequency synchronous clock system, and belongs to the technical field of product application and intelligent hardware.
Background
In a software radar digital TR component system, more and more channels are provided for DAC and ADC, the requirements on the working sampling rate of ADC and DAC for realizing radio frequency direct acquisition are higher and higher, and the requirements on the working frequency of ADC and DAC are different based on the difference of data processing pressure. In order to accurately identify a target, the software-based radar needs to ensure that all DAC channels of the system keep a synchronous state, all ADC channel acquisition also keep a synchronous state, and the DAC output and the ADC acquisition also keep a synchronous state, and the key for realizing the process is that all clocks in the system need to reach the synchronous state. In a common method, a high-frequency clock buffer is adopted for cascade connection, and the high-frequency clock is easily interfered, so that sampling synchronization adjustment is difficult, the adjustment precision is low, and the expansion of the number of channels is limited.
Disclosure of Invention
The invention aims to provide a design method for generating a multi-frequency synchronous clock system, which aims to solve the problems that the front-end clock adopts low-frequency transmission, the expandable number of clock channels and the clock stability are greatly improved, and the clocks with different frequencies can keep a synchronous state, so that the number and the flexibility of a software-based radar array can be greatly improved.
The invention realizes the purpose through the following technical scheme: a design method for generating a multi-frequency synchronous clock system comprises the steps that the multi-frequency synchronous clock system is composed of a phase-locked loop, an FPGA chip and a clock chip; the input end of the clock chip is connected with the output end of an external clock, the clock chips in multiple stages are connected through a phase-locked loop, the output end of the clock chip in the first stage is connected with the input end of the FPGA chip, and the output end of the FPGA chip is connected with the input end of the clock chip in the last stage;
the clock chip comprises a clock chip a and a clock chip b, the working frequency of the clock chip a can cover the output frequency of the phase-locked loop, the clock chip has multi-channel output, each channel contains an independent frequency divider, each channel frequency divider in the clock chip can be uniformly controlled through an external signal, the working frequency of the clock chip b can realize one-channel input multi-channel output, and the channel output jitter meets the requirement of system clock synchronization;
a design method for generating a multiple frequency synchronous clock system, comprising the steps of:
step one, the exterior of the multi-frequency synchronous clock system has and only has a clock source;
selecting an external input to be directly connected with the clock chip a or to be connected with the clock chip a through phase-locked loop frequency multiplication during design according to the clock source frequency and the working frequency of the first-stage clock chip a, so that a measure of direct frequency division or frequency multiplication and reuse by utilizing the phase-locked loop is adopted, and the clock chip a is selected at the same time;
determining the number of the last-stage clock chips a and the number of the phase-locked loops according to the clock frequency and the number of the clock channels which need to be output, and determining the working frequency of the phase-locked loops which need to be selected according to the least common multiple of the clock frequency which needs to be output;
selecting a clock chip b according to the number of clock channels required by the system and the output frequency of the first-stage clock chip a, and outputting multiple paths of the first-stage clock chip through cascade connection of multiple stages of clock chips b to enlarge the clock output scale;
step five, the first-stage clock chip outputs a path of clock to the FPGA, the FPGA generates a synchronous signal according to the clock and controls all the clocks at the last stage to output synchronization, and the clock is generated through the first-stage clock chip, so that the clock and the clock at the last stage have a fixed phase difference;
step six, configuring the least common multiple of all clock frequencies required to be output in a plurality of phase-locked loop generating systems, wherein the high-frequency clock output by the phase-locked loop is directly connected to the last-stage clock chip a;
step seven, configuring a frequency divider of the last-stage clock chip a according to system requirements, and ensuring that each channel generates frequency according to the final system requirements;
and step eight, generating a synchronous control signal, controlling the clock chip a frequency divider to be synchronous, generating and ensuring the required frequency output by each channel, and synchronizing all the clocks.
The invention has the beneficial effects that: the design method of the system for generating the multi-frequency synchronous clock is reasonable in design, the clock chip, the phase-locked loop and the FPGA are matched, multi-channel clock output with different frequencies is achieved, all the clock output keeps synchronous, the front-end clock adopts low-frequency transmission, the extensible number of clock channels and the clock stability are greatly improved, the synchronous state can be kept among different frequency clocks, and therefore the number and the flexibility of software radar arrays can be greatly improved.
Drawings
FIG. 1 is a schematic block diagram of the present invention;
FIG. 2 is a schematic diagram of a multi-frequency synchronous clock generation process according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-2, a design method for generating a multi-frequency synchronous clock system includes the steps of generating a multi-frequency synchronous clock system; the multi-frequency synchronous clock system consists of a phase-locked loop, an FPGA chip and a clock chip; the input end of the clock chip is connected with the output end of an external clock, the clock chips in multiple stages are connected through a phase-locked loop, the output end of the clock chip in the first stage is connected with the input end of the FPGA chip, and the output end of the FPGA chip is connected with the input end of the clock chip in the last stage;
the clock chip comprises a clock chip a and a clock chip b, the working frequency of the clock chip a can cover the output frequency of the phase-locked loop, the clock chip has multi-channel output, each channel contains an independent frequency divider, each channel frequency divider in the clock chip can be uniformly controlled through an external signal, the working frequency of the clock chip b can realize one-channel input multi-channel output, and the channel output jitter meets the requirement of system clock synchronization;
a design method for generating a multiple frequency synchronous clock system, comprising the steps of:
step one, the exterior of the multi-frequency synchronous clock system has and only has a clock source;
selecting an external input to be directly connected with the clock chip a or to be connected with the clock chip a through phase-locked loop frequency multiplication during design according to the clock source frequency and the working frequency of the first-stage clock chip a, so that a measure of direct frequency division or frequency multiplication and reuse by utilizing the phase-locked loop is adopted, and the clock chip a is selected at the same time;
determining the number of the last-stage clock chips a and the number of the phase-locked loops according to the clock frequency and the number of the clock channels which need to be output, and determining the working frequency of the phase-locked loops which need to be selected according to the least common multiple of the clock frequency which needs to be output;
selecting a clock chip b according to the number of clock channels required by the system and the output frequency of the first-stage clock chip a, and outputting multiple paths of the first-stage clock chip through cascade connection of multiple stages of clock chips b to enlarge the clock output scale;
step five, the first-stage clock chip outputs a path of clock to the FPGA, the FPGA generates a synchronous signal according to the clock and controls all the clocks at the last stage to output synchronization, and the clock is generated through the first-stage clock chip, so that the clock and the clock at the last stage have a fixed phase difference;
step six, configuring the least common multiple of all clock frequencies required to be output in a plurality of phase-locked loop generating systems, wherein the high-frequency clock output by the phase-locked loop is directly connected to the last-stage clock chip a;
step seven, configuring a frequency divider of the last-stage clock chip a according to system requirements, and ensuring that each channel generates frequency according to the final system requirements;
and step eight, generating a synchronous control signal, controlling the clock chip a frequency divider to be synchronous, generating and ensuring the required frequency output by each channel, and synchronizing all the clocks.
Examples
According to the system requirements, an externally input 500MHz clock is adjusted, synchronous output of a 64-channel 1GHz clock is realized, synchronous output of a 64-channel 3GHz clock is realized, 125M clock output of a 384-channel is realized, 3.125M clock output of a 256-channel is realized, and clocks among different frequencies are kept in a synchronous state.
By analyzing the required clocks, the least common multiple of all the required clock frequencies is 3GHz, so that the minimum output frequency of the phase-locked loop is selected to be 3 GHz; selecting 14 paths of outputs of each channel of a clock chip a, wherein the maximum working frequency is 3.2GHz, and the final stage in a clock system needs 64 clock chips b according to the number of required clock channels, wherein the output conditions of the 32 clock chips b are as follows: 2 channels 3Ghz, 4 channels 3.125MHz and 6 channels 125MHz, and the other 32 clock chips b output the following conditions: 2 channels 1Ghz, 4 channels 3.125MHz and 6 channels 125 MHz; therefore, the number of the phase-locked loops is required to be 64 finally, the front end of the phase-locked loop needs a 2-level clock to expand the number of the clock channels, a second-level clock chip b is selected, the working frequency of the second-level clock chip b is 100M, the number of the output channels is 14, and the number of the second-level clock chips b is required to be 6; the working frequency of the selected clock chip a is 100MHz, the frequency of the external input signal is 500MHz, so that a phase-locked loop is not needed to carry out frequency multiplication between an external input source and the clock chip, and only the clock chip a is needed to carry out frequency division
Generating a multiple frequency synchronous clock system comprising the steps of:
step one, configuring a first-stage clock chip output frequency dividing ratio to be 5 through an FPGA according to an external input clock frequency, and setting output frequencies of all channels of the first-stage clock chip to be 100 MHz;
generating a synchronous signal through the FPGA chip, and controlling all channel frequency dividers of the first-stage clock chip to be synchronous;
step three, configuring all clock chips of 2-K levels to only expand the clock output quantity, namely all channels directly output according to the input frequency;
step four, all phase-locked loops are configured, the output clock frequency is the least common multiple of all required clock frequencies, the phase-locked loops work in an integer frequency mode, and the phase-locked loops VCO directly output without frequency division;
step five, configuring the frequency dividing ratios of all clock chips of the final stage to generate the clock frequency required by the system;
and step six, the FPGA chip simultaneously generates synchronous control signals of all the clock chips at the last stage according to the input clock of the first-stage clock chip, and frequency divider synchronization of all channels of all the clock chips at the last stage is carried out, so that the system is ensured to require all the clocks to reach a synchronous state.
The working principle is as follows: when the design method for generating the multi-frequency synchronous clock system is used, the clock chip, the phase-locked loop and the FPGA are matched to realize multi-channel clock output with different frequencies, all the clock output keeps synchronous, and before the clock enters the phase-locked loop, the low-frequency clock is adopted to transmit among the multi-stage clocks, so that the system stability is improved.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (1)
1. A design method for generating a multi-frequency synchronous clock system is characterized in that: the multi-frequency synchronous clock system consists of a phase-locked loop, an FPGA chip and a clock chip; the input end of the clock chip is connected with the output end of an external clock, the clock chips in multiple stages are connected through a phase-locked loop, the output end of the clock chip in the first stage is connected with the input end of the FPGA chip, and the output end of the FPGA chip is connected with the input end of the clock chip in the last stage;
the clock chip comprises a clock chip a and a clock chip b, the working frequency of the clock chip a can cover the output frequency of the phase-locked loop, the clock chip has multi-channel output, each channel contains an independent frequency divider, each channel frequency divider in the clock chip can be uniformly controlled through an external signal, the working frequency of the clock chip b can realize one-channel input multi-channel output, and the channel output jitter meets the requirement of system clock synchronization;
a design method for generating a multiple frequency synchronous clock system, comprising the steps of:
step one, the exterior of the multi-frequency synchronous clock system has and only has a clock source;
selecting an external input to be directly connected with the clock chip a or to be connected with the clock chip a through phase-locked loop frequency multiplication during design according to the clock source frequency and the working frequency of the first-stage clock chip a, so that a measure of direct frequency division or frequency multiplication and reuse by utilizing the phase-locked loop is adopted, and the clock chip a is selected at the same time;
determining the number of the last-stage clock chips a and the number of the phase-locked loops according to the clock frequency and the number of the clock channels which need to be output, and determining the working frequency of the phase-locked loops which need to be selected according to the least common multiple of the clock frequency which needs to be output;
selecting a clock chip b according to the number of clock channels required by the system and the output frequency of the first-stage clock chip a, and outputting multiple paths of the first-stage clock chip through cascade connection of multiple stages of clock chips b to enlarge the clock output scale;
step five, the first-stage clock chip outputs a path of clock to the FPGA, the FPGA generates a synchronous signal according to the clock and controls all the clocks at the last stage to output synchronization, and the clock is generated through the first-stage clock chip, so that the clock and the clock at the last stage have a fixed phase difference;
step six, configuring the least common multiple of all clock frequencies required to be output in a plurality of phase-locked loop generating systems, wherein the high-frequency clock output by the phase-locked loop is directly connected to the last-stage clock chip a;
step seven, configuring a frequency divider of the last-stage clock chip a according to system requirements, and ensuring that each channel generates frequency according to the final system requirements;
and step eight, generating a synchronous control signal, controlling the clock chip a frequency divider to be synchronous, generating and ensuring the required frequency output by each channel, and synchronizing all the clocks.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113055000A (en) * | 2021-03-23 | 2021-06-29 | 加特兰微电子科技(上海)有限公司 | Sensing system, related device and method for acquiring working clock signal |
| CN114124278A (en) * | 2021-10-30 | 2022-03-01 | 中国船舶重工集团公司第七二三研究所 | Digital synchronization circuit and method for digital simultaneous multi-beam transmission |
| CN114167712A (en) * | 2021-12-02 | 2022-03-11 | 武汉贞坤电子有限公司 | Multi-frequency synchronous clock system and method |
| CN114938258A (en) * | 2022-07-25 | 2022-08-23 | 星河动力(北京)空间科技有限公司 | Rocket control clock synchronization device, flight controller and rocket control computer |
| CN115001491A (en) * | 2022-05-26 | 2022-09-02 | 湖南迈克森伟电子科技有限公司 | Synchronous sampling method and device of multi-chip ADC sampling clock array |
| WO2022198434A1 (en) * | 2021-03-23 | 2022-09-29 | 加特兰微电子科技(上海)有限公司 | Sensing system, related apparatus, and method for obtaining working clock signal |
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