CN110957984A - Digital audio power amplifier - Google Patents

Digital audio power amplifier Download PDF

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Publication number
CN110957984A
CN110957984A CN201911200149.3A CN201911200149A CN110957984A CN 110957984 A CN110957984 A CN 110957984A CN 201911200149 A CN201911200149 A CN 201911200149A CN 110957984 A CN110957984 A CN 110957984A
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China
Prior art keywords
auxiliary
integrator
current source
type transistor
gate
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CN201911200149.3A
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Inventor
周佳宁
张海军
姚炜
程剑涛
杜黎明
孙洪军
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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Priority to CN201911200149.3A priority Critical patent/CN110957984A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers

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Abstract

The invention discloses a digital audio power amplifier, which provides corresponding auxiliary source current for the input end of a corresponding integrator through a first auxiliary current source and a second auxiliary current source, and avoids the situation that the corresponding power amplification loops of a first side current source, a second side current source and the integrator do not have enough voltage margin to support the normal operation of a circuit. And secondly, the influence of the process deviation of the current source on the current provided for the integrator is improved, the difference of the voltages respectively provided by the first integrator and the second integrator for the audio load is reduced, and the direct-current offset voltage is eliminated. The first auxiliary current source and the second auxiliary current source alternately operate through the first auxiliary state and the second auxiliary state of the driving circuit, so that the first auxiliary current source and the second auxiliary current source alternately provide auxiliary source currents for the input end of the first integrator and the second integrator respectively, and the situation that the power supply rejection ratio is reduced due to non-ideal factors such as mismatch of manufacturing processes of the first auxiliary current source and the second auxiliary current source is avoided.

Description

Digital audio power amplifier
Technical Field
The invention relates to the technical field of digital audio power amplifiers, in particular to a digital audio power amplifier.
Background
Class D audio power amplifiers are currently in widespread use due to their high efficiency, which exceeds 80%. Particularly in the field of electronic equipment such as mobile phones and the like, the high-efficiency audio power amplifier can not only prolong the working time of the electronic equipment and reduce the heat productivity of the electronic equipment, but also obtain larger volume and better tone quality. The class D audio power amplifiers are mainly classified into two types, one is an analog audio power amplifier, and the other is a digital audio power amplifier. The audio signal can be transmitted by the digital audio power amplifier, so that the digital audio power amplifier has extremely high RF interference resistance and low noise floor, and is widely applied at present.
However, when the output voltage of the digital audio power amplifier in the prior art reaches a higher voltage value (e.g., 10V), a situation may occur that the digital audio power amplifier cannot normally operate because the power amplifier loops corresponding to the current source and the integrator of the digital audio power amplifier do not have sufficient voltage margins.
Disclosure of Invention
In view of the above, the present invention provides a digital audio power amplifier, which can effectively solve the technical problems in the prior art.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a digital audio power amplifier, comprising: the digital modulator comprises a D-type digital modulator, a first side current source, a second side current source, a main driving circuit, a first auxiliary current source, a second auxiliary current source, an auxiliary driving circuit, a first integrator and a second integrator;
the D-type digital modulator is used for converting the received audio digital signal into a PWMP signal and a PWMN signal;
the main driving circuit comprises a first main state and a second main state which are operated alternately, wherein when the main driving circuit is in the first main state, the main driving circuit controls a first side current source to provide a first source current or a first sink current for the input end of a first integrator according to the PWMP signal, and controls a second side current source to provide a second source current or a second sink current for the input end of a second integrator according to the PWMN signal; when the main drive circuit is in the second main state, the main drive circuit controls the second side current source to provide a second source current or a second sink current for the input end of the first integrator according to the PWMP signal, and controls the first side current source to provide a first source current or a first sink current for the input end of the second integrator according to the PWMN signal;
and the auxiliary drive circuit comprises a first auxiliary state and a second auxiliary state which are operated alternately, wherein when the auxiliary drive circuit is in the first auxiliary state, the auxiliary drive circuit controls the first auxiliary current source to provide a first auxiliary source current for the input end of the first integrator, and controls the second auxiliary current source to provide a second auxiliary source current for the input end of the second integrator; and when the auxiliary driving circuit is in the second auxiliary state, the auxiliary driving circuit controls the first auxiliary current source to provide the first auxiliary source current for the input end of the second integrator, and controls the second auxiliary current source to provide the second auxiliary source current for the input end of the first integrator.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
according to the digital audio power amplifier, the first auxiliary current source and the second auxiliary current source provide corresponding auxiliary source currents for the input ends of the corresponding integrators, so that the requirement for large reference voltage related in the integrators when the output voltage of the digital audio power amplifier is high is reduced, and the situation that corresponding power amplifier loops of the first side current source, the second side current source and the integrators do not have enough voltage margin to support normal operation of a circuit is avoided.
Secondly, when the main driving circuit is in a first main state, controlling a first side current source to provide current for the input end of a first integrator according to a PWMP signal, and controlling a second side current source to provide current for the input end of a second integrator according to a PWMN signal; and when the main driving circuit is in the second main state, the second side current source is controlled to provide current for the input end of the first integrator according to the PWMP signal, the first side current source is controlled to provide current for the input end of the second integrator according to the PWMN signal, and the first main state and the second main state of the main driving circuit alternately operate, so that the currents provided for the first integrator and the second integrator are the average value of the currents of the first side current source and the second side current source, the influence on the current provided for the integrator due to the process deviation of the current sources is improved, the difference of the voltages respectively provided for the audio load by the first integrator and the second integrator is reduced, the direct-current offset voltage is eliminated, and the sound production effect of the audio load is ensured to be excellent.
In addition, the first auxiliary current source provides a first auxiliary source current for the input end of the first integrator when the auxiliary driving circuit is in a first auxiliary state, and the second auxiliary current source provides a second auxiliary source current for the input end of the second integrator; and when the driving circuit is in the second auxiliary state, the first auxiliary current source provides a first auxiliary source current for the input end of the second integrator, the second auxiliary current source provides a second auxiliary source current for the input end of the first integrator, and then the first auxiliary state and the second auxiliary state of the driving circuit alternately operate to enable the first auxiliary current source and the second auxiliary current source to alternately provide the auxiliary source currents for the input end of the first integrator and the second integrator respectively, so that the situation that the power supply rejection ratio is reduced due to non-ideal factors such as mismatch of manufacturing processes of the first auxiliary current source and the second auxiliary current source is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a digital audio power amplifier according to the prior art;
fig. 2 is a schematic structural diagram of a digital audio power amplifier according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of an integrator provided in an embodiment of the present application;
fig. 4 is a schematic structural diagram of a common mode voltage generating module according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of an auxiliary current source according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a main driving circuit according to an embodiment of the present disclosure;
fig. 8 is a charging/discharging waveform diagram of the first capacitor according to the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, when the output voltage of the digital audio power amplifier in the prior art reaches a higher voltage value (for example, 10V), a situation may occur that the digital audio power amplifier cannot operate normally because the power amplifier loops corresponding to the current source and the integrator of the digital audio power amplifier do not have sufficient voltage margins.
Referring to fig. 1, a schematic structural diagram of a digital audio power amplifier in the prior art is shown, where the digital audio power amplifier includes a first side current source, a second side current source, a first integrator, and a second integrator, and any one of the first integrator and the second integrator includes a common-mode voltage generation module, an operational amplifier, a capacitor C, a power amplifier loop driving module, a feedback resistor Rfb, a transistor P, and a transistor N. Of course, in practical applications, the digital audio power amplifier further includes a digital modulator, etc., and will not be described herein again.
The digital modulator is accessed with I2S and other digital audio signals, then sampling, delta-sigma noise shaping and BD modulation are carried out on the digital audio signals, and two pulse width modulation signals, namely PWMP and PWMN, are output after delta-sigma shaped in-phase signals and delta-sigma shaped anti-phase signals are respectively compared with triangular wave signals. The first side current source provides source current or sink current for the first integrator according to the PWMP signal, and the second side current source provides source current or sink current for the second integrator according to the PWMN signal.
In operation, taking the first integrator as an example, in order to maintain the stability of the power amplifier loop in the first integrator, the Vop voltage is injected into the current value of the Vip node when being equal to the voltage of the power supply PVDD, and must be equal to the current value extracted from the Vip node when the Vop voltage is equal to 0. This means that the reference voltage VREF is equal to half the voltage of PVDD. When the digital audio power amplifier outputs a higher voltage, for example, 10V for a high voltage digital audio power amplifier, the reference voltage VREF provided by the common mode voltage generation module in the integrator is required to be 5V. And because the maximum working voltage that the corresponding power amplifier loop of first side current source and first integrator can support is 5V, there is not enough voltage margin in the corresponding power amplifier loop of first side current source and first integrator of digital audio power amplifier at this moment, and make the unable normal condition of working of digital audio power amplifier.
Based on this, the embodiment of the present application provides a digital audio power amplifier, which can effectively solve the technical problems existing in the prior art. In order to achieve the above object, the technical solutions provided by the embodiments of the present application are described in detail below, and specifically, with reference to fig. 2 to 8.
Referring to fig. 2, a schematic structural diagram of a digital audio power amplifier provided in an embodiment of the present application is shown, where the digital audio power amplifier includes:
the digital modulator comprises a D-type digital modulator 1, a first side current source 2, a second side current source 3, a main driving circuit 9, a first auxiliary current source 4, a second auxiliary current source 5, an auxiliary driving circuit 8, a first integrator 6 and a second integrator 7;
the D-type digital modulator 1 is used for converting a received audio digital signal into a PWMP signal and a PWMN signal;
the main driving circuit 9 comprises a first main state and a second main state which are operated alternately, wherein when the main driving circuit 9 is in the first main state, the main driving circuit 9 controls the first side current source 2 to provide a first source current or a first sink current for the input end Vip of the first integrator 6 according to the PWMP signal, and controls the second side current source 3 to provide a second source current or a second sink current for the input end Vin of the second integrator 7 according to the PWMN signal; when the main driving circuit 9 is in the second main state, the main driving circuit 9 controls the second side current source 3 to provide a second source current or a second sink current for the input end Vip of the first integrator 6 according to the PWMP signal, and controls the first side current source 2 to provide a first source current or a first sink current for the input end Vin of the second integrator 7 according to the PWMN signal;
and the auxiliary driving circuit 8 comprises a first auxiliary state and a second auxiliary state which are operated alternately, wherein when the auxiliary driving circuit 8 is in the first auxiliary state, the auxiliary driving circuit 8 controls the first auxiliary current source 4 to provide a first auxiliary source current for the input end Vip of the first integrator 6, and controls the second auxiliary current source 5 to provide a second auxiliary source current for the input end Vin of the second integrator 7; and when the auxiliary driving circuit 8 is in the second auxiliary state, the auxiliary driving circuit 8 controls the first auxiliary current source 4 to provide the first auxiliary source current for the input terminal Vin of the second integrator 7, and controls the second auxiliary current source 5 to provide the second auxiliary source current for the input terminal Vip of the first integrator 6, wherein the output terminals of the first integrator 6 and the second integrator 7 are both connected to the audio load 10.
It should be noted that the first integrator and the second integrator of the digital audio power amplifier provided in the embodiment of the present application include the same components, and parameters of corresponding components are the same; and the first auxiliary source current generated by the first auxiliary current source is the same as the second auxiliary source current generated by the second auxiliary current source.
According to the above, the first auxiliary current source and the second auxiliary current source provide corresponding auxiliary source currents for the input ends of the corresponding integrators, so that the requirement for large reference voltages related in the integrators when the output voltage of the digital audio power amplifier is high is reduced, and the situation that the corresponding power amplifier loops of the first side current source, the second side current source and the integrators do not have enough voltage margin to support the normal operation of the circuit is avoided.
Secondly, when the main driving circuit is in a first main state, controlling a first side current source to provide current for the input end of a first integrator according to a PWMP signal, and controlling a second side current source to provide current for the input end of a second integrator according to a PWMN signal; and when the main driving circuit is in the second main state, the second side current source is controlled to provide current for the input end of the first integrator according to the PWMP signal, the first side current source is controlled to provide current for the input end of the second integrator according to the PWMN signal, and the first main state and the second main state of the main driving circuit alternately operate, so that the currents provided for the first integrator and the second integrator are the average value of the currents of the first side current source and the second side current source, the influence on the current provided for the integrator due to the process deviation of the current sources is improved, the difference of the voltages respectively provided for the audio load by the first integrator and the second integrator is reduced, the direct-current offset voltage is eliminated, and the sound production effect of the audio load is ensured to be excellent.
In addition, the first auxiliary current source provides a first auxiliary source current for the input end of the first integrator when the auxiliary driving circuit is in a first auxiliary state, and the second auxiliary current source provides a second auxiliary source current for the input end of the second integrator; and when the driving circuit is in the second auxiliary state, the first auxiliary current source provides a first auxiliary source current for the input end of the second integrator, the second auxiliary current source provides a second auxiliary source current for the input end of the first integrator, and then the first auxiliary state and the second auxiliary state of the driving circuit alternately operate to enable the first auxiliary current source and the second auxiliary current source to alternately provide the auxiliary source currents for the input end of the first integrator and the second integrator respectively, so that the situation that the power supply rejection ratio is reduced due to non-ideal factors such as mismatch of manufacturing processes of the first auxiliary current source and the second auxiliary current source is avoided.
Referring to fig. 3, a schematic structural diagram of an integrator provided in an embodiment of the present application is shown, where any one of the first integrator and the second integrator includes: the circuit comprises a first operational amplifier 11, a common-mode voltage generation module, a first capacitor C1, a feedback resistor Rfb, a power amplifier loop driving module, a first auxiliary P-type transistor P1 'and a first auxiliary N-type transistor N1';
the inverting terminal of the first operational amplifier 11 is an input terminal of the integrator (the input terminal Vip of the first integrator/the input terminal Vin of the second integrator), the inverting terminal of the first operational amplifier 11, the first plate of the first capacitor C1 and the first terminal of the feedback resistor Rfb are all connected, the non-inverting terminal of the first operational amplifier 11 is connected to the output terminal of the common-mode voltage generating module, the common-mode voltage generating module is configured to output a reference voltage VREF, and the output terminal of the first operational amplifier 11, the second plate of the first capacitor C1 and the input terminal of the power amplifier loop driving module are all connected;
a first output end of the power amplifier loop driving module is connected with a grid electrode of the first auxiliary P-type transistor P1 ', and a second output end of the power amplifier loop driving module is connected with a grid electrode of the first auxiliary N-type transistor N1';
the source of the first auxiliary P-type transistor P1 'is connected to the power supply PVDD, the source of the first auxiliary N-type transistor N1' is connected to the ground, and the drain of the first auxiliary P-type transistor P1 ', the drain of the first auxiliary N-type transistor N1' and the second end of the feedback resistor Rfb are all connected to the output terminal of the integrator (the output terminal Vop of the first integrator/the output terminal Von of the second integrator).
Referring to fig. 4, a schematic structural diagram of a common mode voltage generating module provided in an embodiment of the present application is shown, where the common mode voltage generating module includes: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3 and a second capacitor C2;
a first end of the first resistor R1 is connected with an operating voltage end VDD, and a second end of the first resistor R1, a first end of the second resistor R2 and a first end of the third resistor R3 are all connected;
the second end of the second resistor R2 and the second plate of the second capacitor C2 are both connected to the ground terminal;
the second end of the third resistor R3 and the first plate of the second capacitor C2 are connected as the output end of the common mode voltage generating module.
In an embodiment of the present application, the reference voltage is a half of the working voltage at the working voltage end, so that the power amplifier loop corresponding to the integrator can work normally.
Further, when the auxiliary driving circuit alternately operates the first auxiliary state and the second auxiliary state, the auxiliary driving circuit is further configured to control the feedback resistance of the first integrator and the feedback resistance of the second integrator to be interchanged with each other, so that an influence of the feedback resistances of the first integrator and the second integrator on the integrators due to manufacturing process deviations can be eliminated, and a situation that a power supply rejection ratio is reduced due to non-ideal factors such as manufacturing process mismatch of the feedback resistances of the first integrator and the second integrator is further eliminated.
Referring to fig. 5, a schematic structural diagram of an auxiliary driving circuit provided in an embodiment of the present application is shown, where the auxiliary driving circuit includes: a first switch M1, a second switch M2, a third switch M3, a fourth switch M4, a fifth switch M5, a sixth switch M6, a seventh switch M7 and an eighth switch M8, wherein the first switch M1, the second switch M2, the third switch M3 and the fourth switch M4 are on in the first auxiliary state and off in the second auxiliary state, and the fifth switch M5, the sixth switch M6, the seventh switch M7 and the eighth switch M8 are off in the first auxiliary state and on in the second auxiliary state;
the first switch M1 is connected between the input end Vip of the first integrator and the output end of the first auxiliary current source 4, the output end of the first auxiliary current source 4 is connected with the first end of the feedback resistor Rfb1 of the first integrator, and the second switch M2 is connected between the second end of the feedback resistor Rfb1 of the first integrator and the output end Vop of the first integrator;
the third switch M3 is connected between the input terminal Vin of the second integrator and the output terminal of the second auxiliary current source 5, the output terminal of the second auxiliary current source 5 is connected to the first terminal of the feedback resistor Rfb2 of the second integrator, and the fourth switch M4 is connected between the second terminal of the feedback resistor Rfb2 of the second integrator and the output terminal Von of the second integrator;
the fifth switch M5 is connected between the input end Vip of the first integrator and the output end of the second auxiliary current source 5, and the sixth switch M6 is connected between the second end of the feedback resistor Rfb2 of the second integrator and the output end Vop of the first integrator;
the seventh switch M7 is connected between the input terminal Vin of the second integrator and the output terminal of the first auxiliary current source 4, and the eighth switch M8 is connected between the second terminal of the feedback resistor Rfb1 of the first integrator and the output terminal Von of the second integrator.
In an embodiment of the present application, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, and the eighth switch provided by the present application are all transistors.
It should be noted that, in the embodiments of the present application, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, and the eighth switch may be P-type transistors, and may also be N-type transistors. Preferably, the first switch, the second switch, the third switch, and the fourth switch have the same conduction condition, and the fifth switch, the sixth switch, the seventh switch, and the eighth switch have the same low conduction condition, so that the number of wirings can be reduced.
Referring to fig. 6, a schematic structural diagram of an auxiliary current source provided in an embodiment of the present application is shown, where any one of the first auxiliary current source and the second auxiliary current source includes: a second operational amplifier 12, a fourth resistor R4, a second auxiliary N-type transistor N2 'and a third auxiliary N-type transistor N3';
the inverting terminal of the second operational amplifier 12 is connected to the working voltage terminal VDD, the non-inverting terminal of the second operational amplifier 12, the second terminal of the fourth resistor R4 and the drain of the second auxiliary N-type transistor N2 ' are all connected, and the output terminal of the second operational amplifier 12, the gate of the second auxiliary N-type transistor N2 ' and the gate of the third auxiliary N-type transistor N3 ' (the third auxiliary N-type transistor N31 ' of the first auxiliary current source and the third auxiliary N-type transistor N32 ' of the second auxiliary current source) are all connected;
a first end of the fourth resistor R4 is connected to the power supply PVDD;
the source of the second auxiliary N-type transistor N2 ' and the source of the third auxiliary N-type transistor N3 ' are both connected to ground, and the drain of the third auxiliary N-type transistor N3 ' is the output terminal of the auxiliary current source (the output terminal Isnk1 of the first auxiliary current source and the output terminal Isnk2 of the second auxiliary current source).
In an embodiment of the present application, as shown in fig. 6, the second operational amplifier of the first auxiliary current source and the second operational amplifier of the second auxiliary current source provided by the present application are the same operational amplifier 12;
the fourth resistor of the first auxiliary current source and the fourth resistor of the second auxiliary current source are the same resistor R4;
and the second auxiliary N-type transistor of the first auxiliary current source and the second auxiliary N-type transistor of the second auxiliary current source are the same N-type transistor N2.
In an embodiment of the present application, a resistance value of the fourth resistor provided by the present application is twice a resistance value of the feedback resistor;
and the width-to-length ratios of the second auxiliary N-type transistor and the third auxiliary N-type transistor are the same.
In an embodiment of the present application, the main driving circuit provided in the embodiment of the present application includes: the first logic conversion circuit, the second logic conversion circuit, the first controllable switch circuit and the second controllable switch circuit;
the first logic conversion circuit is connected with the first controllable switch circuit, is accessed to the PWMP signal and the PWMN signal, and is configured to convert the PWMP signal and the PWMN signal into a first control signal in the first master state, so as to control the first controllable switch circuit to connect the first side current source with the input terminal of the first integrator; the second logic conversion circuit is connected with the second controllable switch circuit, is accessed to the PWMP signal and the PWMN signal, and is used for converting the PWMP signal and the PWMN signal into a second control signal in the first main state so as to control the second controllable switch circuit to connect the second side current source with the input end of the second integrator;
and in the second master state, the first logic conversion circuit is configured to convert the PWMP signal and the PWMN signal into a third control signal to control the first controllable switch circuit to connect the first side current source to the input terminal of the second integrator; and the second logic conversion circuit is used for converting the PWMP signal and the PWMN signal into a fourth control signal so as to control the second controllable switch circuit to connect the second side current source with the input end of the first integrator.
In an embodiment of the present application, the switching of the control signals of the PWMP signal and the PWMN signal in the present application can be realized by a logic gate circuit, that is, the first logic switching circuit performs logic operation control on the PWMP signal and the PWMN signal through the logic gate circuit, and outputs the first control signal in the first main state and outputs the third control signal in the second main state;
and/or the second logic conversion circuit performs logic operation control on the PWMP signal and the PWMN signal through a logic gate circuit, and outputs the second control signal in the first main state and the fourth control signal in the second main state.
Specifically referring to fig. 7, a schematic structural diagram of a main driving circuit provided in the embodiment of the present application is shown, where the first logic converting circuit provided in the embodiment of the present application includes: a first nand gate 2011, a second nand gate 2012, a first nor gate 2021, a second nor gate 2022, and a first inverter 2031;
the output ends of the first nand gate 2011, the second nand gate 2012, the first nor gate 2021 and the second nor gate 2022 are all connected to the first controllable switch circuit, one input ends of the first nand gate 2011, the second nor gate 2022 and the input end of the first inverter 2031 are all connected to a main state control signal PWM _ CTRL, one input ends of the second nand gate 2012 and the first nor gate 2021 are all connected to the output end of the first inverter 2031, the other input ends of the first nand gate 2011 and the first nor gate 2021 are all connected to the PWMP signal, and the other input ends of the second nand gate 2012 and the second nor gate 2022 are all connected to the PWMN signal;
and, the second logic conversion circuit includes: a third nand gate 2013, a fourth nand gate 2014, a third nor gate 2023, a fourth nor gate 2024, and a second inverter 2032;
the output ends of the third nand gate 2013, the fourth nand gate 2014, the third nor gate 2023 and the fourth nor gate 2024 are all connected to the second controllable switch circuit, one input ends of the third nand gate 2013 and the fourth nor gate 2024 and the input end of the second inverter 2032 are all connected to a main state control signal PWM _ CTRL, one input ends of the fourth nand gate 2014 and the third nor gate 2023 are all connected to the output end of the second inverter 2032, the other input ends of the third nand gate 2013 and the third nor gate 2023 are all connected to the PWMN signal, and the other input ends of the fourth nand gate 2014 and the fourth nor gate 2024 are all connected to the PWMP signal.
Referring to fig. 7, in an embodiment of the present application, the first controllable switch circuit provided by the present application includes: a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, and a second N-type transistor N2, the first side current source including a first side first sub-current source idap 1 and a first side second sub-current source idap 2;
the sources of the first P-type transistor P1 and the second P-type transistor P2 are both connected to the output terminal of the first sub-current source IDACP1 on the first side, the gate of the first P-type transistor P1 is connected to the output terminal of the second nand gate 2012, the drain of the first P-type transistor P1 is connected to the input terminal Vin of the second integrator 7, the gate of the second P-type transistor P2 is connected to the output terminal of the first nand gate 2011, and the drain of the second P-type transistor P2 is connected to the input terminal Vip of the first integrator 6;
the sources of the first N-type transistor N1 and the second N-type transistor N2 are both connected to the input terminal of the first-side second sub-current source IDACP2, the gate of the first N-type transistor N1 is connected to the output terminal of the second nor gate 2022, the drain of the first N-type transistor N1 is connected to the input terminal Vin of the second integrator 7, the gate of the second N-type transistor N2 is connected to the output terminal of the first nor gate 2021, and the drain of the second N-type transistor N2 is connected to the input terminal Vip of the first integrator 6;
and, the second controllable switching circuit comprises: a third P-type transistor P3, a fourth P-type transistor P4, a third N-type transistor N3, and a fourth N-type transistor N4, the second side current source including a second side first sub-current source IDACN1 and a second side second sub-current source IDACN 2;
the sources of the third P-type transistor P3 and the fourth P-type transistor P4 are both connected to the output terminal of the first sub-current source IDACN1 on the second side, the gate of the third P-type transistor P3 is connected to the output terminal of the fourth nand gate 2014, the drain of the third P-type transistor P3 is connected to the input terminal Vip of the first integrator 6, the gate of the fourth P-type transistor P4 is connected to the output terminal of the third nand gate 2013, and the drain of the fourth P-type transistor P4 is connected to the input terminal Vin of the second integrator 7;
the sources of the third N-type transistor N3 and the fourth N-type transistor N4 are both connected to the input terminal of the second sub-current source IDACN2 on the second side, the gate of the third N-type transistor N3 is connected to the output terminal of the fourth nor gate 2024, the drain of the third N-type transistor N3 is connected to the input terminal Vip of the first integrator 6, the gate of the fourth N-type transistor N4 is connected to the output terminal of the third nor gate 2023, and the drain of the fourth N-type transistor N4 is connected to the input terminal Vin of the second integrator 7.
In the audio power amplifier provided by the embodiment of the present application shown in fig. 7, an input terminal of the first sub-current source acp1 on the first side is connected to a power signal, and an output terminal of the second sub-current source acp2 on the first side is connected to a ground terminal; the input end of the first sub-current source IDACN1 on the second side is connected to the power signal, and the output end of the second sub-current source IDACN2 on the second side is connected to the ground terminal. Wherein, the alternating driving of the operation state of the main driving circuit, i.e. the alternating driving of the first main state and the second main state, is completed by the state control signal PWM _ CTRL being at a low level or a high level; specifically, when the state control signal is at a high level, the main driving circuit operates in a first main state, the first logic conversion circuit controls the first controllable switch circuit to connect the first side current source with the input end of the first integrator, and the second logic conversion circuit controls the second controllable switch circuit to connect the second side current source with the input end of the second integrator; referring to fig. 7, when the state control signal PWM _ CTRL is at a high level, whether the PWMP signal and the PWMN signal are at a high level or a low level, the first logic conversion circuit can only control the conduction of the second P-type transistor P2 or the second N-type transistor N2 through logic gates, so as to connect the first side current source to the input Vip of the first integrator, and the second logic conversion circuit can only control the conduction of the fourth P-type transistor P4 or the fourth N-type transistor N4 through logic gates, so as to connect the second side current source to the input Vin of the second integrator;
when the state control signal is at a low level, the main driving circuit operates in a second main state, the first logic conversion circuit controls the first controllable switch circuit to communicate the first side current source with the input end of the second integrator, and the second logic conversion circuit controls the second controllable switch circuit to communicate the second side current source with the input end of the first integrator; referring to fig. 7, when the state control signal PWM _ CTRL is at a low level, no matter whether the PWMP signal and the PWMN signal are at a high level or a low level, the first logic conversion circuit can only control the conduction of the first P-type transistor P1 or the first N-type transistor N1 through the logic gate, so as to communicate the first side current source with the input terminal Vin of the second integrator, and the second logic conversion circuit can only control the conduction of the third P-type transistor P3 or the third N-type transistor N3 through the logic gate, so as to communicate the second side current source with the input terminal Vip of the first integrator, so that the main driving circuit finally implements the alternate driving of the operating state of the main driving circuit, that is, the alternate driving of the first main state and the second main state, according to the state control signal PWM _ CTRL being at a low level or a high level.
Referring to fig. 7, the second control signal and the third control signal are signals output by the state control signals PWM _ CTRL and PWMN after being converted by the logic gate circuit, and used for controlling the corresponding first controllable switch or the second controllable switch; and the first control signal and the fourth control signal are signals which are output after the state control signals PWM _ CTRL and PWMP signals are converted through the logic gate circuit and are used for controlling the corresponding first controllable switch or second controllable switch.
The specific operation process and the specific parameter performance of the digital audio power amplifier provided by the embodiment of the present application are analyzed in conjunction with fig. 2 to 8.
Fig. 4 is a schematic structural diagram of the common mode voltage generating module, wherein the reference voltage VREF is a half of the working voltage VDD output by the working voltage terminal. Take the first integrator as an example, when the first productWhen the output end Vop of the divider is "1" (i.e. when the output end Vop is connected with the power supply PVDD), the first capacitor C1 is charged by the feedback resistor Rfb and the first auxiliary current source (the auxiliary pull current of the first auxiliary current source is Isnk1) with a current IFB1_a(ii) a When the output terminal Vop of the first integrator is "0" (i.e., the output terminal Vop is connected to the ground), a discharge current I is provided to the first capacitor C1 through the feedback resistor Rfb and the first auxiliary current source (the auxiliary pull current of the first auxiliary current source is Isnk1)FB1_b(ii) a Wherein, PVDD is the voltage of the power supply:
let IFB＝IFB1_a＝IFB1_b
Figure BDA0002295669000000161
Figure BDA0002295669000000162
It is possible to obtain:
Figure BDA0002295669000000163
referring to fig. 3 and 8, fig. 8 is a waveform diagram of charging and discharging of the first capacitor, and the relationship between the input duty ratio and the output is analyzed by taking the first integrator as an example. The charging and discharging of the first capacitor C1 of the first integrator in one period are divided into 4 stages; ic1 is the charging/discharging current of the first capacitor C1, and Vc1 is the voltage of the first capacitor C1.
Stage T1: PWMP being "1", the output terminal V of the first integratorOP1', the first side current source (current value is I)DAC) The first capacitor C1 is charged, and the output signal of the digital audio power amplifier passes through the branch of the feedback resistor Rfb and the first auxiliary current source (the branch current value is I)FB) Charging the first capacitor C1:
IC1_T1＝IDAC+IFB；
stage T2: PWMP being "1", the output terminal V of the first integratorOP0', the first side current source (current value is I)DAC) The first capacitor C1 is charged, and the output signal of the digital audio power amplifier passes through the branch of the feedback resistor Rfb and the first auxiliary current source (the branch current value is I)FB) Discharge the first capacitor C1:
IC1_T2＝IDAC-IFB；
stage T3: PWMP being "0", the output terminal V of the first integratorOP0', the first side current source (current value is I)DAC) The output signal of the digital audio power amplifier is discharged from the first capacitor C1, and passes through the branch of the feedback resistor Rfb and the first auxiliary current source (the branch current value is I)FB) Discharge the first capacitor C1:
IC1_T3＝-IDAC-IFB；
stage T4: PWMP is equal to "0", and the output signal V of the first integrator 6OP1', the first side current source (current value is I)DAC) The output signal of the digital audio power amplifier is discharged from the first capacitor C1, and passes through the branch of the feedback resistor Rfb and the first auxiliary current source (the branch current value is I)FB) Charging the first capacitor C1:
IC1_T4＝-IDAC+IFB；
during normal operation, the charge and discharge balance of the first capacitor C1 includes:
IC1_T1×t1+IC1_T2×t2＝-IC1_T3×t3-IC1_T4×t4
will IC1_T1～4Can be obtained by substituting the formula and finishing
IDAC×(t1+t2)-IDAC×(t3+t4)＝IFB×(t2+t3)-IFB×(t1+t4)
Wherein, t1+t2＝DIN×T，t3+t4＝(1-DIN)×T，t1+t4＝DOUT×T，t2+t3＝(1-DOUT)×T；Wherein T is the period, DINIndicating the duty cycle of the input PWMP signal, DOUTThe duty ratio of an output signal of the audio power amplifier is defined;
finishing to obtain:
Figure BDA0002295669000000181
Figure BDA0002295669000000182
the output end Vop of the first integrator satisfies:
VOP＝DOUT*PVDD
Figure BDA0002295669000000183
the above formula shows that the Vop signal at the output of the first integrator is a common-mode point of 1/2 × PVDD with 50% input duty cycle DINA central signal. Therefore, the gain of the digital audio power amplifier is 2 Rfb IDAC。
According to the digital audio power amplifier provided by the embodiment of the application, the corresponding auxiliary source current is provided for the input end of the corresponding integrator through the first auxiliary current source and the second auxiliary current source, the requirement for the reference voltage involved in the integrator is large when the output voltage of the digital audio power amplifier is high is reduced, and the situation that the corresponding power amplifier loops of the first side current source, the second side current source and the integrator do not have enough voltage margin to support the normal work of a circuit is avoided.
Secondly, when the main driving circuit is in a first main state, controlling a first side current source to provide current for the input end of a first integrator according to a PWMP signal, and controlling a second side current source to provide current for the input end of a second integrator according to a PWMN signal; and when the main driving circuit is in the second main state, the second side current source is controlled to provide current for the input end of the first integrator according to the PWMP signal, the first side current source is controlled to provide current for the input end of the second integrator according to the PWMN signal, and the first main state and the second main state of the main driving circuit alternately operate, so that the currents provided for the first integrator and the second integrator are the average value of the currents of the first side current source and the second side current source, the influence on the current provided for the integrator due to the process deviation of the current sources is improved, the difference of the voltages respectively provided for the audio load by the first integrator and the second integrator is reduced, the direct-current offset voltage is eliminated, and the sound production effect of the audio load is ensured to be excellent.
In addition, the first auxiliary current source provides a first auxiliary source current for the input end of the first integrator when the auxiliary driving circuit is in a first auxiliary state, and the second auxiliary current source provides a second auxiliary source current for the input end of the second integrator; and when the driving circuit is in the second auxiliary state, the first auxiliary current source provides a first auxiliary source current for the input end of the second integrator, the second auxiliary current source provides a second auxiliary source current for the input end of the first integrator, and then the first auxiliary state and the second auxiliary state of the driving circuit alternately operate to enable the first auxiliary current source and the second auxiliary current source to alternately provide the auxiliary source currents for the input end of the first integrator and the second integrator respectively, so that the situation that the power supply rejection ratio is reduced due to non-ideal factors such as mismatch of manufacturing processes of the first auxiliary current source and the second auxiliary current source is avoided.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (13)

1. A digital audio power amplifier, comprising: the digital modulator comprises a D-type digital modulator, a first side current source, a second side current source, a main driving circuit, a first auxiliary current source, a second auxiliary current source, an auxiliary driving circuit, a first integrator and a second integrator;
the D-type digital modulator is used for converting the received audio digital signal into a PWMP signal and a PWMN signal;
the main driving circuit comprises a first main state and a second main state which are operated alternately, wherein when the main driving circuit is in the first main state, the main driving circuit controls a first side current source to provide a first source current or a first sink current for the input end of a first integrator according to the PWMP signal, and controls a second side current source to provide a second source current or a second sink current for the input end of a second integrator according to the PWMN signal; when the main drive circuit is in the second main state, the main drive circuit controls the second side current source to provide a second source current or a second sink current for the input end of the first integrator according to the PWMP signal, and controls the first side current source to provide a first source current or a first sink current for the input end of the second integrator according to the PWMN signal;
and the auxiliary drive circuit comprises a first auxiliary state and a second auxiliary state which are operated alternately, wherein when the auxiliary drive circuit is in the first auxiliary state, the auxiliary drive circuit controls the first auxiliary current source to provide a first auxiliary source current for the input end of the first integrator, and controls the second auxiliary current source to provide a second auxiliary source current for the input end of the second integrator; and when the auxiliary driving circuit is in the second auxiliary state, the auxiliary driving circuit controls the first auxiliary current source to provide the first auxiliary source current for the input end of the second integrator, and controls the second auxiliary current source to provide the second auxiliary source current for the input end of the first integrator.
2. The digital audio power amplifier of claim 1, wherein any one of the first integrator and the second integrator comprises: the power amplifier comprises a first operational amplifier, a common-mode voltage generation module, a first capacitor, a feedback resistor, a power amplifier loop driving module, a first auxiliary P-type transistor and a first auxiliary N-type transistor;
the inverting terminal of the first operational amplifier is the input terminal of the integrator, the inverting terminal of the first operational amplifier, the first polar plate of the first capacitor and the first terminal of the feedback resistor are all connected, the non-inverting terminal of the first operational amplifier is connected with the output terminal of the common-mode voltage generating module, the common-mode voltage generating module is used for outputting a reference voltage, and the output terminal of the first operational amplifier, the second polar plate of the first capacitor and the input terminal of the power amplifier loop driving module are all connected;
a first output end of the power amplifier loop driving module is connected with a grid electrode of the first auxiliary P-type transistor, and a second output end of the power amplifier loop driving module is connected with a grid electrode of the first auxiliary N-type transistor;
the source electrode of the first auxiliary P-type transistor is connected with a power supply, the source electrode of the first auxiliary N-type transistor is connected with a grounding end, and the drain electrode of the first auxiliary P-type transistor, the drain electrode of the first auxiliary N-type transistor and the second end of the feedback resistor are connected into the output end of the integrator.
3. The digital audio power amplifier of claim 2, wherein the common mode voltage generating module comprises: the circuit comprises a first resistor, a second resistor, a third resistor and a second capacitor;
the first end of the first resistor is connected with a working voltage end, and the second end of the first resistor, the first end of the second resistor and the first end of the third resistor are all connected;
the second end of the second resistor and the second polar plate of the second capacitor are both connected with a ground terminal;
and the second end of the third resistor and the first polar plate of the second capacitor are connected as the output end of the common-mode voltage generation module.
4. The digital audio power amplifier of claim 3, wherein the reference voltage is half of an operating voltage of the operating voltage terminal.
5. The digital audio power amplifier of claim 2, wherein the auxiliary drive circuit is further configured to control a feedback resistance of the first integrator and a feedback resistance of the second integrator to be interchanged when the first auxiliary state and the second auxiliary state are alternately operated.
6. The digital audio power amplifier of claim 5, wherein the auxiliary drive circuit comprises: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch, wherein the first switch, the second switch, the third switch, and the fourth switch are on in the first assist state and off in the second assist state, and the fifth switch, the sixth switch, the seventh switch, and the eighth switch are off in the first assist state and on in the second assist state;
the first switch is connected between the input end of the first integrator and the output end of the first auxiliary current source, the output end of the first auxiliary current source is connected with the first end of the feedback resistor of the first integrator, and the second switch is connected between the second end of the feedback resistor of the first integrator and the output end of the first integrator;
the third switch is connected between the input end of the second integrator and the output end of the second auxiliary current source, the output end of the second auxiliary current source is connected with the first end of the feedback resistor of the second integrator, and the fourth switch is connected between the second end of the feedback resistor of the second integrator and the output end of the second integrator;
the fifth switch is connected between the input terminal of the first integrator and the output terminal of the second auxiliary current source, and the sixth switch is connected between the second terminal of the feedback resistor of the second integrator and the output terminal of the first integrator;
the seventh switch is connected between the input terminal of the second integrator and the output terminal of the first auxiliary current source, and the eighth switch is connected between the second terminal of the feedback resistor of the first integrator and the output terminal of the second integrator.
7. The digital audio power amplifier of claim 2, wherein any one of the first auxiliary current source and the second auxiliary current source comprises: the second operational amplifier, the fourth resistor, the second auxiliary N-type transistor and the third auxiliary N-type transistor;
the inverting terminal of the second operational amplifier is connected with the working voltage terminal, the non-inverting terminal of the second operational amplifier, the second terminal of the fourth resistor and the drain electrode of the second auxiliary N-type transistor are all connected, and the output terminal of the second operational amplifier, the grid electrode of the second auxiliary N-type transistor and the grid electrode of the third auxiliary N-type transistor are all connected;
the first end of the fourth resistor is connected with the power supply;
and the source electrode of the second auxiliary N-type transistor and the source electrode of the third auxiliary N-type transistor are both connected with a grounding end, and the drain electrode of the third auxiliary N-type transistor is the output end of the auxiliary current source.
8. The digital audio power amplifier of claim 7, wherein the second operational amplifier of the first auxiliary current source and the second operational amplifier of the second auxiliary current source are the same operational amplifier;
the fourth resistor of the first auxiliary current source and the fourth resistor of the second auxiliary current source are the same resistor;
and the second auxiliary N-type transistor of the first auxiliary current source and the second auxiliary N-type transistor of the second auxiliary current source are the same N-type transistor.
9. The digital audio power amplifier of claim 7, wherein the fourth resistor has a resistance value twice that of the feedback resistor;
and the width-to-length ratios of the second auxiliary N-type transistor and the third auxiliary N-type transistor are the same.
10. The digital audio power amplifier of claim 1, wherein the main drive circuit comprises: the first logic conversion circuit, the second logic conversion circuit, the first controllable switch circuit and the second controllable switch circuit;
the first logic conversion circuit is connected with the first controllable switch circuit, is accessed to the PWMP signal and the PWMN signal, and is configured to convert the PWMP signal and the PWMN signal into a first control signal in the first master state, so as to control the first controllable switch circuit to connect the first side current source with the input terminal of the first integrator; the second logic conversion circuit is connected with the second controllable switch circuit, is accessed to the PWMP signal and the PWMN signal, and is used for converting the PWMP signal and the PWMN signal into a second control signal in the first main state so as to control the second controllable switch circuit to connect the second side current source with the input end of the second integrator;
and in the second master state, the first logic conversion circuit is configured to convert the PWMP signal and the PWMN signal into a third control signal to control the first controllable switch circuit to connect the first side current source to the input terminal of the second integrator; and the second logic conversion circuit is used for converting the PWMP signal and the PWMN signal into a fourth control signal so as to control the second controllable switch circuit to connect the second side current source with the input end of the first integrator.
11. The digital audio power amplifier of claim 10, wherein the first logic conversion circuit performs logic operation control on the PWMP signal and the PWMN signal through a logic gate circuit to output the first control signal in the first main state and output the third control signal in the second main state;
and/or the second logic conversion circuit performs logic operation control on the PWMP signal and the PWMN signal through a logic gate circuit, and outputs the second control signal in the first main state and the fourth control signal in the second main state.
12. The digital audio power amplifier of claim 10, wherein the first logic conversion circuit comprises: the first NAND gate, the second NAND gate, the first NOR gate, the second NOR gate and the first inverter;
the output ends of the first nand gate, the second nand gate, the first nor gate and the second nor gate are all connected with the first controllable switch circuit, one input ends of the first nand gate and the second nor gate and the input end of the first inverter are all connected with a main state control signal, one input ends of the second nand gate and the first nor gate are all connected with the output end of the first inverter, the other input ends of the first nand gate and the first nor gate are all connected with the PWMP signal, and the other input ends of the second nand gate and the second nor gate are all connected with the PWMN signal;
and, the second logic conversion circuit includes: the first NAND gate, the second NAND gate, the third NOR gate, the fourth NOR gate and the second inverter;
the output ends of the third nand gate, the fourth nand gate, the third nor gate and the fourth nor gate are all connected with the second controllable switch circuit, one input ends of the third nand gate and the fourth nor gate and the input ends of the second phase inverter are all connected with a master state control signal, one input ends of the fourth nand gate and the third nor gate are all connected with the output end of the second phase inverter, the other input ends of the third nand gate and the third nor gate are all connected with the PWMN signal, and the other input ends of the fourth nand gate and the fourth nor gate are all connected with the PWMP signal.
13. The digital audio power amplifier of claim 12, wherein the first controllable switch circuit comprises: the first side current source comprises a first sub current source at a first side and a second sub current source at the first side;
the sources of the first P-type transistor and the second P-type transistor are both connected to the output end of the first sub-current source on the first side, the gate of the first P-type transistor is connected to the output end of the second nand gate, the drain of the first P-type transistor is connected to the input end of the second integrator, the gate of the second P-type transistor is connected to the output end of the first nand gate, and the drain of the second P-type transistor is connected to the input end of the first integrator;
the source electrodes of the first N-type transistor and the second N-type transistor are both connected with the input end of the second sub-current source on the first side, the grid electrode of the first N-type transistor is connected with the output end of the second NOR gate, the drain electrode of the first N-type transistor is connected with the input end of the second integrator, the grid electrode of the second N-type transistor is connected with the output end of the first NOR gate, and the drain electrode of the second N-type transistor is connected with the input end of the first integrator;
and, the second controllable switching circuit comprises: the second side current source comprises a first sub current source at a second side and a second sub current source at the second side;
the source electrodes of the third P-type transistor and the fourth P-type transistor are both connected to the output end of the first sub-current source on the second side, the gate electrode of the third P-type transistor is connected to the output end of the fourth nand gate, the drain electrode of the third P-type transistor is connected to the input end of the first integrator, the gate electrode of the fourth P-type transistor is connected to the output end of the third nand gate, and the drain electrode of the fourth P-type transistor is connected to the input end of the second integrator;
the source electrodes of the third N-type transistor and the fourth N-type transistor are connected with the input end of the second sub-current source on the second side, the grid electrode of the third N-type transistor is connected with the output end of the fourth NOR gate, the drain electrode of the third N-type transistor is connected with the input end of the first integrator, the grid electrode of the fourth N-type transistor is connected with the output end of the third NOR gate, and the drain electrode of the fourth N-type transistor is connected with the input end of the second integrator.
CN201911200149.3A 2019-11-29 2019-11-29 Digital audio power amplifier Pending CN110957984A (en)

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CN108736848A (en) * 2018-08-20 2018-11-02 上海艾为电子技术股份有限公司 A kind of digital audio frequency power amplifier and electronic equipment
CN109068240A (en) * 2018-08-27 2018-12-21 上海艾为电子技术股份有限公司 A kind of digital audio power amplification system
CN109068241A (en) * 2018-08-27 2018-12-21 上海艾为电子技术股份有限公司 A kind of digital audio power amplification system
CN109660917A (en) * 2018-12-26 2019-04-19 上海艾为电子技术股份有限公司 A kind of high-voltage digital audio power amplification system
CN109688514A (en) * 2018-12-26 2019-04-26 上海艾为电子技术股份有限公司 A kind of high-voltage digital audio power amplification system

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CN108736848A (en) * 2018-08-20 2018-11-02 上海艾为电子技术股份有限公司 A kind of digital audio frequency power amplifier and electronic equipment
CN109068240A (en) * 2018-08-27 2018-12-21 上海艾为电子技术股份有限公司 A kind of digital audio power amplification system
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