CN110943738A - Inductance-capacitance voltage-controlled oscillator with adjustable common-mode voltage of output clock - Google Patents
Inductance-capacitance voltage-controlled oscillator with adjustable common-mode voltage of output clock Download PDFInfo
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Abstract
The invention discloses an inductance-capacitance voltage-controlled oscillator with adjustable output clock common-mode voltage, which comprises: the power pad, the band gap circuit, the LDO circuit, the bias circuit and the LCVCO circuit; the input end of the PowerPad is connected with an external power supply, and the output end of the PowerPad is connected with the input end of the band gap circuit, the input end of the LDO circuit and the source electrode of the oscillator current tube; the output end of the band gap circuit is connected with the input end of the LDO circuit; the output end of the LDO circuit is connected with the input end of the biasing circuit; the input end of the bias circuit is connected with the first differential signal and the second differential signal, and the output end of the bias circuit is connected with the grid electrode of the oscillator current tube; the LCVCO circuit is connected with the drain electrode of the oscillator current tube. The invention can effectively reduce the phase noise of the inductance-capacitance voltage-controlled oscillator on the premise of not obviously increasing the power supply and the power consumption, and simultaneously adjust the common-mode voltage of the output clock of the oscillator to ensure that the power consumption and the area of the phase-locked loop meet the design requirements.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to an inductance-capacitance voltage-controlled oscillator with adjustable output clock common-mode voltage.
Background
Phase Locked Loops (PLLs) are widely used in electronic design, and in radio frequency communication systems, a Phase Locked Loop (PLL) is a very critical module and is widely used to provide stable frequency for transceivers. The rf pll circuit generally comprises a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider. Because the phase noise performance is good, an inductance-capacitance voltage controlled oscillator (LCVCO) is widely used in a radio frequency phase-locked loop (PLL) circuit, the phase noise and the oscillation starting speed of the LCVCO are important performances of the PLL, particularly in low-jitter clock applications such as high-speed data transmission and the like, the VCO is a main contribution part of noise, and the noise performance directly influences the jitter of the PLL clock. How to reduce the phase noise under the conditions of small area and low power consumption becomes the key of circuit design.
A conventional LCVCO circuit is shown in fig. 1, but since noise existing in the power supply and ground is directly coupled into the circuit, resulting in poor VCO phase noise performance, and VCO phase noise is a major contribution in the phase-locked loop, how to reduce the LCVCO phase noise becomes a key of circuit design. One way to reduce phase noise is to use the LDO to power the LCVCO, as shown in fig. 2, to isolate noise on the power supply through the LDO, but since the LCVCO needs to draw a large current from the power supply when operating normally, the use of the LDO to power it increases extra power consumption. There is also a circuit for reducing phase noise by filtering, as shown in fig. 3, and it is analyzed from the circuit that the current source will introduce considerable phase noise to the oscillator, and for a current source of a voltage controlled oscillator: 1) as for the thermal noise in the vicinity of the second harmonic, phase noise is caused; 2) the current source end only needs to have high impedance at the frequency of the second harmonic; therefore, adding a narrow band circuit to the current source reduces the oscillator phase noise, as shown in fig. 2, C1 can short-circuit the second harmonic noise to ground, and to increase the impedance, an inductor L3 is added between the current source and M1, M2, where the inductor and capacitor oscillate. Although this structure can effectively reduce the phase noise of the oscillator, the introduction of the inductance module requires a considerable increase in area.
With the increasing of the frequency of the output clock of the phase-locked loop, the swing amplitude is gradually reduced, and the temperature and the angle are changed, on the premise of ensuring the stability of the output frequency, how to correctly identify the high and low levels of the output clock by a subsequent circuit is also a key of the design, and in a traditional circuit, an additional shaping circuit is usually added at the output end of an oscillator to ensure the normal work of the output clock, so that not only is the additional area increased, but also the additional power consumption is increased.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide the inductance-capacitance voltage-controlled oscillator with the adjustable output clock common-mode voltage, which can effectively reduce the phase noise of the inductance-capacitance voltage-controlled oscillator on the premise of ensuring that the power supply and the power consumption are not obviously increased, and meanwhile, the output clock common-mode voltage of the oscillator is adjusted, so that the power consumption and the area of a phase-locked loop meet the design requirements.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
an lc voltage controlled oscillator with adjustable output clock common mode voltage, the lc voltage controlled oscillator comprising: the power pad, the band gap circuit, the LDO circuit, the bias circuit and the LCVCO circuit;
the input end of the PowerPad is connected with an external power supply, and the output end of the PowerPad is connected with the input end of the band gap circuit, the input end of the LDO circuit and the source electrode of the oscillator current tube;
the output end of the band gap circuit is connected with the input end of the LDO circuit;
the output end of the LDO circuit is connected with the input end of the bias circuit;
the input end of the bias circuit is connected with the first differential signal and the second differential signal, and the output end of the bias circuit is connected with the grid electrode of the oscillator current tube;
the LCVCO circuit is connected with the drain electrode of the oscillator current tube.
Further, an lc voltage controlled oscillator with adjustable common-mode voltage of output clocks as described above, the bias circuit comprising: the circuit comprises voltage dividing resistors R1 and R2, a bias resistor R3, an RC filter resistor R4, an RC filter capacitor C1, a current mirror tube, an enable tube NM6, a common-mode voltage control tube NM5 and an input tube; the current mirror tube includes: NMOS transistors NM1 and NM2, NM3 and NM4, PMOS transistors PM1 and PM2, PM3 and PM 4; the input tube includes: NMOS transistors NM7 and NM 8;
the positive end of the R1 is connected with a power supply provided by the LDO circuit, and the negative end of the R1 is connected with the positive ends of the R2 and the R4; the positive terminal of the R3 is connected to the power supply, the negative terminal is connected to the gate and drain of the NM1, the gate of the NM 2; the sources of the NM1, NM2, NM3 and NM4 are grounded, and the sources of the PM1, PM2, PM3 and PM4 are connected with a power supply; the drain of the NM2 is connected with the sources of the NM5, NM7 and NM 8; the positive end of the C1 is connected with the negative end of the R4 and the grid of the NM5, and the negative end is connected with the output end of the bias circuit; the gate and the drain of the PM1 are both connected to the gate of the PM2 and the drain of the NM 5; the drain of the PM2 is connected with the drain and the gate of the NM3 and the gate of the NM 4; the drain of the NM4 is connected with the source of the NM6 and the output end of the bias circuit; the gate of the PM3 is connected with the drains of the PM4, NM7 and NM8, and the drain of the PM3 is connected with the drain of the NM 6; the gate and the drain of the PM4 are both connected with the gate of the PM 3; a gate of the NM6 is connected to an enable signal, a gate of the NM7 is connected to the first differential signal, and a gate of the NM8 is connected to the second differential signal.
Further, according to the LC voltage-controlled oscillator with the adjustable common-mode voltage of the output clock, the oscillator current tube is a PMOS tube.
Further, as to the lc voltage controlled oscillator with adjustable common-mode voltage of the output clock, the enable transistor NM6 and the common-mode voltage control transistor NM5 are NMOS transistors.
Further, as described above, the output clock common-mode voltage adjustable lc-vco, the LDO circuit is configured to suppress noise of an external power supply input by the PowerPad and provide the suppressed power supply to the bias circuit.
Further, an lc voltage controlled oscillator with adjustable common-mode voltage of output clocks as described above, wherein the bias circuit is configured to:
the voltage of the power supply which is connected is divided by the voltage dividing resistors R1 and R2, the divided voltage is supplied to the grid electrode of the common mode voltage control tube NM5 through an RC filter circuit consisting of R4 and C1, the NM5 is conducted, and meanwhile, a high-frequency fluctuation signal in the divided voltage is filtered through the RC filter circuit.
Further, an lc voltage controlled oscillator with adjustable common-mode voltage of output clocks as described above, wherein the bias circuit is configured to:
forming a current through the R3 and the NM1, mirroring the current through the NM1 and NM2 into two branches of the NM2, one of which is mirrored through the PM3, PM4 into an output terminal of the bias circuit after a part of the current flowing through the NM2 flows to the NM5, PM1 respectively through the PM1, PM2 into the PM2 branch and the PM3 branch when the enable signal is enabled; in another aspect, another part of the current flowing through the NM2 is mirrored to the output terminal of the bias circuit through the PM3 and the PM4 after passing through the NM7, NM8 and PM 4; and the voltage signal at the output end of the bias circuit provides bias voltage for the LCVCO circuit after being mirrored so as to reduce the phase noise of the LC VCO.
Further, as for the LC voltage-controlled oscillator with adjustable output clock common-mode voltage, the bias circuit is also used for adjusting the output clock common-mode voltage.
Further, as described above, the lc voltage-controlled oscillator with an adjustable common-mode voltage of the output clock, the bias circuit is specifically configured to:
when the LCVCO circuit starts oscillation, a common-mode voltage V1 of the first differential signal and the second differential signal generates an impedance R1 after passing through the NM7 and NM8, a voltage V2 obtained by dividing the voltage by the voltage dividing resistors R1 and R2 generates an impedance R2 after passing through the NM5, and if V1 is equal to V2, the current value flowing through the NM5 and PM1 is the same as the current value flowing through the NM7, NM8 and PM 4;
when V1 is smaller than V2, r1 is larger than r2, the currents passing through NM7, NM8 and PM4 are reduced, the currents mirrored through PM3 and PM4 are correspondingly reduced, the currents mirrored to PM2 and NM3 after passing through PM5 and PM1 are correspondingly increased, the currents mirrored through NM3 and NM4 are correspondingly increased, the output voltage of the output end of the bias circuit is reduced, the current of the oscillator current tube controlled by the output voltage is increased, and the common-mode voltage V1 is increased until V1 and V63 2 are equal.
Further, as described above, the lc voltage-controlled oscillator with an adjustable common-mode voltage of the output clock, the bias circuit is specifically configured to:
when V1 is greater than V2, r1 is less than r2, the current passing through NM7, NM8 and PM4 is increased, the current after mirror image of PM3 and PM4 is correspondingly increased, the current after mirror image of PM5 and PM1 is correspondingly decreased to PM2 and NM3, the current after mirror image of NM3 and NM4 is correspondingly decreased, the output voltage of the output end of the bias circuit is increased, the current of the oscillator current tube controlled by the output voltage is decreased, and the common mode voltage V1 is decreased until V1 and V63 2 are equal.
The invention has the beneficial effects that: the invention can effectively reduce the phase noise of the inductance-capacitance voltage-controlled oscillator on the premise of not obviously increasing the power supply and the power consumption, and simultaneously adjust the common-mode voltage of the output clock of the oscillator to ensure that the power consumption and the area of the phase-locked loop meet the design requirements. The bias circuit supplies power through the LDO, carries out noise isolation through the LDO, can reduce the noise that introduces through oscillator current tube grid, and this kind of circuit structure is for the structure that the tradition was directly supplied power by the LDO to the oscillator, and phase noise performance differs little, and owing to still supply power by low voltage power supply, its consumption can the greatly reduced consumption for directly supplying power from high voltage power supply.
Drawings
Fig. 1 is a circuit diagram of a conventional LC oscillator provided in an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an oscillator for supplying power to the LDO provided in the embodiment of the present invention;
fig. 3 is a schematic diagram of an oscillator with an LC filter structure according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an lc voltage-controlled oscillator with an adjustable common-mode voltage of an output clock according to an embodiment of the present invention;
fig. 5 is a schematic diagram of the bias circuit in fig. 4.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
Aiming at various technical problems mentioned in the background technology, the invention provides a design method of an LCVCO (capacitor controlled oscillator voltage control oscillator) bias circuit, which can effectively reduce the phase noise of an inductance-capacitance voltage controlled oscillator (LCVCO) on the premise of ensuring that the power supply and the power consumption are not obviously increased, and simultaneously adjust the common-mode voltage of an oscillator output clock, and ensure that the power consumption and the area of a phase-locked loop meet the design requirements.
As shown in fig. 4, an lc voltage controlled oscillator with adjustable common-mode voltage of output clock includes: PowerPad, bandgap circuit (BG), LDO circuit, Bias circuit (Bias), and LCVCO circuit;
the input end of the PowerPad is connected with an external power supply, and the output end of the PowerPad is connected with the input end of the band gap circuit, the input end of the LDO circuit and the source electrode of the oscillator current tube;
the output end of the band gap circuit is connected with the input end of the LDO circuit;
the output end of the LDO circuit is connected with the input end of the biasing circuit;
the input end of the bias circuit is connected with the first differential signal and the second differential signal, and the output end of the bias circuit is connected with the grid electrode of the oscillator current tube;
the LCVCO circuit is connected with the drain electrode of the oscillator current tube.
As shown in fig. 5, the bias circuit includes: the circuit comprises voltage dividing resistors R1 and R2, a bias resistor R3, an RC filter resistor R4, an RC filter capacitor C1, a current mirror tube, an enable tube NM6, a common-mode voltage control tube NM5 and an input tube; the current mirror image tube includes: NMOS transistors NM1 and NM2, NM3 and NM4, PMOS transistors PM1 and PM2, PM3 and PM 4; the input tube includes: NMOS transistors NM7 and NM 8;
the positive end of the R1 is connected with a power supply provided by the LDO circuit, and the negative end of the R1 is connected with the positive ends of the R2 and the R4; the positive end of R3 is connected with the power supply, the negative end is connected with the grid and the drain of NM1 and the grid of NM 2; the sources of NM1, NM2, NM3 and NM4 are grounded, and the sources of PM1, PM2, PM3 and PM4 are connected with a power supply; the drain of NM2 is connected with the sources of NM5, NM7 and NM 8; the positive end of the C1 is connected with the negative end of the R4 and the grid of the NM5, and the negative end is connected with the output end of the bias circuit; the gate and the drain of the PM1 are both connected with the gate of the PM2 and the drain of the NM 5; the drain of the PM2 is connected with the drain and the gate of the NM3 and the gate of the NM 4; the drain of NM4 is connected with the source of NM6 and the output end of the bias circuit; the gate of the PM3 is connected with the drains of the PM4, the NM7 and the NM8, and the drain is connected with the drain of the NM 6; the gate and the drain of the PM4 are both connected with the gate of the PM 3; a gate of the NM6 is connected to an enable signal, a gate of the NM7 is connected to a first differential signal, and a gate of the NM8 is connected to a second differential signal.
The oscillator current tube is a PMOS tube.
The enable tube NM6 and the common mode voltage control tube NM5 are NMOS tubes.
The LDO circuit is used for suppressing noise of an external power supply input by the PowerPad and providing the suppressed power supply for the bias circuit.
The bias circuit is used for:
the voltage of the accessed power supply is divided by the voltage dividing resistors R1 and R2, the divided voltage supplies power to the grid electrode of the common mode voltage control tube NM5 through an RC filter circuit consisting of R4 and C1, NM5 is conducted, and meanwhile high-frequency fluctuation signals in the divided voltage are filtered through the RC filter circuit.
The bias circuit is used for:
the current is formed through R3 and NM1, the current is mirrored into two branches of NM2 through NM1 and NM2, when an enable signal is enabled, a part of the current flowing through NM2 flows to NM5 and PM1 respectively, then is mirrored into a PM2 branch and a PM3 branch through PM1 and PM2, and is mirrored to the output end of the bias circuit through PM3 and PM 4; in the other part, the other part of the current flowing through the NM2 is mirrored to the output end of the bias circuit through the PM3 and the PM4 after passing through the NM7, NM8 and PM 4; the voltage signal of the output end of the bias circuit provides bias voltage to the LCVCO circuit after being mirrored so as to reduce the phase noise of the LC VCO.
The bias circuit is also used to adjust the output clock common mode voltage.
The bias circuit is specifically configured to:
when the LCVCO circuit starts to oscillate, a common-mode voltage V1 of the first differential signal and the second differential signal generates an impedance R1 after passing through NM7 and NM8, a voltage V2 obtained by dividing the voltage by voltage dividing resistors R1 and R2 generates an impedance R2 after passing through NM5, and if V1 is equal to V2, the current value flowing through NM5 and PM1 is the same as the current value flowing through NM7, NM8 and PM 4;
when V1 is smaller than V2, r1 is larger than r2, the current passing through NM7, NM8 and PM4 is reduced, the mirrored current passing through PM3 and PM4 is correspondingly reduced, the mirrored current passing through PM5 and PM1 is correspondingly increased to PM2 and NM3, the mirrored current passing through NM3 and NM4 is correspondingly increased, the output voltage Vdriver at the output end of the bias circuit is reduced, the current of a PMOS transistor (oscillator current transistor) controlled by the output voltage Vdriver is increased, and the common-mode voltage V1 is increased until V1 and V2 are equal, and then the common-mode signal is adjusted to V2;
when V1 is greater than V2, r1 is less than r2, the current passing through NM7, NM8 and PM4 increases, the mirrored current passing through PM3 and PM4 also increases correspondingly, the mirrored current passing through PM5 and PM1 decreases correspondingly to PM2 and NM3, the mirrored current passing through NM3 and NM4 also decreases correspondingly, the output voltage Vdriver at the output end of the bias circuit increases, the PMOS transistor current controlled by the output voltage Vdriver decreases, the common mode voltage V1 is reduced until V1 and V2 are equal, and at this time, the common mode signal is also adjusted to V2.
The bias circuit of the invention supplies power through an LDO (low dropout regulator), and noise isolation is carried out through the LDO, so that the noise introduced by the grid electrode of the tail current tube can be reduced.
On the basis of optimizing the phase noise of the oscillator, comparator circuits NM4, NM6 and PM3 are added, a bias circuit outputs bias voltage to adjust the current of an oscillator current tube, differential voltage signals vco _ m (first differential signal) and vco _ p (first differential signal) after the oscillator starts oscillation are used as input signals to participate in adjustment of the bias voltage signals output by the bias circuit, the comparator compares the common-mode voltages of the differential voltage signals vco _ m and vco _ p and the value of NM5 gate voltage to adjust the bias voltage, common-mode voltages of the vco _ m and the vco _ p are guaranteed to be the value of NM5 gate voltage, and the NM5 gate voltage value can be adjusted by adjusting resistance values of R1 and R2.
The design of the bias circuit reduces the phase noise of the oscillator on the premise of ensuring that the power consumption and the area are not additionally increased, and can effectively adjust the common-mode voltage value of the output clock and ensure the normal work of a subsequent circuit. The invention is not limited to the LC oscillator, and is also applicable to the oscillator composed of a partial tail current type ring-tap structure.
As shown in fig. 4, the power supply of the whole oscillator is a low-voltage external power supply, the external power supply simultaneously supplies power to BG (Band Gap) and the LDO circuit, BG provides a reference voltage for the LDO, the LDO provides a power supply for the bias circuit, and the bias circuit provides a bias voltage for the gate of the oscillator current tube.
Since an external power supply needs to supply power to different modules, much noise is inevitably coupled into the external power supply, and therefore, the power supply vreg _ vp after noise suppression is provided for the bias circuit through the high power supply rejection ratio of the LDO.
The structure of the bias circuit is shown in fig. 5, the LDO is used as a power supply of the bias circuit, noise of an external power supply can be suppressed through a high power supply rejection ratio of the LDO, voltage division is performed through resistors R1 and R2, the divided voltage supplies power to a gate of an NM5 tube through an RC low-pass filter circuit composed of R4 and C1, it is required to ensure that the voltage after voltage division by R1 and R2 makes NM5 conductive, and meanwhile, the RC low-pass filter circuit can filter out high-frequency fluctuation of the divided voltage generated by R1 and R2; the power supply forms current through R3 and NM1, the current mirrors the current to the NM2 branch through the left and right images of NM1 and NM2, the current is divided into two parts, when an enable signal EN enables, the current flowing through NM2 can respectively flow to NM5 and PM1 branches, then the current is mirrored to PM2 and PM3 branches through PM1 and PM2 mirroring tubes, and the current is mirrored to a Vride signal (bias voltage signal) of an output end through PM3 and PM 4; the other part of the current flowing through NM2 is mirrored to the Vdrive signal at the output end through PM3 and PM4 mirror tubes after flowing through NM7, NM8 and PM4, the Vdrive signal provides bias voltage for the oscillator current tube after being mirrored, and the phase noise of the oscillator is greatly reduced compared with the situation that the external power supply supplies power for the bias.
The bias circuit provides a "clean" bias voltage while also having the effect of adjusting the output clock common mode voltage. When the oscillator starts to oscillate, vco _ m and vco _ p are differential voltage signals, the impedance of the common-mode voltage V1 after passing through NM7 and NM8 is R1, and the impedance generated when the voltage value V2 after R1 and R2 divide the voltage acts on NM5 is R2. If V1 is equal to V2, the current flowing through NM5 and PM1 is the same as the current flowing through NM7, NM8 and PM 4.
When V1 is smaller than V2, r1 is larger than r2, the current passing through NM7, NM8 and PM4 is relatively reduced, the current after being mirrored through PM3 and PM4 is correspondingly reduced, meanwhile, the current after passing through PM5 and PM1 and being mirrored to PM2 and NM3 is correspondingly increased, the current after being mirrored through NM3 and NM4 is also correspondingly increased, and finally, the Vdriver voltage is reduced, so that the current of a PMOS transistor controlled by the Vdriver voltage is increased, the vco _ m and the vco _ p common-mode voltage V1 are improved, and finally, the values of the vco _ m, the vco _ p common-mode voltage V1 and a preset value V2 are equal; on the contrary, when the common-mode voltage V1 of the vco _ m and the vco _ p is higher than the preset value V2, the Vdriver voltage is increased, and the output clock common-mode voltage is reduced; and finally, the common-mode voltage of the output clock is adjusted.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (10)
1. An lc voltage controlled oscillator with adjustable output clock common mode voltage, comprising: the power pad, the band gap circuit, the LDO circuit, the bias circuit and the LCVCO circuit;
the input end of the PowerPad is connected with an external power supply, and the output end of the PowerPad is connected with the input end of the band gap circuit, the input end of the LDO circuit and the source electrode of the oscillator current tube;
the output end of the band gap circuit is connected with the input end of the LDO circuit;
the output end of the LDO circuit is connected with the input end of the bias circuit;
the input end of the bias circuit is connected with the first differential signal and the second differential signal, and the output end of the bias circuit is connected with the grid electrode of the oscillator current tube;
the LCVCO circuit is connected with the drain electrode of the oscillator current tube.
2. The LC VCO in accordance with claim 1, wherein said bias circuit comprises: the circuit comprises voltage dividing resistors R1 and R2, a bias resistor R3, an RC filter resistor R4, an RC filter capacitor C1, a current mirror tube, an enable tube NM6, a common-mode voltage control tube NM5 and an input tube; the current mirror tube includes: NMOS transistors NM1 and NM2, NM3 and NM4, PMOS transistors PM1 and PM2, PM3 and PM 4; the input tube includes: NMOS transistors NM7 and NM 8;
the positive end of the R1 is connected with a power supply provided by the LDO circuit, and the negative end of the R1 is connected with the positive ends of the R2 and the R4; the positive terminal of the R3 is connected to the power supply, the negative terminal is connected to the gate and drain of the NM1, the gate of the NM 2; the sources of the NM1, NM2, NM3 and NM4 are grounded, and the sources of the PM1, PM2, PM3 and PM4 are connected with a power supply; the drain of the NM2 is connected with the sources of the NM5, NM7 and NM 8; the positive end of the C1 is connected with the negative end of the R4 and the grid of the NM5, and the negative end is connected with the output end of the bias circuit; the gate and the drain of the PM1 are both connected to the gate of the PM2 and the drain of the NM 5; the drain of the PM2 is connected with the drain and the gate of the NM3 and the gate of the NM 4; the drain of the NM4 is connected with the source of the NM6 and the output end of the bias circuit; the gate of the PM3 is connected with the drains of the PM4, NM7 and NM8, and the drain of the PM3 is connected with the drain of the NM 6; the gate and the drain of the PM4 are both connected with the gate of the PM 3; a gate of the NM6 is connected to an enable signal, a gate of the NM7 is connected to the first differential signal, and a gate of the NM8 is connected to the second differential signal.
3. The LC VCO as in claim 1, wherein said oscillator current transistors are PMOS transistors.
4. The LC VCO in claim 2, wherein said enable transistor NM6 and said common mode voltage control transistor NM5 are NMOS transistors.
5. The LC VCO in claim 2, wherein said LDO circuit is configured to suppress noise of an external power supply at said PowerPad input and provide the suppressed power supply to said bias circuit.
6. The lc voltage controlled oscillator of claim 2, wherein the bias circuit is configured to:
the voltage of the power supply which is connected is divided by the voltage dividing resistors R1 and R2, the divided voltage is supplied to the grid electrode of the common mode voltage control tube NM5 through an RC filter circuit consisting of R4 and C1, the NM5 is conducted, and meanwhile, a high-frequency fluctuation signal in the divided voltage is filtered through the RC filter circuit.
7. The lc voltage controlled oscillator of claim 2, wherein the bias circuit is configured to:
forming a current through the R3 and the NM1, mirroring the current through the NM1 and NM2 into two branches of the NM2, one of which is mirrored through the PM3, PM4 into an output terminal of the bias circuit after a part of the current flowing through the NM2 flows to the NM5, PM1 respectively through the PM1, PM2 into the PM2 branch and the PM3 branch when the enable signal is enabled; in another aspect, another part of the current flowing through the NM2 is mirrored to the output terminal of the bias circuit through the PM3 and the PM4 after passing through the NM7, NM8 and PM 4; and the voltage signal at the output end of the bias circuit provides bias voltage for the LCVCO circuit after being mirrored so as to reduce the phase noise of the LC VCO.
8. The LC VCO in accordance with claim 3, wherein said bias circuit is further configured to adjust said output clock common mode voltage.
9. The lc vco of claim 8, wherein the bias circuit is specifically configured to:
when the LCVCO circuit starts oscillation, a common-mode voltage V1 of the first differential signal and the second differential signal generates an impedance R1 after passing through the NM7 and NM8, a voltage V2 obtained by dividing the voltage by the voltage dividing resistors R1 and R2 generates an impedance R2 after passing through the NM5, and if V1 is equal to V2, the current value flowing through the NM5 and PM1 is the same as the current value flowing through the NM7, NM8 and PM 4;
when V1 is smaller than V2, r1 is larger than r2, the currents passing through NM7, NM8 and PM4 are reduced, the currents mirrored through PM3 and PM4 are correspondingly reduced, the currents mirrored to PM2 and NM3 after passing through PM5 and PM1 are correspondingly increased, the currents mirrored through NM3 and NM4 are correspondingly increased, the output voltage of the output end of the bias circuit is reduced, the current of the oscillator current tube controlled by the output voltage is increased, and the common-mode voltage V1 is increased until V1 and V63 2 are equal.
10. The lc vco of claim 9, wherein the bias circuit is specifically configured to:
when V1 is greater than V2, r1 is less than r2, the current passing through NM7, NM8 and PM4 is increased, the current after mirror image of PM3 and PM4 is correspondingly increased, the current after mirror image of PM5 and PM1 is correspondingly decreased to PM2 and NM3, the current after mirror image of NM3 and NM4 is correspondingly decreased, the output voltage of the output end of the bias circuit is increased, the current of the oscillator current tube controlled by the output voltage is decreased, and the common mode voltage V1 is decreased until V1 and V63 2 are equal.
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